library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity pix_engine_bg is Port ( reset_n : in std_ulogic; clock : in std_ulogic; pix_x : in unsigned (9 downto 0); pix_y : in unsigned (8 downto 0); pix_r : out std_ulogic_vector (2 downto 0); pix_g : out std_ulogic_vector (2 downto 0); pix_b : out std_ulogic_vector (2 downto 0); rd_req : out std_ulogic; rd_ack : in std_ulogic; rd_addr : out std_ulogic_vector (17 downto 0); rd_data : in std_ulogic_vector (31 downto 0)); end pix_engine_bg; architecture Behavioral of pix_engine_bg is signal pix_addr : unsigned (18 downto 0); begin -- calculate address in ram addr_proc: process (clock, reset_n) variable dummy : unsigned (11 downto 0); begin if reset_n = '0' then pix_addr <= (others => '0'); elsif rising_edge(clock) then -- pix_addr <= (640 * pix_y) + pix_x; -- geht nicht, weil "640" zu "512" wird. siehe Definition von * in numeric_std!! -- pix_addr <= ((to_unsigned(640, 10) * pix_y)) + pix_x; -- 10 slices, 19 luts, 1 mul -- pix_addr <= (640 * ('0' & pix_y)) + pix_x; -- 10 slices, 19 luts, 1 mul -- pix_addr <= (pix_y & "0000000") + ('0' & pix_y & "000000000") + pix_x; -- 7 slices, 14 luts -- pix_addr <= ('0' & pix_y & "000000000") + (pix_y & "0000000") + pix_x; -- 7 slices, 14 luts -- pix_addr <= pix_x + ('0' & pix_y & "000000000") + (pix_y & "0000000"); -- 7 slices, 14 luts -- pix_addr <= ((pix_y & "0000000") + pix_x) + ('0' & pix_y & "000000000") ; -- 10 slices, 19 luts dummy := '0' & pix_y & "00" + pix_y; pix_addr <= (dummy & "0000000" + pix_x); -- 11 slices, 21 luts :(( end if; end process; rd_addr <= std_ulogic_vector(pix_addr(18 downto 1)); rd_req <= std_ulogic(pix_addr(0)); -- damit nichts wegoptimiert wird end Behavioral;