-------------------------------------------------------------------------------- Release 9.1.03i Trace Copyright (c) 1995-2007 Xilinx, Inc. All rights reserved. C:\Xilinx\bin\nt\trce.exe -ise C:/daten/VHDL/FEVXALU/IJVM/IJVM.ise -intstyle ise -e 3 -s 4 -xml IJVM IJVM.ncd -o IJVM.twr IJVM.pcf Design file: ijvm.ncd Physical constraint file: ijvm.pcf Device,speed: xc3s200,-4 (PRODUCTION 1.39 2006-10-19) Report level: error report Environment Variable Effect -------------------- ------ NONE No environment variables were set -------------------------------------------------------------------------------- INFO:Timing:2698 - No timing constraints found, doing default enumeration. INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths option. All paths that are not constrained will be reported in the unconstrained paths section(s) of the report. INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on a 50 Ohm transmission line loading model. For the details of this model, and for more information on accounting for different loading conditions, please see the device datasheet. Data Sheet report: ----------------- All values displayed in nanoseconds (ns) Setup/Hold to clock clk ------------+------------+------------+------------------+--------+ | Setup to | Hold to | | Clock | Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase | ------------+------------+------------+------------------+--------+ xA<0> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<1> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<2> | 3.017(R)| -0.462(R)|clk_BUFGP | 0.000| xA<3> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xA<4> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xA<5> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<6> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xA<7> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xA<8> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xA<9> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xA<10> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<11> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<12> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<13> | 3.019(R)| -0.464(R)|clk_BUFGP | 0.000| xA<14> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xA<15> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xA<16> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<17> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xA<18> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<19> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<20> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<21> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<22> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<23> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<24> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<25> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<26> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<27> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<28> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xA<29> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<30> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xA<31> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<0> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xB<1> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xB<2> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<3> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xB<4> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xB<5> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<6> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xB<7> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xB<8> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<9> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<10> | 3.018(R)| -0.463(R)|clk_BUFGP | 0.000| xB<11> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<12> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<13> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<14> | 3.019(R)| -0.464(R)|clk_BUFGP | 0.000| xB<15> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<16> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xB<17> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<18> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<19> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<20> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<21> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<22> | 3.017(R)| -0.461(R)|clk_BUFGP | 0.000| xB<23> | 3.018(R)| -0.463(R)|clk_BUFGP | 0.000| xB<24> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<25> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<26> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<27> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<28> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<29> | 3.018(R)| -0.462(R)|clk_BUFGP | 0.000| xB<30> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xB<31> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xENA | 3.017(R)| 0.023(R)|clk_BUFGP | 0.000| xENB | 3.017(R)| 0.391(R)|clk_BUFGP | 0.000| xF<0> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xF<1> | 3.019(R)| -0.463(R)|clk_BUFGP | 0.000| xINC | 3.019(R)| -0.464(R)|clk_BUFGP | 0.000| xINVA | 3.017(R)| -0.146(R)|clk_BUFGP | 0.000| ------------+------------+------------+------------------+--------+ Clock clk to Pad ------------+------------+------------------+--------+ | clk (edge) | | Clock | Destination | to PAD |Internal Clock(s) | Phase | ------------+------------+------------------+--------+ xFLAG_N | 9.788(R)|clk_BUFGP | 0.000| xFLAG_Z | 23.030(R)|clk_BUFGP | 0.000| xY<0> | 7.360(R)|clk_BUFGP | 0.000| xY<1> | 7.362(R)|clk_BUFGP | 0.000| xY<2> | 7.360(R)|clk_BUFGP | 0.000| xY<3> | 7.360(R)|clk_BUFGP | 0.000| xY<4> | 7.361(R)|clk_BUFGP | 0.000| xY<5> | 7.362(R)|clk_BUFGP | 0.000| xY<6> | 7.360(R)|clk_BUFGP | 0.000| xY<7> | 7.360(R)|clk_BUFGP | 0.000| xY<8> | 7.360(R)|clk_BUFGP | 0.000| xY<9> | 7.360(R)|clk_BUFGP | 0.000| xY<10> | 7.360(R)|clk_BUFGP | 0.000| xY<11> | 7.360(R)|clk_BUFGP | 0.000| xY<12> | 7.360(R)|clk_BUFGP | 0.000| xY<13> | 7.360(R)|clk_BUFGP | 0.000| xY<14> | 7.360(R)|clk_BUFGP | 0.000| xY<15> | 7.360(R)|clk_BUFGP | 0.000| xY<16> | 7.360(R)|clk_BUFGP | 0.000| xY<17> | 7.362(R)|clk_BUFGP | 0.000| xY<18> | 7.360(R)|clk_BUFGP | 0.000| xY<19> | 7.360(R)|clk_BUFGP | 0.000| xY<20> | 7.360(R)|clk_BUFGP | 0.000| xY<21> | 7.362(R)|clk_BUFGP | 0.000| xY<22> | 7.362(R)|clk_BUFGP | 0.000| xY<23> | 7.362(R)|clk_BUFGP | 0.000| xY<24> | 7.362(R)|clk_BUFGP | 0.000| xY<25> | 7.360(R)|clk_BUFGP | 0.000| xY<26> | 7.360(R)|clk_BUFGP | 0.000| xY<27> | 7.359(R)|clk_BUFGP | 0.000| xY<28> | 7.360(R)|clk_BUFGP | 0.000| xY<29> | 7.361(R)|clk_BUFGP | 0.000| xY<30> | 7.360(R)|clk_BUFGP | 0.000| xY<31> | 9.430(R)|clk_BUFGP | 0.000| ------------+------------+------------------+--------+ Clock to Setup on destination clock clk ---------------+---------+---------+---------+---------+ | Src:Rise| Src:Fall| Src:Rise| Src:Fall| Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall| ---------------+---------+---------+---------+---------+ clk | 13.277| | | | ---------------+---------+---------+---------+---------+ Analysis completed Tue Mar 31 18:46:21 2009 -------------------------------------------------------------------------------- Peak Memory Usage: 87 MB