.include "tn13adef.inc"         ; real target
//.include "m2560def.inc"       ; my test board

/****************************************************************************
                                                                            *
 Fractional divider using bresenham algorithm                               *
 Maximum output jitter is 1 input clock cycle                               *
 Integer divider ratios are jitter free                                     *
                                                                            *
fuses                                                                       *
                                                                            *
L: 0x78  ;use external clock                                                *
H: 0xF9  ;5V supply BOD configuration                                       *
                                                                            *
clock input  : PB3 (CLKI)                                                   *
clock output : PB4                                                          *
                                                                            *
f_in / f_out = N / M                                                        *
                                                                            *
Notes:                                                                      *
                                                                            *
1) M is limited to range 1-32767                                            *
2) N / M must be >= 14                                                      *
3) N / M must be <= 524000                                                  *
4) to calculate M and N, write down the fraction of f_out / f_in            *
   and reduce it until M is <= 32767                                        *
                                                                            *
Example:                                                                    *
                                                                            *
f_in / f_out = N / M = 11,000,000 / 310,000 = 1,100,000 / 31,000            *
                                                                            *
****************************************************************************/

.equ M =    31000
.equ N = 11000000

.equ ticks_per_half_cycle = N / (2*M)
.equ rest                 = N % (2*M)

.if (M>32767 || M<1)
.error "M must be within 1-32767"
.endif

.if (ticks_per_half_cycle < 7) 
.error "N/M must be >= 14"
.endif

.if (ticks_per_half_cycle > 262000 ) 
.error "N/M must be <= 524000"
.endif

.def tmp         = r16
.def cnt_l       = r17
.def cnt_h       = r18
.def m_l         = r19
.def m_h         = r20
.def r_l         = r21
.def r_h         = r22
.def delay_cnt_l = r24      ; r25:r24
.def delay_cnt_h = r25

;############################################################################

.macro  my_delay

.if (@0) > 262140
.error "max. delay 262140 cycles!"
.endif

.if (@0) < 0
.error "delay negative!"
.endif


.if (@0 == 1)
    nop
.endif
 
.if (@0 == 2)
    nop
    nop
.endif

.if (@0 == 3)
    nop
    nop
    nop
.endif

.if (@0 == 4)
    nop
    nop
    nop
    nop
.endif

.if @0 >= 5


.if ((@0-1) % 4) == 1
    nop
.endif

.if ((@0-1) % 4) == 2
    nop
    nop
.endif

.if ((@0-1) % 4) == 3
    nop
    nop
    nop
.endif

    ldi     delay_cnt_l,  low((@0-1) / 4)
    ldi     delay_cnt_h, high((@0-1) / 4)
loop:
    sbiw    delay_cnt_l, 1
    brne    loop
.endif
.endm
.
;switch off all unnecessary hardware stuff ##################################

  ldi tmp,(1<<PRTIM0)|(1<<PRADC)
  out PRR,tmp
  ldi tmp,1<<ACD
  out ACSR,tmp
  ldi tmp,(1<<ADC0D)|(1<<ADC2D)|(1<<ADC1D)|(1<<AIN1D)|(1<<AIN0D)
  out DIDR0,tmp

;enable output pin (and preload output helper register) #####################

  ldi tmp,1<<PORTB4
  out DDRB,tmp

;initialize for bresenham algorithm #########################################

  ldi cnt_l, 0
  ldi cnt_h, 0
  ldi m_l, low(2*M)
  ldi m_h, high(2*M)
  ldi r_l, low(rest)
  ldi r_h, high(rest)

;fractional divider loop ####################################################

slow:
  add cnt_l, m_l
  adc cnt_h, m_h
fast:
my_delay (ticks_per_half_cycle-6)   ;wait some ticks
  out PINB, tmp     ; toggle output
  sub cnt_l, r_l    ; accumulate error
  sbc cnt_h, r_h
  brcs slow         ; this loop takes ticks_per_half_cycle+1 total, 7 minimum
  rjmp fast         ; this loop takes ticks_per_half_cycle total, 6 minimim

;############################################################################