--- DFF ------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity DFF is
    generic(
    P_DELAY : time := 1 ns;
    SETUP   : time := 1 ns);
    port(
    D       : in std_logic;
    CLK     : in std_logic;
    EN      : in std_logic;
    RESET   : in std_logic;
    Q       : out std_logic;
    Q_INV   : out std_logic);
end DFF;

architecture rtl of DFF is

-- Zusätzliche Signale

begin

-- Hier kommt die Beschreibung vom DFF rein.

end;

--- MUX2X1 ------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity MUX2X1 is
    generic(
    P_DELAY : time := 2 ns);
    port(
    S       : in std_logic;
    E1      : in std_logic;
    E2      : in std_logic;
    Y       : out std_logic);
end MUX2X1;

architecture rtl of MUX2X1 is

-- Zusätzliche Signale

begin

-- Hier kommt die Beschreibung vom MUX2X1 rein.

end;

----- D_RIPPLE_REG ------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity D_RIPPLE_REG is
    generic(
    P_DELAY : time := 8 ns;
    SETUP   : time := 2 ns;
    SIZE    : positive := 4);
    port(
    D       : in std_logic_vector(SIZE-1 downto 0);
    CLK     : in std_logic;
    EN      : in std_logic;
    RESET   : in std_logic;
    RIPPLE  : in std_logic;
    INPUT   : in std_logic;
    Q       : out std_logic_vector(SIZE-1 downto 0);
    Q_INV   : out std_logic_vector(SIZE-1 downto 0);
    OUTPUT  : out std_logic);
end D_RIPPLE_REG;

architecture rtl of D_RIPPLE_REG is

-- Hier werden verwendete Komponenten deklariert.
-- Zusätzliche Signale

begin

-- Hier kommt die Beschreibung vom MUX2X1 rein.

end;

----- Testbench --------------------------------------

-- Optional