-- ######################## Testbenches ######################## --

----- Testbench DFF --------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity Testbench_DFF is
end Testbench_DFF;

architecture sim of Testbench_DFF is

signal TB_D     : std_logic:='0';
signal TB_CLK   : std_logic:='0';
signal TB_EN    : std_logic:='0';
signal TB_RESET : std_logic:='0';   
signal TB_Q     : std_logic:='0';
signal TB_Q_INV : std_logic:='0';

begin

process begin
    wait for 20 ns;
	TB_EN <= '1';
    wait for 20 ns;
	for I in 0 to 35 loop
		if I = 5 then
			TB_D <= '1';
		end if;
		if I = 10 then
			TB_EN <= '0';
		end if;
		if I = 15 then
			TB_RESET <= '1';
		end if;
		if I = 20 then
			TB_D <= '0';
			TB_RESET <= '0';
		end if;
		if I = 25 then
			TB_EN <= '1';
		end if;
		if I = 30 then
			TB_D <= '1';
		end if;
		TB_CLK <= not TB_CLK;
		wait for 10 ns;
	end loop;
end process;
	
UUT: entity work.DFF
    port map(
    D       => TB_D,
    CLK     => TB_CLK,
    EN      => TB_EN,
    RESET   => TB_RESET,
    Q       => TB_Q,
    Q_INV   => TB_Q_INV);

end;

----- Testbench MUX2X1 --------------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity Testbench_MUX2X1 is
end Testbench_MUX2X1;

architecture sim of Testbench_MUX2X1 is

signal TB_S  : std_logic:='0';
signal TB_E1 : std_logic:='0';
signal TB_E2 : std_logic:='0';
signal TB_Y  : std_logic:='0';   

begin

TB_E1 <= not TB_E1 after 3 ns;
TB_E2 <= not TB_E2 after 7 ns;

process begin
    wait for 50 ns;
	TB_S <= not TB_S;
end process;

UUT: entity work.MUX2X1
    port map(
    S       => TB_S,
    E1      => TB_E1,
    E2      => TB_E2,
    Y       => TB_Y);

end;

----- Testbench D_RIPPLE_REG --------------------------------------

library ieee;
use ieee.std_logic_1164.all;

entity Testbench_D_RIPPLE_REG is
end Testbench_D_RIPPLE_REG;

architecture sim of Testbench_D_RIPPLE_REG is

constant SIZE   : integer:=8;
signal TB_D     : std_logic_vector(SIZE-1 downto 0):=(others => '0');
signal TB_CLK   : std_logic:='0';
signal TB_EN    : std_logic:='0';
signal TB_RESET : std_logic:='0';
signal TB_RIPPLE: std_logic:='0';
signal TB_INPUT : std_logic:='0';
signal TB_Q     : std_logic_vector(SIZE-1 downto 0):=(others => '0');
signal TB_Q_INV : std_logic_vector(SIZE-1 downto 0):=(others => '0');
signal TB_OUTPUT: std_logic:='0';

begin

TB_CLK <= not TB_CLK after 10 ns;
TB_EN <= '1';
TB_RESET <= '0';

process 
    variable TB_D_Bit: std_logic:='0';
begin
    TB_RIPPLE <= '0';
    for I in 0 to SIZE-1 loop
        TB_D_Bit := not TB_D_Bit;
        TB_D(I) <= TB_D_Bit;
    end loop;
    wait for 80 ns;
    TB_D <= not TB_D;
    wait for 200 ns;
    TB_RIPPLE <= '1';
    wait for 30 ns;
    TB_INPUT <= not TB_INPUT;
    wait for 50 ns;
    TB_INPUT <= not TB_INPUT;
    wait for 20 ns;
    TB_INPUT <= not TB_INPUT;
    wait for 40 ns;
    TB_INPUT <= not TB_INPUT;
    wait;
end process;

UUT: entity work.D_RIPPLE_REG
    generic map(
    SIZE    => SIZE)
    port map(
    D       => TB_D,
    CLK     => TB_CLK,
    EN      => TB_EN,
    RESET   => TB_RESET,
    RIPPLE  => TB_RIPPLE,
    INPUT   => TB_INPUT,
    Q       => TB_Q,
    Q_INV   => TB_Q_INV,
    OUTPUT  => TB_OUTPUT);

end;