library ieee;
use ieee.std_logic_1164.all;

entity DFF is
  generic(P_DELAY: time := 1 ns; SETUP : time := 1 ns);
  port(D, CLK, EN, RESET: in std_logic;
       Q, Q_INV : out std_logic);
end DFF;

architecture Verhalten1 of DFF is
begin
  process(CLK, RESET)
  begin 
    if RESET = '1' then
      Q <= '0';
      Q_INV <= '1';
    elsif rising_edge(CLK) and EN = '1' then
      Q <= D;
      Q_INV <= not D; 
    end if;       
  end process;
end Verhalten1;
----------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity MUX2X1 is
  generic(P_DELAY: time := 2 ns);
  port(S, E1, E2: in std_logic;
       Y: out std_logic);
end MUX2X1;

architecture Verhalten2 of MUX2X1 is
begin
  Y <= E1 when S = '1' else E2;  
end Verhalten2;
-------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;

entity D_RIPPLE_REG is
  generic (P_DELAY: time := 8 ns; SETUP : time := 2 ns;
           SIZE : positive := 4);
  port (D: in std_logic_vector(size-1 downto 0);
        CLK, EN, RESET, RIPPLE, INPUT: in std_logic;
        Q : out std_logic_vector (size-1 downto 0);
        Q_INV : out std_logic_vector (size-1 downto 0);
        OUTPUT: out std_logic);
end D_RIPPLE_REG;

architecture Verhalten3 of D_RIPPLE_REG is 
COMPONENT DFF is
  generic (P_DELAY: time := 1 ns; SETUP : time := 1 ns);
  port (D, CLK, EN, RESET: in std_logic;
        Q, Q_INV : out std_logic);
end component;

COMPONENT MUX2X1 is
  generic (P_DELAY: time := 2 ns);
  port (S, E1, E2: in std_logic;
        Y: out std_logic);
end component;

SIGNAL Q_TEMP, Q_INV_TEMP, Y_TEMP: std_logic_vector(size-1 downto 0) := (others => '0');

begin 
  gen1: for i in 0 to size - 1 generate
    mux: MUX2X1 port map (
	S  => RIPPLE, 
	E1 => Q_TEMP(i), 
	E2 => D(i), 
	Y  => Y_TEMP(i));
  end generate;

  gen2: for i in 0 to size - 1 generate
    ffd: DFF port map (
	D     => Y_TEMP(i), 
	CLK   => CLK, 
	EN    => EN, 
	RESET => RESET, 
	Q     => Q_TEMP(i), 
	Q_INV => Q_INV_TEMP(i));
  end generate;

process (CLK)
begin
  for i in 0 to size - 1 loop              
    Q_INV_TEMP(i) <= not Q_TEMP(i);
  end loop;
end process;

end Verhalten3;