-- ddr3controller_s0_mm_interconnect_0.vhd

-- This file was auto-generated from altera_mm_interconnect_hw.tcl.  If you edit it your changes
-- will probably be lost.
-- 
-- Generated using ACDS version 18.1 625

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity ddr3controller_s0_mm_interconnect_0 is
	port (
		avl_clk_out_clk_clk                                          : in  std_logic                     := '0';             --                                        avl_clk_out_clk.clk
		cpu_inst_reset_n_reset_bridge_in_reset_reset                 : in  std_logic                     := '0';             --                 cpu_inst_reset_n_reset_bridge_in_reset.reset
		sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset : in  std_logic                     := '0';             -- sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset.reset
		cpu_inst_data_master_address                                 : in  std_logic_vector(19 downto 0) := (others => '0'); --                                   cpu_inst_data_master.address
		cpu_inst_data_master_waitrequest                             : out std_logic;                                        --                                                       .waitrequest
		cpu_inst_data_master_read                                    : in  std_logic                     := '0';             --                                                       .read
		cpu_inst_data_master_readdata                                : out std_logic_vector(31 downto 0);                    --                                                       .readdata
		cpu_inst_data_master_write                                   : in  std_logic                     := '0';             --                                                       .write
		cpu_inst_data_master_writedata                               : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                       .writedata
		sequencer_phy_mgr_inst_avl_address                           : out std_logic_vector(12 downto 0);                    --                             sequencer_phy_mgr_inst_avl.address
		sequencer_phy_mgr_inst_avl_write                             : out std_logic;                                        --                                                       .write
		sequencer_phy_mgr_inst_avl_read                              : out std_logic;                                        --                                                       .read
		sequencer_phy_mgr_inst_avl_readdata                          : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                       .readdata
		sequencer_phy_mgr_inst_avl_writedata                         : out std_logic_vector(31 downto 0);                    --                                                       .writedata
		sequencer_phy_mgr_inst_avl_waitrequest                       : in  std_logic                     := '0';             --                                                       .waitrequest
		sequencer_pll_mgr_inst_avl_address                           : out std_logic_vector(12 downto 0);                    --                             sequencer_pll_mgr_inst_avl.address
		sequencer_pll_mgr_inst_avl_write                             : out std_logic;                                        --                                                       .write
		sequencer_pll_mgr_inst_avl_read                              : out std_logic;                                        --                                                       .read
		sequencer_pll_mgr_inst_avl_readdata                          : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                       .readdata
		sequencer_pll_mgr_inst_avl_writedata                         : out std_logic_vector(31 downto 0);                    --                                                       .writedata
		sequencer_pll_mgr_inst_avl_waitrequest                       : in  std_logic                     := '0';             --                                                       .waitrequest
		sequencer_rw_mgr_inst_avl_address                            : out std_logic_vector(12 downto 0);                    --                              sequencer_rw_mgr_inst_avl.address
		sequencer_rw_mgr_inst_avl_write                              : out std_logic;                                        --                                                       .write
		sequencer_rw_mgr_inst_avl_read                               : out std_logic;                                        --                                                       .read
		sequencer_rw_mgr_inst_avl_readdata                           : in  std_logic_vector(31 downto 0) := (others => '0'); --                                                       .readdata
		sequencer_rw_mgr_inst_avl_writedata                          : out std_logic_vector(31 downto 0);                    --                                                       .writedata
		sequencer_rw_mgr_inst_avl_waitrequest                        : in  std_logic                     := '0'              --                                                       .waitrequest
	);
end entity ddr3controller_s0_mm_interconnect_0;

architecture rtl of ddr3controller_s0_mm_interconnect_0 is
	component altera_merlin_master_translator is
		generic (
			AV_ADDRESS_W                : integer := 32;
			AV_DATA_W                   : integer := 32;
			AV_BURSTCOUNT_W             : integer := 4;
			AV_BYTEENABLE_W             : integer := 4;
			UAV_ADDRESS_W               : integer := 38;
			UAV_BURSTCOUNT_W            : integer := 10;
			USE_READ                    : integer := 1;
			USE_WRITE                   : integer := 1;
			USE_BEGINBURSTTRANSFER      : integer := 0;
			USE_BEGINTRANSFER           : integer := 0;
			USE_CHIPSELECT              : integer := 0;
			USE_BURSTCOUNT              : integer := 1;
			USE_READDATAVALID           : integer := 1;
			USE_WAITREQUEST             : integer := 1;
			USE_READRESPONSE            : integer := 0;
			USE_WRITERESPONSE           : integer := 0;
			AV_SYMBOLS_PER_WORD         : integer := 4;
			AV_ADDRESS_SYMBOLS          : integer := 0;
			AV_BURSTCOUNT_SYMBOLS       : integer := 0;
			AV_CONSTANT_BURST_BEHAVIOR  : integer := 0;
			UAV_CONSTANT_BURST_BEHAVIOR : integer := 0;
			AV_LINEWRAPBURSTS           : integer := 0;
			AV_REGISTERINCOMINGSIGNALS  : integer := 0
		);
		port (
			clk                    : in  std_logic                     := 'X';             -- clk
			reset                  : in  std_logic                     := 'X';             -- reset
			uav_address            : out std_logic_vector(19 downto 0);                    -- address
			uav_burstcount         : out std_logic_vector(2 downto 0);                     -- burstcount
			uav_read               : out std_logic;                                        -- read
			uav_write              : out std_logic;                                        -- write
			uav_waitrequest        : in  std_logic                     := 'X';             -- waitrequest
			uav_readdatavalid      : in  std_logic                     := 'X';             -- readdatavalid
			uav_byteenable         : out std_logic_vector(3 downto 0);                     -- byteenable
			uav_readdata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			uav_writedata          : out std_logic_vector(31 downto 0);                    -- writedata
			uav_lock               : out std_logic;                                        -- lock
			uav_debugaccess        : out std_logic;                                        -- debugaccess
			av_address             : in  std_logic_vector(19 downto 0) := (others => 'X'); -- address
			av_waitrequest         : out std_logic;                                        -- waitrequest
			av_read                : in  std_logic                     := 'X';             -- read
			av_readdata            : out std_logic_vector(31 downto 0);                    -- readdata
			av_write               : in  std_logic                     := 'X';             -- write
			av_writedata           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			av_burstcount          : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- burstcount
			av_byteenable          : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			av_beginbursttransfer  : in  std_logic                     := 'X';             -- beginbursttransfer
			av_begintransfer       : in  std_logic                     := 'X';             -- begintransfer
			av_chipselect          : in  std_logic                     := 'X';             -- chipselect
			av_readdatavalid       : out std_logic;                                        -- readdatavalid
			av_lock                : in  std_logic                     := 'X';             -- lock
			av_debugaccess         : in  std_logic                     := 'X';             -- debugaccess
			uav_clken              : out std_logic;                                        -- clken
			av_clken               : in  std_logic                     := 'X';             -- clken
			uav_response           : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- response
			av_response            : out std_logic_vector(1 downto 0);                     -- response
			uav_writeresponsevalid : in  std_logic                     := 'X';             -- writeresponsevalid
			av_writeresponsevalid  : out std_logic                                         -- writeresponsevalid
		);
	end component altera_merlin_master_translator;

	component altera_merlin_slave_translator is
		generic (
			AV_ADDRESS_W                   : integer := 30;
			AV_DATA_W                      : integer := 32;
			UAV_DATA_W                     : integer := 32;
			AV_BURSTCOUNT_W                : integer := 4;
			AV_BYTEENABLE_W                : integer := 4;
			UAV_BYTEENABLE_W               : integer := 4;
			UAV_ADDRESS_W                  : integer := 32;
			UAV_BURSTCOUNT_W               : integer := 4;
			AV_READLATENCY                 : integer := 0;
			USE_READDATAVALID              : integer := 1;
			USE_WAITREQUEST                : integer := 1;
			USE_UAV_CLKEN                  : integer := 0;
			USE_READRESPONSE               : integer := 0;
			USE_WRITERESPONSE              : integer := 0;
			AV_SYMBOLS_PER_WORD            : integer := 4;
			AV_ADDRESS_SYMBOLS             : integer := 0;
			AV_BURSTCOUNT_SYMBOLS          : integer := 0;
			AV_CONSTANT_BURST_BEHAVIOR     : integer := 0;
			UAV_CONSTANT_BURST_BEHAVIOR    : integer := 0;
			AV_REQUIRE_UNALIGNED_ADDRESSES : integer := 0;
			CHIPSELECT_THROUGH_READLATENCY : integer := 0;
			AV_READ_WAIT_CYCLES            : integer := 0;
			AV_WRITE_WAIT_CYCLES           : integer := 0;
			AV_SETUP_WAIT_CYCLES           : integer := 0;
			AV_DATA_HOLD_CYCLES            : integer := 0
		);
		port (
			clk                    : in  std_logic                     := 'X';             -- clk
			reset                  : in  std_logic                     := 'X';             -- reset
			uav_address            : in  std_logic_vector(19 downto 0) := (others => 'X'); -- address
			uav_burstcount         : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			uav_read               : in  std_logic                     := 'X';             -- read
			uav_write              : in  std_logic                     := 'X';             -- write
			uav_waitrequest        : out std_logic;                                        -- waitrequest
			uav_readdatavalid      : out std_logic;                                        -- readdatavalid
			uav_byteenable         : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			uav_readdata           : out std_logic_vector(31 downto 0);                    -- readdata
			uav_writedata          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			uav_lock               : in  std_logic                     := 'X';             -- lock
			uav_debugaccess        : in  std_logic                     := 'X';             -- debugaccess
			av_address             : out std_logic_vector(12 downto 0);                    -- address
			av_write               : out std_logic;                                        -- write
			av_read                : out std_logic;                                        -- read
			av_readdata            : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			av_writedata           : out std_logic_vector(31 downto 0);                    -- writedata
			av_waitrequest         : in  std_logic                     := 'X';             -- waitrequest
			av_begintransfer       : out std_logic;                                        -- begintransfer
			av_beginbursttransfer  : out std_logic;                                        -- beginbursttransfer
			av_burstcount          : out std_logic_vector(0 downto 0);                     -- burstcount
			av_byteenable          : out std_logic_vector(3 downto 0);                     -- byteenable
			av_readdatavalid       : in  std_logic                     := 'X';             -- readdatavalid
			av_writebyteenable     : out std_logic_vector(3 downto 0);                     -- writebyteenable
			av_lock                : out std_logic;                                        -- lock
			av_chipselect          : out std_logic;                                        -- chipselect
			av_clken               : out std_logic;                                        -- clken
			uav_clken              : in  std_logic                     := 'X';             -- clken
			av_debugaccess         : out std_logic;                                        -- debugaccess
			av_outputenable        : out std_logic;                                        -- outputenable
			uav_response           : out std_logic_vector(1 downto 0);                     -- response
			av_response            : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- response
			uav_writeresponsevalid : out std_logic;                                        -- writeresponsevalid
			av_writeresponsevalid  : in  std_logic                     := 'X'              -- writeresponsevalid
		);
	end component altera_merlin_slave_translator;

	component altera_merlin_master_agent is
		generic (
			PKT_ORI_BURST_SIZE_H      : integer := 116;
			PKT_ORI_BURST_SIZE_L      : integer := 114;
			PKT_RESPONSE_STATUS_H     : integer := 113;
			PKT_RESPONSE_STATUS_L     : integer := 112;
			PKT_QOS_H                 : integer := 111;
			PKT_QOS_L                 : integer := 108;
			PKT_DATA_SIDEBAND_H       : integer := 107;
			PKT_DATA_SIDEBAND_L       : integer := 100;
			PKT_ADDR_SIDEBAND_H       : integer := 99;
			PKT_ADDR_SIDEBAND_L       : integer := 95;
			PKT_BURST_TYPE_H          : integer := 94;
			PKT_BURST_TYPE_L          : integer := 93;
			PKT_CACHE_H               : integer := 92;
			PKT_CACHE_L               : integer := 89;
			PKT_THREAD_ID_H           : integer := 88;
			PKT_THREAD_ID_L           : integer := 87;
			PKT_BURST_SIZE_H          : integer := 86;
			PKT_BURST_SIZE_L          : integer := 84;
			PKT_TRANS_EXCLUSIVE       : integer := 83;
			PKT_TRANS_LOCK            : integer := 82;
			PKT_BEGIN_BURST           : integer := 81;
			PKT_PROTECTION_H          : integer := 80;
			PKT_PROTECTION_L          : integer := 80;
			PKT_BURSTWRAP_H           : integer := 79;
			PKT_BURSTWRAP_L           : integer := 77;
			PKT_BYTE_CNT_H            : integer := 76;
			PKT_BYTE_CNT_L            : integer := 74;
			PKT_ADDR_H                : integer := 73;
			PKT_ADDR_L                : integer := 42;
			PKT_TRANS_COMPRESSED_READ : integer := 41;
			PKT_TRANS_POSTED          : integer := 40;
			PKT_TRANS_WRITE           : integer := 39;
			PKT_TRANS_READ            : integer := 38;
			PKT_DATA_H                : integer := 37;
			PKT_DATA_L                : integer := 6;
			PKT_BYTEEN_H              : integer := 5;
			PKT_BYTEEN_L              : integer := 2;
			PKT_SRC_ID_H              : integer := 1;
			PKT_SRC_ID_L              : integer := 1;
			PKT_DEST_ID_H             : integer := 0;
			PKT_DEST_ID_L             : integer := 0;
			ST_DATA_W                 : integer := 115;
			ST_CHANNEL_W              : integer := 1;
			AV_BURSTCOUNT_W           : integer := 3;
			SUPPRESS_0_BYTEEN_RSP     : integer := 1;
			ID                        : integer := 1;
			BURSTWRAP_VALUE           : integer := 4;
			CACHE_VALUE               : integer := 0;
			SECURE_ACCESS_BIT         : integer := 1;
			USE_READRESPONSE          : integer := 0;
			USE_WRITERESPONSE         : integer := 0
		);
		port (
			clk                   : in  std_logic                     := 'X';             -- clk
			reset                 : in  std_logic                     := 'X';             -- reset
			av_address            : in  std_logic_vector(19 downto 0) := (others => 'X'); -- address
			av_write              : in  std_logic                     := 'X';             -- write
			av_read               : in  std_logic                     := 'X';             -- read
			av_writedata          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			av_readdata           : out std_logic_vector(31 downto 0);                    -- readdata
			av_waitrequest        : out std_logic;                                        -- waitrequest
			av_readdatavalid      : out std_logic;                                        -- readdatavalid
			av_byteenable         : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			av_burstcount         : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			av_debugaccess        : in  std_logic                     := 'X';             -- debugaccess
			av_lock               : in  std_logic                     := 'X';             -- lock
			cp_valid              : out std_logic;                                        -- valid
			cp_data               : out std_logic_vector(91 downto 0);                    -- data
			cp_startofpacket      : out std_logic;                                        -- startofpacket
			cp_endofpacket        : out std_logic;                                        -- endofpacket
			cp_ready              : in  std_logic                     := 'X';             -- ready
			rp_valid              : in  std_logic                     := 'X';             -- valid
			rp_data               : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			rp_channel            : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- channel
			rp_startofpacket      : in  std_logic                     := 'X';             -- startofpacket
			rp_endofpacket        : in  std_logic                     := 'X';             -- endofpacket
			rp_ready              : out std_logic;                                        -- ready
			av_response           : out std_logic_vector(1 downto 0);                     -- response
			av_writeresponsevalid : out std_logic                                         -- writeresponsevalid
		);
	end component altera_merlin_master_agent;

	component altera_merlin_slave_agent is
		generic (
			PKT_ORI_BURST_SIZE_H      : integer := 90;
			PKT_ORI_BURST_SIZE_L      : integer := 88;
			PKT_RESPONSE_STATUS_H     : integer := 87;
			PKT_RESPONSE_STATUS_L     : integer := 86;
			PKT_BURST_SIZE_H          : integer := 85;
			PKT_BURST_SIZE_L          : integer := 83;
			PKT_TRANS_LOCK            : integer := 82;
			PKT_BEGIN_BURST           : integer := 81;
			PKT_PROTECTION_H          : integer := 80;
			PKT_PROTECTION_L          : integer := 80;
			PKT_BURSTWRAP_H           : integer := 79;
			PKT_BURSTWRAP_L           : integer := 77;
			PKT_BYTE_CNT_H            : integer := 76;
			PKT_BYTE_CNT_L            : integer := 74;
			PKT_ADDR_H                : integer := 73;
			PKT_ADDR_L                : integer := 42;
			PKT_TRANS_COMPRESSED_READ : integer := 41;
			PKT_TRANS_POSTED          : integer := 40;
			PKT_TRANS_WRITE           : integer := 39;
			PKT_TRANS_READ            : integer := 38;
			PKT_DATA_H                : integer := 37;
			PKT_DATA_L                : integer := 6;
			PKT_BYTEEN_H              : integer := 5;
			PKT_BYTEEN_L              : integer := 2;
			PKT_SRC_ID_H              : integer := 1;
			PKT_SRC_ID_L              : integer := 1;
			PKT_DEST_ID_H             : integer := 0;
			PKT_DEST_ID_L             : integer := 0;
			PKT_SYMBOL_W              : integer := 8;
			ST_CHANNEL_W              : integer := 8;
			ST_DATA_W                 : integer := 96;
			AVS_BURSTCOUNT_W          : integer := 4;
			SUPPRESS_0_BYTEEN_CMD     : integer := 1;
			PREVENT_FIFO_OVERFLOW     : integer := 0;
			USE_READRESPONSE          : integer := 0;
			USE_WRITERESPONSE         : integer := 0;
			ECC_ENABLE                : integer := 0
		);
		port (
			clk                     : in  std_logic                     := 'X';             -- clk
			reset                   : in  std_logic                     := 'X';             -- reset
			m0_address              : out std_logic_vector(19 downto 0);                    -- address
			m0_burstcount           : out std_logic_vector(2 downto 0);                     -- burstcount
			m0_byteenable           : out std_logic_vector(3 downto 0);                     -- byteenable
			m0_debugaccess          : out std_logic;                                        -- debugaccess
			m0_lock                 : out std_logic;                                        -- lock
			m0_readdata             : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			m0_readdatavalid        : in  std_logic                     := 'X';             -- readdatavalid
			m0_read                 : out std_logic;                                        -- read
			m0_waitrequest          : in  std_logic                     := 'X';             -- waitrequest
			m0_writedata            : out std_logic_vector(31 downto 0);                    -- writedata
			m0_write                : out std_logic;                                        -- write
			rp_endofpacket          : out std_logic;                                        -- endofpacket
			rp_ready                : in  std_logic                     := 'X';             -- ready
			rp_valid                : out std_logic;                                        -- valid
			rp_data                 : out std_logic_vector(91 downto 0);                    -- data
			rp_startofpacket        : out std_logic;                                        -- startofpacket
			cp_ready                : out std_logic;                                        -- ready
			cp_valid                : in  std_logic                     := 'X';             -- valid
			cp_data                 : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			cp_startofpacket        : in  std_logic                     := 'X';             -- startofpacket
			cp_endofpacket          : in  std_logic                     := 'X';             -- endofpacket
			cp_channel              : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- channel
			rf_sink_ready           : out std_logic;                                        -- ready
			rf_sink_valid           : in  std_logic                     := 'X';             -- valid
			rf_sink_startofpacket   : in  std_logic                     := 'X';             -- startofpacket
			rf_sink_endofpacket     : in  std_logic                     := 'X';             -- endofpacket
			rf_sink_data            : in  std_logic_vector(92 downto 0) := (others => 'X'); -- data
			rf_source_ready         : in  std_logic                     := 'X';             -- ready
			rf_source_valid         : out std_logic;                                        -- valid
			rf_source_startofpacket : out std_logic;                                        -- startofpacket
			rf_source_endofpacket   : out std_logic;                                        -- endofpacket
			rf_source_data          : out std_logic_vector(92 downto 0);                    -- data
			rdata_fifo_sink_ready   : out std_logic;                                        -- ready
			rdata_fifo_sink_valid   : in  std_logic                     := 'X';             -- valid
			rdata_fifo_sink_data    : in  std_logic_vector(33 downto 0) := (others => 'X'); -- data
			rdata_fifo_sink_error   : in  std_logic                     := 'X';             -- error
			rdata_fifo_src_ready    : in  std_logic                     := 'X';             -- ready
			rdata_fifo_src_valid    : out std_logic;                                        -- valid
			rdata_fifo_src_data     : out std_logic_vector(33 downto 0);                    -- data
			m0_response             : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- response
			m0_writeresponsevalid   : in  std_logic                     := 'X'              -- writeresponsevalid
		);
	end component altera_merlin_slave_agent;

	component altera_avalon_sc_fifo is
		generic (
			SYMBOLS_PER_BEAT    : integer := 1;
			BITS_PER_SYMBOL     : integer := 8;
			FIFO_DEPTH          : integer := 16;
			CHANNEL_WIDTH       : integer := 0;
			ERROR_WIDTH         : integer := 0;
			USE_PACKETS         : integer := 0;
			USE_FILL_LEVEL      : integer := 0;
			EMPTY_LATENCY       : integer := 3;
			USE_MEMORY_BLOCKS   : integer := 1;
			USE_STORE_FORWARD   : integer := 0;
			USE_ALMOST_FULL_IF  : integer := 0;
			USE_ALMOST_EMPTY_IF : integer := 0
		);
		port (
			clk               : in  std_logic                     := 'X';             -- clk
			reset             : in  std_logic                     := 'X';             -- reset
			in_data           : in  std_logic_vector(92 downto 0) := (others => 'X'); -- data
			in_valid          : in  std_logic                     := 'X';             -- valid
			in_ready          : out std_logic;                                        -- ready
			in_startofpacket  : in  std_logic                     := 'X';             -- startofpacket
			in_endofpacket    : in  std_logic                     := 'X';             -- endofpacket
			out_data          : out std_logic_vector(92 downto 0);                    -- data
			out_valid         : out std_logic;                                        -- valid
			out_ready         : in  std_logic                     := 'X';             -- ready
			out_startofpacket : out std_logic;                                        -- startofpacket
			out_endofpacket   : out std_logic;                                        -- endofpacket
			csr_address       : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- address
			csr_read          : in  std_logic                     := 'X';             -- read
			csr_write         : in  std_logic                     := 'X';             -- write
			csr_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			csr_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			almost_full_data  : out std_logic;                                        -- data
			almost_empty_data : out std_logic;                                        -- data
			in_empty          : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- empty
			out_empty         : out std_logic_vector(0 downto 0);                     -- empty
			in_error          : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- error
			out_error         : out std_logic_vector(0 downto 0);                     -- error
			in_channel        : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- channel
			out_channel       : out std_logic_vector(0 downto 0)                      -- channel
		);
	end component altera_avalon_sc_fifo;

	component ddr3controller_s0_mm_interconnect_0_router is
		port (
			sink_ready         : out std_logic;                                        -- ready
			sink_valid         : in  std_logic                     := 'X';             -- valid
			sink_data          : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			sink_startofpacket : in  std_logic                     := 'X';             -- startofpacket
			sink_endofpacket   : in  std_logic                     := 'X';             -- endofpacket
			clk                : in  std_logic                     := 'X';             -- clk
			reset              : in  std_logic                     := 'X';             -- reset
			src_ready          : in  std_logic                     := 'X';             -- ready
			src_valid          : out std_logic;                                        -- valid
			src_data           : out std_logic_vector(91 downto 0);                    -- data
			src_channel        : out std_logic_vector(2 downto 0);                     -- channel
			src_startofpacket  : out std_logic;                                        -- startofpacket
			src_endofpacket    : out std_logic                                         -- endofpacket
		);
	end component ddr3controller_s0_mm_interconnect_0_router;

	component ddr3controller_s0_mm_interconnect_0_router_001 is
		port (
			sink_ready         : out std_logic;                                        -- ready
			sink_valid         : in  std_logic                     := 'X';             -- valid
			sink_data          : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			sink_startofpacket : in  std_logic                     := 'X';             -- startofpacket
			sink_endofpacket   : in  std_logic                     := 'X';             -- endofpacket
			clk                : in  std_logic                     := 'X';             -- clk
			reset              : in  std_logic                     := 'X';             -- reset
			src_ready          : in  std_logic                     := 'X';             -- ready
			src_valid          : out std_logic;                                        -- valid
			src_data           : out std_logic_vector(91 downto 0);                    -- data
			src_channel        : out std_logic_vector(2 downto 0);                     -- channel
			src_startofpacket  : out std_logic;                                        -- startofpacket
			src_endofpacket    : out std_logic                                         -- endofpacket
		);
	end component ddr3controller_s0_mm_interconnect_0_router_001;

	component ddr3controller_s0_mm_interconnect_0_cmd_demux is
		port (
			clk                : in  std_logic                     := 'X';             -- clk
			reset              : in  std_logic                     := 'X';             -- reset
			sink_ready         : out std_logic;                                        -- ready
			sink_channel       : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- channel
			sink_data          : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			sink_startofpacket : in  std_logic                     := 'X';             -- startofpacket
			sink_endofpacket   : in  std_logic                     := 'X';             -- endofpacket
			sink_valid         : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- valid
			src0_ready         : in  std_logic                     := 'X';             -- ready
			src0_valid         : out std_logic;                                        -- valid
			src0_data          : out std_logic_vector(91 downto 0);                    -- data
			src0_channel       : out std_logic_vector(2 downto 0);                     -- channel
			src0_startofpacket : out std_logic;                                        -- startofpacket
			src0_endofpacket   : out std_logic;                                        -- endofpacket
			src1_ready         : in  std_logic                     := 'X';             -- ready
			src1_valid         : out std_logic;                                        -- valid
			src1_data          : out std_logic_vector(91 downto 0);                    -- data
			src1_channel       : out std_logic_vector(2 downto 0);                     -- channel
			src1_startofpacket : out std_logic;                                        -- startofpacket
			src1_endofpacket   : out std_logic;                                        -- endofpacket
			src2_ready         : in  std_logic                     := 'X';             -- ready
			src2_valid         : out std_logic;                                        -- valid
			src2_data          : out std_logic_vector(91 downto 0);                    -- data
			src2_channel       : out std_logic_vector(2 downto 0);                     -- channel
			src2_startofpacket : out std_logic;                                        -- startofpacket
			src2_endofpacket   : out std_logic                                         -- endofpacket
		);
	end component ddr3controller_s0_mm_interconnect_0_cmd_demux;

	component ddr3controller_s0_mm_interconnect_0_cmd_mux is
		port (
			clk                 : in  std_logic                     := 'X';             -- clk
			reset               : in  std_logic                     := 'X';             -- reset
			src_ready           : in  std_logic                     := 'X';             -- ready
			src_valid           : out std_logic;                                        -- valid
			src_data            : out std_logic_vector(91 downto 0);                    -- data
			src_channel         : out std_logic_vector(2 downto 0);                     -- channel
			src_startofpacket   : out std_logic;                                        -- startofpacket
			src_endofpacket     : out std_logic;                                        -- endofpacket
			sink0_ready         : out std_logic;                                        -- ready
			sink0_valid         : in  std_logic                     := 'X';             -- valid
			sink0_channel       : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- channel
			sink0_data          : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			sink0_startofpacket : in  std_logic                     := 'X';             -- startofpacket
			sink0_endofpacket   : in  std_logic                     := 'X'              -- endofpacket
		);
	end component ddr3controller_s0_mm_interconnect_0_cmd_mux;

	component ddr3controller_s0_mm_interconnect_0_rsp_demux is
		port (
			clk                : in  std_logic                     := 'X';             -- clk
			reset              : in  std_logic                     := 'X';             -- reset
			sink_ready         : out std_logic;                                        -- ready
			sink_channel       : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- channel
			sink_data          : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			sink_startofpacket : in  std_logic                     := 'X';             -- startofpacket
			sink_endofpacket   : in  std_logic                     := 'X';             -- endofpacket
			sink_valid         : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- valid
			src0_ready         : in  std_logic                     := 'X';             -- ready
			src0_valid         : out std_logic;                                        -- valid
			src0_data          : out std_logic_vector(91 downto 0);                    -- data
			src0_channel       : out std_logic_vector(2 downto 0);                     -- channel
			src0_startofpacket : out std_logic;                                        -- startofpacket
			src0_endofpacket   : out std_logic                                         -- endofpacket
		);
	end component ddr3controller_s0_mm_interconnect_0_rsp_demux;

	component ddr3controller_s0_mm_interconnect_0_rsp_mux is
		port (
			clk                 : in  std_logic                     := 'X';             -- clk
			reset               : in  std_logic                     := 'X';             -- reset
			src_ready           : in  std_logic                     := 'X';             -- ready
			src_valid           : out std_logic;                                        -- valid
			src_data            : out std_logic_vector(91 downto 0);                    -- data
			src_channel         : out std_logic_vector(2 downto 0);                     -- channel
			src_startofpacket   : out std_logic;                                        -- startofpacket
			src_endofpacket     : out std_logic;                                        -- endofpacket
			sink0_ready         : out std_logic;                                        -- ready
			sink0_valid         : in  std_logic                     := 'X';             -- valid
			sink0_channel       : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- channel
			sink0_data          : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			sink0_startofpacket : in  std_logic                     := 'X';             -- startofpacket
			sink0_endofpacket   : in  std_logic                     := 'X';             -- endofpacket
			sink1_ready         : out std_logic;                                        -- ready
			sink1_valid         : in  std_logic                     := 'X';             -- valid
			sink1_channel       : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- channel
			sink1_data          : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			sink1_startofpacket : in  std_logic                     := 'X';             -- startofpacket
			sink1_endofpacket   : in  std_logic                     := 'X';             -- endofpacket
			sink2_ready         : out std_logic;                                        -- ready
			sink2_valid         : in  std_logic                     := 'X';             -- valid
			sink2_channel       : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- channel
			sink2_data          : in  std_logic_vector(91 downto 0) := (others => 'X'); -- data
			sink2_startofpacket : in  std_logic                     := 'X';             -- startofpacket
			sink2_endofpacket   : in  std_logic                     := 'X'              -- endofpacket
		);
	end component ddr3controller_s0_mm_interconnect_0_rsp_mux;

	component ddr3controller_s0_mm_interconnect_0_avalon_st_adapter is
		generic (
			inBitsPerSymbol : integer := 8;
			inUsePackets    : integer := 0;
			inDataWidth     : integer := 8;
			inChannelWidth  : integer := 3;
			inErrorWidth    : integer := 2;
			inUseEmptyPort  : integer := 0;
			inUseValid      : integer := 1;
			inUseReady      : integer := 1;
			inReadyLatency  : integer := 0;
			outDataWidth    : integer := 32;
			outChannelWidth : integer := 3;
			outErrorWidth   : integer := 2;
			outUseEmptyPort : integer := 0;
			outUseValid     : integer := 1;
			outUseReady     : integer := 1;
			outReadyLatency : integer := 0
		);
		port (
			in_clk_0_clk   : in  std_logic                     := 'X';             -- clk
			in_rst_0_reset : in  std_logic                     := 'X';             -- reset
			in_0_data      : in  std_logic_vector(33 downto 0) := (others => 'X'); -- data
			in_0_valid     : in  std_logic                     := 'X';             -- valid
			in_0_ready     : out std_logic;                                        -- ready
			out_0_data     : out std_logic_vector(33 downto 0);                    -- data
			out_0_valid    : out std_logic;                                        -- valid
			out_0_ready    : in  std_logic                     := 'X';             -- ready
			out_0_error    : out std_logic_vector(0 downto 0)                      -- error
		);
	end component ddr3controller_s0_mm_interconnect_0_avalon_st_adapter;

	signal cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest   : std_logic;                     -- cpu_inst_data_master_agent:av_waitrequest -> cpu_inst_data_master_translator:uav_waitrequest
	signal cpu_inst_data_master_translator_avalon_universal_master_0_readdata      : std_logic_vector(31 downto 0); -- cpu_inst_data_master_agent:av_readdata -> cpu_inst_data_master_translator:uav_readdata
	signal cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess   : std_logic;                     -- cpu_inst_data_master_translator:uav_debugaccess -> cpu_inst_data_master_agent:av_debugaccess
	signal cpu_inst_data_master_translator_avalon_universal_master_0_address       : std_logic_vector(19 downto 0); -- cpu_inst_data_master_translator:uav_address -> cpu_inst_data_master_agent:av_address
	signal cpu_inst_data_master_translator_avalon_universal_master_0_read          : std_logic;                     -- cpu_inst_data_master_translator:uav_read -> cpu_inst_data_master_agent:av_read
	signal cpu_inst_data_master_translator_avalon_universal_master_0_byteenable    : std_logic_vector(3 downto 0);  -- cpu_inst_data_master_translator:uav_byteenable -> cpu_inst_data_master_agent:av_byteenable
	signal cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid : std_logic;                     -- cpu_inst_data_master_agent:av_readdatavalid -> cpu_inst_data_master_translator:uav_readdatavalid
	signal cpu_inst_data_master_translator_avalon_universal_master_0_lock          : std_logic;                     -- cpu_inst_data_master_translator:uav_lock -> cpu_inst_data_master_agent:av_lock
	signal cpu_inst_data_master_translator_avalon_universal_master_0_write         : std_logic;                     -- cpu_inst_data_master_translator:uav_write -> cpu_inst_data_master_agent:av_write
	signal cpu_inst_data_master_translator_avalon_universal_master_0_writedata     : std_logic_vector(31 downto 0); -- cpu_inst_data_master_translator:uav_writedata -> cpu_inst_data_master_agent:av_writedata
	signal cpu_inst_data_master_translator_avalon_universal_master_0_burstcount    : std_logic_vector(2 downto 0);  -- cpu_inst_data_master_translator:uav_burstcount -> cpu_inst_data_master_agent:av_burstcount
	signal rsp_mux_src_valid                                                       : std_logic;                     -- rsp_mux:src_valid -> cpu_inst_data_master_agent:rp_valid
	signal rsp_mux_src_data                                                        : std_logic_vector(91 downto 0); -- rsp_mux:src_data -> cpu_inst_data_master_agent:rp_data
	signal rsp_mux_src_ready                                                       : std_logic;                     -- cpu_inst_data_master_agent:rp_ready -> rsp_mux:src_ready
	signal rsp_mux_src_channel                                                     : std_logic_vector(2 downto 0);  -- rsp_mux:src_channel -> cpu_inst_data_master_agent:rp_channel
	signal rsp_mux_src_startofpacket                                               : std_logic;                     -- rsp_mux:src_startofpacket -> cpu_inst_data_master_agent:rp_startofpacket
	signal rsp_mux_src_endofpacket                                                 : std_logic;                     -- rsp_mux:src_endofpacket -> cpu_inst_data_master_agent:rp_endofpacket
	signal sequencer_phy_mgr_inst_avl_agent_m0_readdata                            : std_logic_vector(31 downto 0); -- sequencer_phy_mgr_inst_avl_translator:uav_readdata -> sequencer_phy_mgr_inst_avl_agent:m0_readdata
	signal sequencer_phy_mgr_inst_avl_agent_m0_waitrequest                         : std_logic;                     -- sequencer_phy_mgr_inst_avl_translator:uav_waitrequest -> sequencer_phy_mgr_inst_avl_agent:m0_waitrequest
	signal sequencer_phy_mgr_inst_avl_agent_m0_debugaccess                         : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:m0_debugaccess -> sequencer_phy_mgr_inst_avl_translator:uav_debugaccess
	signal sequencer_phy_mgr_inst_avl_agent_m0_address                             : std_logic_vector(19 downto 0); -- sequencer_phy_mgr_inst_avl_agent:m0_address -> sequencer_phy_mgr_inst_avl_translator:uav_address
	signal sequencer_phy_mgr_inst_avl_agent_m0_byteenable                          : std_logic_vector(3 downto 0);  -- sequencer_phy_mgr_inst_avl_agent:m0_byteenable -> sequencer_phy_mgr_inst_avl_translator:uav_byteenable
	signal sequencer_phy_mgr_inst_avl_agent_m0_read                                : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:m0_read -> sequencer_phy_mgr_inst_avl_translator:uav_read
	signal sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid                       : std_logic;                     -- sequencer_phy_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_phy_mgr_inst_avl_agent:m0_readdatavalid
	signal sequencer_phy_mgr_inst_avl_agent_m0_lock                                : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:m0_lock -> sequencer_phy_mgr_inst_avl_translator:uav_lock
	signal sequencer_phy_mgr_inst_avl_agent_m0_writedata                           : std_logic_vector(31 downto 0); -- sequencer_phy_mgr_inst_avl_agent:m0_writedata -> sequencer_phy_mgr_inst_avl_translator:uav_writedata
	signal sequencer_phy_mgr_inst_avl_agent_m0_write                               : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:m0_write -> sequencer_phy_mgr_inst_avl_translator:uav_write
	signal sequencer_phy_mgr_inst_avl_agent_m0_burstcount                          : std_logic_vector(2 downto 0);  -- sequencer_phy_mgr_inst_avl_agent:m0_burstcount -> sequencer_phy_mgr_inst_avl_translator:uav_burstcount
	signal sequencer_phy_mgr_inst_avl_agent_rf_source_valid                        : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:rf_source_valid -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_valid
	signal sequencer_phy_mgr_inst_avl_agent_rf_source_data                         : std_logic_vector(92 downto 0); -- sequencer_phy_mgr_inst_avl_agent:rf_source_data -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_data
	signal sequencer_phy_mgr_inst_avl_agent_rf_source_ready                        : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_phy_mgr_inst_avl_agent:rf_source_ready
	signal sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket                : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
	signal sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket                  : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
	signal sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid                     : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_phy_mgr_inst_avl_agent:rf_sink_valid
	signal sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data                      : std_logic_vector(92 downto 0); -- sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_phy_mgr_inst_avl_agent:rf_sink_data
	signal sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready                     : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:rf_sink_ready -> sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_ready
	signal sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket             : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_phy_mgr_inst_avl_agent:rf_sink_startofpacket
	signal sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket               : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_phy_mgr_inst_avl_agent:rf_sink_endofpacket
	signal cmd_mux_src_valid                                                       : std_logic;                     -- cmd_mux:src_valid -> sequencer_phy_mgr_inst_avl_agent:cp_valid
	signal cmd_mux_src_data                                                        : std_logic_vector(91 downto 0); -- cmd_mux:src_data -> sequencer_phy_mgr_inst_avl_agent:cp_data
	signal cmd_mux_src_ready                                                       : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:cp_ready -> cmd_mux:src_ready
	signal cmd_mux_src_channel                                                     : std_logic_vector(2 downto 0);  -- cmd_mux:src_channel -> sequencer_phy_mgr_inst_avl_agent:cp_channel
	signal cmd_mux_src_startofpacket                                               : std_logic;                     -- cmd_mux:src_startofpacket -> sequencer_phy_mgr_inst_avl_agent:cp_startofpacket
	signal cmd_mux_src_endofpacket                                                 : std_logic;                     -- cmd_mux:src_endofpacket -> sequencer_phy_mgr_inst_avl_agent:cp_endofpacket
	signal sequencer_rw_mgr_inst_avl_agent_m0_readdata                             : std_logic_vector(31 downto 0); -- sequencer_rw_mgr_inst_avl_translator:uav_readdata -> sequencer_rw_mgr_inst_avl_agent:m0_readdata
	signal sequencer_rw_mgr_inst_avl_agent_m0_waitrequest                          : std_logic;                     -- sequencer_rw_mgr_inst_avl_translator:uav_waitrequest -> sequencer_rw_mgr_inst_avl_agent:m0_waitrequest
	signal sequencer_rw_mgr_inst_avl_agent_m0_debugaccess                          : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:m0_debugaccess -> sequencer_rw_mgr_inst_avl_translator:uav_debugaccess
	signal sequencer_rw_mgr_inst_avl_agent_m0_address                              : std_logic_vector(19 downto 0); -- sequencer_rw_mgr_inst_avl_agent:m0_address -> sequencer_rw_mgr_inst_avl_translator:uav_address
	signal sequencer_rw_mgr_inst_avl_agent_m0_byteenable                           : std_logic_vector(3 downto 0);  -- sequencer_rw_mgr_inst_avl_agent:m0_byteenable -> sequencer_rw_mgr_inst_avl_translator:uav_byteenable
	signal sequencer_rw_mgr_inst_avl_agent_m0_read                                 : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:m0_read -> sequencer_rw_mgr_inst_avl_translator:uav_read
	signal sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid                        : std_logic;                     -- sequencer_rw_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_rw_mgr_inst_avl_agent:m0_readdatavalid
	signal sequencer_rw_mgr_inst_avl_agent_m0_lock                                 : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:m0_lock -> sequencer_rw_mgr_inst_avl_translator:uav_lock
	signal sequencer_rw_mgr_inst_avl_agent_m0_writedata                            : std_logic_vector(31 downto 0); -- sequencer_rw_mgr_inst_avl_agent:m0_writedata -> sequencer_rw_mgr_inst_avl_translator:uav_writedata
	signal sequencer_rw_mgr_inst_avl_agent_m0_write                                : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:m0_write -> sequencer_rw_mgr_inst_avl_translator:uav_write
	signal sequencer_rw_mgr_inst_avl_agent_m0_burstcount                           : std_logic_vector(2 downto 0);  -- sequencer_rw_mgr_inst_avl_agent:m0_burstcount -> sequencer_rw_mgr_inst_avl_translator:uav_burstcount
	signal sequencer_rw_mgr_inst_avl_agent_rf_source_valid                         : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:rf_source_valid -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_valid
	signal sequencer_rw_mgr_inst_avl_agent_rf_source_data                          : std_logic_vector(92 downto 0); -- sequencer_rw_mgr_inst_avl_agent:rf_source_data -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_data
	signal sequencer_rw_mgr_inst_avl_agent_rf_source_ready                         : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_rw_mgr_inst_avl_agent:rf_source_ready
	signal sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket                 : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
	signal sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket                   : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
	signal sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid                      : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_rw_mgr_inst_avl_agent:rf_sink_valid
	signal sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data                       : std_logic_vector(92 downto 0); -- sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_rw_mgr_inst_avl_agent:rf_sink_data
	signal sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready                      : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:rf_sink_ready -> sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_ready
	signal sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket              : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_rw_mgr_inst_avl_agent:rf_sink_startofpacket
	signal sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket                : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_rw_mgr_inst_avl_agent:rf_sink_endofpacket
	signal cmd_mux_001_src_valid                                                   : std_logic;                     -- cmd_mux_001:src_valid -> sequencer_rw_mgr_inst_avl_agent:cp_valid
	signal cmd_mux_001_src_data                                                    : std_logic_vector(91 downto 0); -- cmd_mux_001:src_data -> sequencer_rw_mgr_inst_avl_agent:cp_data
	signal cmd_mux_001_src_ready                                                   : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:cp_ready -> cmd_mux_001:src_ready
	signal cmd_mux_001_src_channel                                                 : std_logic_vector(2 downto 0);  -- cmd_mux_001:src_channel -> sequencer_rw_mgr_inst_avl_agent:cp_channel
	signal cmd_mux_001_src_startofpacket                                           : std_logic;                     -- cmd_mux_001:src_startofpacket -> sequencer_rw_mgr_inst_avl_agent:cp_startofpacket
	signal cmd_mux_001_src_endofpacket                                             : std_logic;                     -- cmd_mux_001:src_endofpacket -> sequencer_rw_mgr_inst_avl_agent:cp_endofpacket
	signal sequencer_pll_mgr_inst_avl_agent_m0_readdata                            : std_logic_vector(31 downto 0); -- sequencer_pll_mgr_inst_avl_translator:uav_readdata -> sequencer_pll_mgr_inst_avl_agent:m0_readdata
	signal sequencer_pll_mgr_inst_avl_agent_m0_waitrequest                         : std_logic;                     -- sequencer_pll_mgr_inst_avl_translator:uav_waitrequest -> sequencer_pll_mgr_inst_avl_agent:m0_waitrequest
	signal sequencer_pll_mgr_inst_avl_agent_m0_debugaccess                         : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:m0_debugaccess -> sequencer_pll_mgr_inst_avl_translator:uav_debugaccess
	signal sequencer_pll_mgr_inst_avl_agent_m0_address                             : std_logic_vector(19 downto 0); -- sequencer_pll_mgr_inst_avl_agent:m0_address -> sequencer_pll_mgr_inst_avl_translator:uav_address
	signal sequencer_pll_mgr_inst_avl_agent_m0_byteenable                          : std_logic_vector(3 downto 0);  -- sequencer_pll_mgr_inst_avl_agent:m0_byteenable -> sequencer_pll_mgr_inst_avl_translator:uav_byteenable
	signal sequencer_pll_mgr_inst_avl_agent_m0_read                                : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:m0_read -> sequencer_pll_mgr_inst_avl_translator:uav_read
	signal sequencer_pll_mgr_inst_avl_agent_m0_readdatavalid                       : std_logic;                     -- sequencer_pll_mgr_inst_avl_translator:uav_readdatavalid -> sequencer_pll_mgr_inst_avl_agent:m0_readdatavalid
	signal sequencer_pll_mgr_inst_avl_agent_m0_lock                                : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:m0_lock -> sequencer_pll_mgr_inst_avl_translator:uav_lock
	signal sequencer_pll_mgr_inst_avl_agent_m0_writedata                           : std_logic_vector(31 downto 0); -- sequencer_pll_mgr_inst_avl_agent:m0_writedata -> sequencer_pll_mgr_inst_avl_translator:uav_writedata
	signal sequencer_pll_mgr_inst_avl_agent_m0_write                               : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:m0_write -> sequencer_pll_mgr_inst_avl_translator:uav_write
	signal sequencer_pll_mgr_inst_avl_agent_m0_burstcount                          : std_logic_vector(2 downto 0);  -- sequencer_pll_mgr_inst_avl_agent:m0_burstcount -> sequencer_pll_mgr_inst_avl_translator:uav_burstcount
	signal sequencer_pll_mgr_inst_avl_agent_rf_source_valid                        : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:rf_source_valid -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_valid
	signal sequencer_pll_mgr_inst_avl_agent_rf_source_data                         : std_logic_vector(92 downto 0); -- sequencer_pll_mgr_inst_avl_agent:rf_source_data -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_data
	signal sequencer_pll_mgr_inst_avl_agent_rf_source_ready                        : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_ready -> sequencer_pll_mgr_inst_avl_agent:rf_source_ready
	signal sequencer_pll_mgr_inst_avl_agent_rf_source_startofpacket                : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:rf_source_startofpacket -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_startofpacket
	signal sequencer_pll_mgr_inst_avl_agent_rf_source_endofpacket                  : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:rf_source_endofpacket -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:in_endofpacket
	signal sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_valid                     : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_valid -> sequencer_pll_mgr_inst_avl_agent:rf_sink_valid
	signal sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_data                      : std_logic_vector(92 downto 0); -- sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_data -> sequencer_pll_mgr_inst_avl_agent:rf_sink_data
	signal sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_ready                     : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:rf_sink_ready -> sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_ready
	signal sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_startofpacket             : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_startofpacket -> sequencer_pll_mgr_inst_avl_agent:rf_sink_startofpacket
	signal sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_endofpacket               : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent_rsp_fifo:out_endofpacket -> sequencer_pll_mgr_inst_avl_agent:rf_sink_endofpacket
	signal cmd_mux_002_src_valid                                                   : std_logic;                     -- cmd_mux_002:src_valid -> sequencer_pll_mgr_inst_avl_agent:cp_valid
	signal cmd_mux_002_src_data                                                    : std_logic_vector(91 downto 0); -- cmd_mux_002:src_data -> sequencer_pll_mgr_inst_avl_agent:cp_data
	signal cmd_mux_002_src_ready                                                   : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:cp_ready -> cmd_mux_002:src_ready
	signal cmd_mux_002_src_channel                                                 : std_logic_vector(2 downto 0);  -- cmd_mux_002:src_channel -> sequencer_pll_mgr_inst_avl_agent:cp_channel
	signal cmd_mux_002_src_startofpacket                                           : std_logic;                     -- cmd_mux_002:src_startofpacket -> sequencer_pll_mgr_inst_avl_agent:cp_startofpacket
	signal cmd_mux_002_src_endofpacket                                             : std_logic;                     -- cmd_mux_002:src_endofpacket -> sequencer_pll_mgr_inst_avl_agent:cp_endofpacket
	signal cpu_inst_data_master_agent_cp_valid                                     : std_logic;                     -- cpu_inst_data_master_agent:cp_valid -> router:sink_valid
	signal cpu_inst_data_master_agent_cp_data                                      : std_logic_vector(91 downto 0); -- cpu_inst_data_master_agent:cp_data -> router:sink_data
	signal cpu_inst_data_master_agent_cp_ready                                     : std_logic;                     -- router:sink_ready -> cpu_inst_data_master_agent:cp_ready
	signal cpu_inst_data_master_agent_cp_startofpacket                             : std_logic;                     -- cpu_inst_data_master_agent:cp_startofpacket -> router:sink_startofpacket
	signal cpu_inst_data_master_agent_cp_endofpacket                               : std_logic;                     -- cpu_inst_data_master_agent:cp_endofpacket -> router:sink_endofpacket
	signal router_src_valid                                                        : std_logic;                     -- router:src_valid -> cmd_demux:sink_valid
	signal router_src_data                                                         : std_logic_vector(91 downto 0); -- router:src_data -> cmd_demux:sink_data
	signal router_src_ready                                                        : std_logic;                     -- cmd_demux:sink_ready -> router:src_ready
	signal router_src_channel                                                      : std_logic_vector(2 downto 0);  -- router:src_channel -> cmd_demux:sink_channel
	signal router_src_startofpacket                                                : std_logic;                     -- router:src_startofpacket -> cmd_demux:sink_startofpacket
	signal router_src_endofpacket                                                  : std_logic;                     -- router:src_endofpacket -> cmd_demux:sink_endofpacket
	signal sequencer_phy_mgr_inst_avl_agent_rp_valid                               : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:rp_valid -> router_001:sink_valid
	signal sequencer_phy_mgr_inst_avl_agent_rp_data                                : std_logic_vector(91 downto 0); -- sequencer_phy_mgr_inst_avl_agent:rp_data -> router_001:sink_data
	signal sequencer_phy_mgr_inst_avl_agent_rp_ready                               : std_logic;                     -- router_001:sink_ready -> sequencer_phy_mgr_inst_avl_agent:rp_ready
	signal sequencer_phy_mgr_inst_avl_agent_rp_startofpacket                       : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:rp_startofpacket -> router_001:sink_startofpacket
	signal sequencer_phy_mgr_inst_avl_agent_rp_endofpacket                         : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:rp_endofpacket -> router_001:sink_endofpacket
	signal router_001_src_valid                                                    : std_logic;                     -- router_001:src_valid -> rsp_demux:sink_valid
	signal router_001_src_data                                                     : std_logic_vector(91 downto 0); -- router_001:src_data -> rsp_demux:sink_data
	signal router_001_src_ready                                                    : std_logic;                     -- rsp_demux:sink_ready -> router_001:src_ready
	signal router_001_src_channel                                                  : std_logic_vector(2 downto 0);  -- router_001:src_channel -> rsp_demux:sink_channel
	signal router_001_src_startofpacket                                            : std_logic;                     -- router_001:src_startofpacket -> rsp_demux:sink_startofpacket
	signal router_001_src_endofpacket                                              : std_logic;                     -- router_001:src_endofpacket -> rsp_demux:sink_endofpacket
	signal sequencer_rw_mgr_inst_avl_agent_rp_valid                                : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:rp_valid -> router_002:sink_valid
	signal sequencer_rw_mgr_inst_avl_agent_rp_data                                 : std_logic_vector(91 downto 0); -- sequencer_rw_mgr_inst_avl_agent:rp_data -> router_002:sink_data
	signal sequencer_rw_mgr_inst_avl_agent_rp_ready                                : std_logic;                     -- router_002:sink_ready -> sequencer_rw_mgr_inst_avl_agent:rp_ready
	signal sequencer_rw_mgr_inst_avl_agent_rp_startofpacket                        : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:rp_startofpacket -> router_002:sink_startofpacket
	signal sequencer_rw_mgr_inst_avl_agent_rp_endofpacket                          : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:rp_endofpacket -> router_002:sink_endofpacket
	signal router_002_src_valid                                                    : std_logic;                     -- router_002:src_valid -> rsp_demux_001:sink_valid
	signal router_002_src_data                                                     : std_logic_vector(91 downto 0); -- router_002:src_data -> rsp_demux_001:sink_data
	signal router_002_src_ready                                                    : std_logic;                     -- rsp_demux_001:sink_ready -> router_002:src_ready
	signal router_002_src_channel                                                  : std_logic_vector(2 downto 0);  -- router_002:src_channel -> rsp_demux_001:sink_channel
	signal router_002_src_startofpacket                                            : std_logic;                     -- router_002:src_startofpacket -> rsp_demux_001:sink_startofpacket
	signal router_002_src_endofpacket                                              : std_logic;                     -- router_002:src_endofpacket -> rsp_demux_001:sink_endofpacket
	signal sequencer_pll_mgr_inst_avl_agent_rp_valid                               : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:rp_valid -> router_003:sink_valid
	signal sequencer_pll_mgr_inst_avl_agent_rp_data                                : std_logic_vector(91 downto 0); -- sequencer_pll_mgr_inst_avl_agent:rp_data -> router_003:sink_data
	signal sequencer_pll_mgr_inst_avl_agent_rp_ready                               : std_logic;                     -- router_003:sink_ready -> sequencer_pll_mgr_inst_avl_agent:rp_ready
	signal sequencer_pll_mgr_inst_avl_agent_rp_startofpacket                       : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:rp_startofpacket -> router_003:sink_startofpacket
	signal sequencer_pll_mgr_inst_avl_agent_rp_endofpacket                         : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:rp_endofpacket -> router_003:sink_endofpacket
	signal router_003_src_valid                                                    : std_logic;                     -- router_003:src_valid -> rsp_demux_002:sink_valid
	signal router_003_src_data                                                     : std_logic_vector(91 downto 0); -- router_003:src_data -> rsp_demux_002:sink_data
	signal router_003_src_ready                                                    : std_logic;                     -- rsp_demux_002:sink_ready -> router_003:src_ready
	signal router_003_src_channel                                                  : std_logic_vector(2 downto 0);  -- router_003:src_channel -> rsp_demux_002:sink_channel
	signal router_003_src_startofpacket                                            : std_logic;                     -- router_003:src_startofpacket -> rsp_demux_002:sink_startofpacket
	signal router_003_src_endofpacket                                              : std_logic;                     -- router_003:src_endofpacket -> rsp_demux_002:sink_endofpacket
	signal cmd_demux_src0_valid                                                    : std_logic;                     -- cmd_demux:src0_valid -> cmd_mux:sink0_valid
	signal cmd_demux_src0_data                                                     : std_logic_vector(91 downto 0); -- cmd_demux:src0_data -> cmd_mux:sink0_data
	signal cmd_demux_src0_ready                                                    : std_logic;                     -- cmd_mux:sink0_ready -> cmd_demux:src0_ready
	signal cmd_demux_src0_channel                                                  : std_logic_vector(2 downto 0);  -- cmd_demux:src0_channel -> cmd_mux:sink0_channel
	signal cmd_demux_src0_startofpacket                                            : std_logic;                     -- cmd_demux:src0_startofpacket -> cmd_mux:sink0_startofpacket
	signal cmd_demux_src0_endofpacket                                              : std_logic;                     -- cmd_demux:src0_endofpacket -> cmd_mux:sink0_endofpacket
	signal cmd_demux_src1_valid                                                    : std_logic;                     -- cmd_demux:src1_valid -> cmd_mux_001:sink0_valid
	signal cmd_demux_src1_data                                                     : std_logic_vector(91 downto 0); -- cmd_demux:src1_data -> cmd_mux_001:sink0_data
	signal cmd_demux_src1_ready                                                    : std_logic;                     -- cmd_mux_001:sink0_ready -> cmd_demux:src1_ready
	signal cmd_demux_src1_channel                                                  : std_logic_vector(2 downto 0);  -- cmd_demux:src1_channel -> cmd_mux_001:sink0_channel
	signal cmd_demux_src1_startofpacket                                            : std_logic;                     -- cmd_demux:src1_startofpacket -> cmd_mux_001:sink0_startofpacket
	signal cmd_demux_src1_endofpacket                                              : std_logic;                     -- cmd_demux:src1_endofpacket -> cmd_mux_001:sink0_endofpacket
	signal cmd_demux_src2_valid                                                    : std_logic;                     -- cmd_demux:src2_valid -> cmd_mux_002:sink0_valid
	signal cmd_demux_src2_data                                                     : std_logic_vector(91 downto 0); -- cmd_demux:src2_data -> cmd_mux_002:sink0_data
	signal cmd_demux_src2_ready                                                    : std_logic;                     -- cmd_mux_002:sink0_ready -> cmd_demux:src2_ready
	signal cmd_demux_src2_channel                                                  : std_logic_vector(2 downto 0);  -- cmd_demux:src2_channel -> cmd_mux_002:sink0_channel
	signal cmd_demux_src2_startofpacket                                            : std_logic;                     -- cmd_demux:src2_startofpacket -> cmd_mux_002:sink0_startofpacket
	signal cmd_demux_src2_endofpacket                                              : std_logic;                     -- cmd_demux:src2_endofpacket -> cmd_mux_002:sink0_endofpacket
	signal rsp_demux_src0_valid                                                    : std_logic;                     -- rsp_demux:src0_valid -> rsp_mux:sink0_valid
	signal rsp_demux_src0_data                                                     : std_logic_vector(91 downto 0); -- rsp_demux:src0_data -> rsp_mux:sink0_data
	signal rsp_demux_src0_ready                                                    : std_logic;                     -- rsp_mux:sink0_ready -> rsp_demux:src0_ready
	signal rsp_demux_src0_channel                                                  : std_logic_vector(2 downto 0);  -- rsp_demux:src0_channel -> rsp_mux:sink0_channel
	signal rsp_demux_src0_startofpacket                                            : std_logic;                     -- rsp_demux:src0_startofpacket -> rsp_mux:sink0_startofpacket
	signal rsp_demux_src0_endofpacket                                              : std_logic;                     -- rsp_demux:src0_endofpacket -> rsp_mux:sink0_endofpacket
	signal rsp_demux_001_src0_valid                                                : std_logic;                     -- rsp_demux_001:src0_valid -> rsp_mux:sink1_valid
	signal rsp_demux_001_src0_data                                                 : std_logic_vector(91 downto 0); -- rsp_demux_001:src0_data -> rsp_mux:sink1_data
	signal rsp_demux_001_src0_ready                                                : std_logic;                     -- rsp_mux:sink1_ready -> rsp_demux_001:src0_ready
	signal rsp_demux_001_src0_channel                                              : std_logic_vector(2 downto 0);  -- rsp_demux_001:src0_channel -> rsp_mux:sink1_channel
	signal rsp_demux_001_src0_startofpacket                                        : std_logic;                     -- rsp_demux_001:src0_startofpacket -> rsp_mux:sink1_startofpacket
	signal rsp_demux_001_src0_endofpacket                                          : std_logic;                     -- rsp_demux_001:src0_endofpacket -> rsp_mux:sink1_endofpacket
	signal rsp_demux_002_src0_valid                                                : std_logic;                     -- rsp_demux_002:src0_valid -> rsp_mux:sink2_valid
	signal rsp_demux_002_src0_data                                                 : std_logic_vector(91 downto 0); -- rsp_demux_002:src0_data -> rsp_mux:sink2_data
	signal rsp_demux_002_src0_ready                                                : std_logic;                     -- rsp_mux:sink2_ready -> rsp_demux_002:src0_ready
	signal rsp_demux_002_src0_channel                                              : std_logic_vector(2 downto 0);  -- rsp_demux_002:src0_channel -> rsp_mux:sink2_channel
	signal rsp_demux_002_src0_startofpacket                                        : std_logic;                     -- rsp_demux_002:src0_startofpacket -> rsp_mux:sink2_startofpacket
	signal rsp_demux_002_src0_endofpacket                                          : std_logic;                     -- rsp_demux_002:src0_endofpacket -> rsp_mux:sink2_endofpacket
	signal sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid                   : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter:in_0_valid
	signal sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data                    : std_logic_vector(33 downto 0); -- sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter:in_0_data
	signal sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready                   : std_logic;                     -- avalon_st_adapter:in_0_ready -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_src_ready
	signal avalon_st_adapter_out_0_valid                                           : std_logic;                     -- avalon_st_adapter:out_0_valid -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_valid
	signal avalon_st_adapter_out_0_data                                            : std_logic_vector(33 downto 0); -- avalon_st_adapter:out_0_data -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_data
	signal avalon_st_adapter_out_0_ready                                           : std_logic;                     -- sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter:out_0_ready
	signal avalon_st_adapter_out_0_error                                           : std_logic_vector(0 downto 0);  -- avalon_st_adapter:out_0_error -> sequencer_phy_mgr_inst_avl_agent:rdata_fifo_sink_error
	signal sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid                    : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_001:in_0_valid
	signal sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data                     : std_logic_vector(33 downto 0); -- sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_001:in_0_data
	signal sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready                    : std_logic;                     -- avalon_st_adapter_001:in_0_ready -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_src_ready
	signal avalon_st_adapter_001_out_0_valid                                       : std_logic;                     -- avalon_st_adapter_001:out_0_valid -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_valid
	signal avalon_st_adapter_001_out_0_data                                        : std_logic_vector(33 downto 0); -- avalon_st_adapter_001:out_0_data -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_data
	signal avalon_st_adapter_001_out_0_ready                                       : std_logic;                     -- sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_001:out_0_ready
	signal avalon_st_adapter_001_out_0_error                                       : std_logic_vector(0 downto 0);  -- avalon_st_adapter_001:out_0_error -> sequencer_rw_mgr_inst_avl_agent:rdata_fifo_sink_error
	signal sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_valid                   : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:rdata_fifo_src_valid -> avalon_st_adapter_002:in_0_valid
	signal sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_data                    : std_logic_vector(33 downto 0); -- sequencer_pll_mgr_inst_avl_agent:rdata_fifo_src_data -> avalon_st_adapter_002:in_0_data
	signal sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_ready                   : std_logic;                     -- avalon_st_adapter_002:in_0_ready -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_src_ready
	signal avalon_st_adapter_002_out_0_valid                                       : std_logic;                     -- avalon_st_adapter_002:out_0_valid -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_valid
	signal avalon_st_adapter_002_out_0_data                                        : std_logic_vector(33 downto 0); -- avalon_st_adapter_002:out_0_data -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_data
	signal avalon_st_adapter_002_out_0_ready                                       : std_logic;                     -- sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_ready -> avalon_st_adapter_002:out_0_ready
	signal avalon_st_adapter_002_out_0_error                                       : std_logic_vector(0 downto 0);  -- avalon_st_adapter_002:out_0_error -> sequencer_pll_mgr_inst_avl_agent:rdata_fifo_sink_error

begin

	cpu_inst_data_master_translator : component altera_merlin_master_translator
		generic map (
			AV_ADDRESS_W                => 20,
			AV_DATA_W                   => 32,
			AV_BURSTCOUNT_W             => 1,
			AV_BYTEENABLE_W             => 4,
			UAV_ADDRESS_W               => 20,
			UAV_BURSTCOUNT_W            => 3,
			USE_READ                    => 1,
			USE_WRITE                   => 1,
			USE_BEGINBURSTTRANSFER      => 0,
			USE_BEGINTRANSFER           => 0,
			USE_CHIPSELECT              => 0,
			USE_BURSTCOUNT              => 0,
			USE_READDATAVALID           => 0,
			USE_WAITREQUEST             => 1,
			USE_READRESPONSE            => 0,
			USE_WRITERESPONSE           => 0,
			AV_SYMBOLS_PER_WORD         => 4,
			AV_ADDRESS_SYMBOLS          => 1,
			AV_BURSTCOUNT_SYMBOLS       => 0,
			AV_CONSTANT_BURST_BEHAVIOR  => 0,
			UAV_CONSTANT_BURST_BEHAVIOR => 0,
			AV_LINEWRAPBURSTS           => 0,
			AV_REGISTERINCOMINGSIGNALS  => 0
		)
		port map (
			clk                    => avl_clk_out_clk_clk,                                                     --                       clk.clk
			reset                  => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset,            --                     reset.reset
			uav_address            => cpu_inst_data_master_translator_avalon_universal_master_0_address,       -- avalon_universal_master_0.address
			uav_burstcount         => cpu_inst_data_master_translator_avalon_universal_master_0_burstcount,    --                          .burstcount
			uav_read               => cpu_inst_data_master_translator_avalon_universal_master_0_read,          --                          .read
			uav_write              => cpu_inst_data_master_translator_avalon_universal_master_0_write,         --                          .write
			uav_waitrequest        => cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest,   --                          .waitrequest
			uav_readdatavalid      => cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid, --                          .readdatavalid
			uav_byteenable         => cpu_inst_data_master_translator_avalon_universal_master_0_byteenable,    --                          .byteenable
			uav_readdata           => cpu_inst_data_master_translator_avalon_universal_master_0_readdata,      --                          .readdata
			uav_writedata          => cpu_inst_data_master_translator_avalon_universal_master_0_writedata,     --                          .writedata
			uav_lock               => cpu_inst_data_master_translator_avalon_universal_master_0_lock,          --                          .lock
			uav_debugaccess        => cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess,   --                          .debugaccess
			av_address             => cpu_inst_data_master_address,                                            --      avalon_anti_master_0.address
			av_waitrequest         => cpu_inst_data_master_waitrequest,                                        --                          .waitrequest
			av_read                => cpu_inst_data_master_read,                                               --                          .read
			av_readdata            => cpu_inst_data_master_readdata,                                           --                          .readdata
			av_write               => cpu_inst_data_master_write,                                              --                          .write
			av_writedata           => cpu_inst_data_master_writedata,                                          --                          .writedata
			av_burstcount          => "1",                                                                     --               (terminated)
			av_byteenable          => "1111",                                                                  --               (terminated)
			av_beginbursttransfer  => '0',                                                                     --               (terminated)
			av_begintransfer       => '0',                                                                     --               (terminated)
			av_chipselect          => '0',                                                                     --               (terminated)
			av_readdatavalid       => open,                                                                    --               (terminated)
			av_lock                => '0',                                                                     --               (terminated)
			av_debugaccess         => '0',                                                                     --               (terminated)
			uav_clken              => open,                                                                    --               (terminated)
			av_clken               => '1',                                                                     --               (terminated)
			uav_response           => "00",                                                                    --               (terminated)
			av_response            => open,                                                                    --               (terminated)
			uav_writeresponsevalid => '0',                                                                     --               (terminated)
			av_writeresponsevalid  => open                                                                     --               (terminated)
		);

	sequencer_phy_mgr_inst_avl_translator : component altera_merlin_slave_translator
		generic map (
			AV_ADDRESS_W                   => 13,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 1,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 20,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 0,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 0,
			AV_BURSTCOUNT_SYMBOLS          => 0,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 1,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0
		)
		port map (
			clk                    => avl_clk_out_clk_clk,                                          --                      clk.clk
			reset                  => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, --                    reset.reset
			uav_address            => sequencer_phy_mgr_inst_avl_agent_m0_address,                  -- avalon_universal_slave_0.address
			uav_burstcount         => sequencer_phy_mgr_inst_avl_agent_m0_burstcount,               --                         .burstcount
			uav_read               => sequencer_phy_mgr_inst_avl_agent_m0_read,                     --                         .read
			uav_write              => sequencer_phy_mgr_inst_avl_agent_m0_write,                    --                         .write
			uav_waitrequest        => sequencer_phy_mgr_inst_avl_agent_m0_waitrequest,              --                         .waitrequest
			uav_readdatavalid      => sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid,            --                         .readdatavalid
			uav_byteenable         => sequencer_phy_mgr_inst_avl_agent_m0_byteenable,               --                         .byteenable
			uav_readdata           => sequencer_phy_mgr_inst_avl_agent_m0_readdata,                 --                         .readdata
			uav_writedata          => sequencer_phy_mgr_inst_avl_agent_m0_writedata,                --                         .writedata
			uav_lock               => sequencer_phy_mgr_inst_avl_agent_m0_lock,                     --                         .lock
			uav_debugaccess        => sequencer_phy_mgr_inst_avl_agent_m0_debugaccess,              --                         .debugaccess
			av_address             => sequencer_phy_mgr_inst_avl_address,                           --      avalon_anti_slave_0.address
			av_write               => sequencer_phy_mgr_inst_avl_write,                             --                         .write
			av_read                => sequencer_phy_mgr_inst_avl_read,                              --                         .read
			av_readdata            => sequencer_phy_mgr_inst_avl_readdata,                          --                         .readdata
			av_writedata           => sequencer_phy_mgr_inst_avl_writedata,                         --                         .writedata
			av_waitrequest         => sequencer_phy_mgr_inst_avl_waitrequest,                       --                         .waitrequest
			av_begintransfer       => open,                                                         --              (terminated)
			av_beginbursttransfer  => open,                                                         --              (terminated)
			av_burstcount          => open,                                                         --              (terminated)
			av_byteenable          => open,                                                         --              (terminated)
			av_readdatavalid       => '0',                                                          --              (terminated)
			av_writebyteenable     => open,                                                         --              (terminated)
			av_lock                => open,                                                         --              (terminated)
			av_chipselect          => open,                                                         --              (terminated)
			av_clken               => open,                                                         --              (terminated)
			uav_clken              => '0',                                                          --              (terminated)
			av_debugaccess         => open,                                                         --              (terminated)
			av_outputenable        => open,                                                         --              (terminated)
			uav_response           => open,                                                         --              (terminated)
			av_response            => "00",                                                         --              (terminated)
			uav_writeresponsevalid => open,                                                         --              (terminated)
			av_writeresponsevalid  => '0'                                                           --              (terminated)
		);

	sequencer_rw_mgr_inst_avl_translator : component altera_merlin_slave_translator
		generic map (
			AV_ADDRESS_W                   => 13,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 1,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 20,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 0,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 0,
			AV_BURSTCOUNT_SYMBOLS          => 0,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 1,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0
		)
		port map (
			clk                    => avl_clk_out_clk_clk,                                          --                      clk.clk
			reset                  => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, --                    reset.reset
			uav_address            => sequencer_rw_mgr_inst_avl_agent_m0_address,                   -- avalon_universal_slave_0.address
			uav_burstcount         => sequencer_rw_mgr_inst_avl_agent_m0_burstcount,                --                         .burstcount
			uav_read               => sequencer_rw_mgr_inst_avl_agent_m0_read,                      --                         .read
			uav_write              => sequencer_rw_mgr_inst_avl_agent_m0_write,                     --                         .write
			uav_waitrequest        => sequencer_rw_mgr_inst_avl_agent_m0_waitrequest,               --                         .waitrequest
			uav_readdatavalid      => sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid,             --                         .readdatavalid
			uav_byteenable         => sequencer_rw_mgr_inst_avl_agent_m0_byteenable,                --                         .byteenable
			uav_readdata           => sequencer_rw_mgr_inst_avl_agent_m0_readdata,                  --                         .readdata
			uav_writedata          => sequencer_rw_mgr_inst_avl_agent_m0_writedata,                 --                         .writedata
			uav_lock               => sequencer_rw_mgr_inst_avl_agent_m0_lock,                      --                         .lock
			uav_debugaccess        => sequencer_rw_mgr_inst_avl_agent_m0_debugaccess,               --                         .debugaccess
			av_address             => sequencer_rw_mgr_inst_avl_address,                            --      avalon_anti_slave_0.address
			av_write               => sequencer_rw_mgr_inst_avl_write,                              --                         .write
			av_read                => sequencer_rw_mgr_inst_avl_read,                               --                         .read
			av_readdata            => sequencer_rw_mgr_inst_avl_readdata,                           --                         .readdata
			av_writedata           => sequencer_rw_mgr_inst_avl_writedata,                          --                         .writedata
			av_waitrequest         => sequencer_rw_mgr_inst_avl_waitrequest,                        --                         .waitrequest
			av_begintransfer       => open,                                                         --              (terminated)
			av_beginbursttransfer  => open,                                                         --              (terminated)
			av_burstcount          => open,                                                         --              (terminated)
			av_byteenable          => open,                                                         --              (terminated)
			av_readdatavalid       => '0',                                                          --              (terminated)
			av_writebyteenable     => open,                                                         --              (terminated)
			av_lock                => open,                                                         --              (terminated)
			av_chipselect          => open,                                                         --              (terminated)
			av_clken               => open,                                                         --              (terminated)
			uav_clken              => '0',                                                          --              (terminated)
			av_debugaccess         => open,                                                         --              (terminated)
			av_outputenable        => open,                                                         --              (terminated)
			uav_response           => open,                                                         --              (terminated)
			av_response            => "00",                                                         --              (terminated)
			uav_writeresponsevalid => open,                                                         --              (terminated)
			av_writeresponsevalid  => '0'                                                           --              (terminated)
		);

	sequencer_pll_mgr_inst_avl_translator : component altera_merlin_slave_translator
		generic map (
			AV_ADDRESS_W                   => 13,
			AV_DATA_W                      => 32,
			UAV_DATA_W                     => 32,
			AV_BURSTCOUNT_W                => 1,
			AV_BYTEENABLE_W                => 4,
			UAV_BYTEENABLE_W               => 4,
			UAV_ADDRESS_W                  => 20,
			UAV_BURSTCOUNT_W               => 3,
			AV_READLATENCY                 => 0,
			USE_READDATAVALID              => 0,
			USE_WAITREQUEST                => 1,
			USE_UAV_CLKEN                  => 0,
			USE_READRESPONSE               => 0,
			USE_WRITERESPONSE              => 0,
			AV_SYMBOLS_PER_WORD            => 4,
			AV_ADDRESS_SYMBOLS             => 0,
			AV_BURSTCOUNT_SYMBOLS          => 0,
			AV_CONSTANT_BURST_BEHAVIOR     => 0,
			UAV_CONSTANT_BURST_BEHAVIOR    => 0,
			AV_REQUIRE_UNALIGNED_ADDRESSES => 0,
			CHIPSELECT_THROUGH_READLATENCY => 0,
			AV_READ_WAIT_CYCLES            => 1,
			AV_WRITE_WAIT_CYCLES           => 0,
			AV_SETUP_WAIT_CYCLES           => 0,
			AV_DATA_HOLD_CYCLES            => 0
		)
		port map (
			clk                    => avl_clk_out_clk_clk,                                          --                      clk.clk
			reset                  => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, --                    reset.reset
			uav_address            => sequencer_pll_mgr_inst_avl_agent_m0_address,                  -- avalon_universal_slave_0.address
			uav_burstcount         => sequencer_pll_mgr_inst_avl_agent_m0_burstcount,               --                         .burstcount
			uav_read               => sequencer_pll_mgr_inst_avl_agent_m0_read,                     --                         .read
			uav_write              => sequencer_pll_mgr_inst_avl_agent_m0_write,                    --                         .write
			uav_waitrequest        => sequencer_pll_mgr_inst_avl_agent_m0_waitrequest,              --                         .waitrequest
			uav_readdatavalid      => sequencer_pll_mgr_inst_avl_agent_m0_readdatavalid,            --                         .readdatavalid
			uav_byteenable         => sequencer_pll_mgr_inst_avl_agent_m0_byteenable,               --                         .byteenable
			uav_readdata           => sequencer_pll_mgr_inst_avl_agent_m0_readdata,                 --                         .readdata
			uav_writedata          => sequencer_pll_mgr_inst_avl_agent_m0_writedata,                --                         .writedata
			uav_lock               => sequencer_pll_mgr_inst_avl_agent_m0_lock,                     --                         .lock
			uav_debugaccess        => sequencer_pll_mgr_inst_avl_agent_m0_debugaccess,              --                         .debugaccess
			av_address             => sequencer_pll_mgr_inst_avl_address,                           --      avalon_anti_slave_0.address
			av_write               => sequencer_pll_mgr_inst_avl_write,                             --                         .write
			av_read                => sequencer_pll_mgr_inst_avl_read,                              --                         .read
			av_readdata            => sequencer_pll_mgr_inst_avl_readdata,                          --                         .readdata
			av_writedata           => sequencer_pll_mgr_inst_avl_writedata,                         --                         .writedata
			av_waitrequest         => sequencer_pll_mgr_inst_avl_waitrequest,                       --                         .waitrequest
			av_begintransfer       => open,                                                         --              (terminated)
			av_beginbursttransfer  => open,                                                         --              (terminated)
			av_burstcount          => open,                                                         --              (terminated)
			av_byteenable          => open,                                                         --              (terminated)
			av_readdatavalid       => '0',                                                          --              (terminated)
			av_writebyteenable     => open,                                                         --              (terminated)
			av_lock                => open,                                                         --              (terminated)
			av_chipselect          => open,                                                         --              (terminated)
			av_clken               => open,                                                         --              (terminated)
			uav_clken              => '0',                                                          --              (terminated)
			av_debugaccess         => open,                                                         --              (terminated)
			av_outputenable        => open,                                                         --              (terminated)
			uav_response           => open,                                                         --              (terminated)
			av_response            => "00",                                                         --              (terminated)
			uav_writeresponsevalid => open,                                                         --              (terminated)
			av_writeresponsevalid  => '0'                                                           --              (terminated)
		);

	cpu_inst_data_master_agent : component altera_merlin_master_agent
		generic map (
			PKT_ORI_BURST_SIZE_H      => 91,
			PKT_ORI_BURST_SIZE_L      => 89,
			PKT_RESPONSE_STATUS_H     => 88,
			PKT_RESPONSE_STATUS_L     => 87,
			PKT_QOS_H                 => 74,
			PKT_QOS_L                 => 74,
			PKT_DATA_SIDEBAND_H       => 72,
			PKT_DATA_SIDEBAND_L       => 72,
			PKT_ADDR_SIDEBAND_H       => 71,
			PKT_ADDR_SIDEBAND_L       => 71,
			PKT_BURST_TYPE_H          => 70,
			PKT_BURST_TYPE_L          => 69,
			PKT_CACHE_H               => 86,
			PKT_CACHE_L               => 83,
			PKT_THREAD_ID_H           => 79,
			PKT_THREAD_ID_L           => 79,
			PKT_BURST_SIZE_H          => 68,
			PKT_BURST_SIZE_L          => 66,
			PKT_TRANS_EXCLUSIVE       => 61,
			PKT_TRANS_LOCK            => 60,
			PKT_BEGIN_BURST           => 73,
			PKT_PROTECTION_H          => 82,
			PKT_PROTECTION_L          => 80,
			PKT_BURSTWRAP_H           => 65,
			PKT_BURSTWRAP_L           => 65,
			PKT_BYTE_CNT_H            => 64,
			PKT_BYTE_CNT_L            => 62,
			PKT_ADDR_H                => 55,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 56,
			PKT_TRANS_POSTED          => 57,
			PKT_TRANS_WRITE           => 58,
			PKT_TRANS_READ            => 59,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 76,
			PKT_SRC_ID_L              => 75,
			PKT_DEST_ID_H             => 78,
			PKT_DEST_ID_L             => 77,
			ST_DATA_W                 => 92,
			ST_CHANNEL_W              => 3,
			AV_BURSTCOUNT_W           => 3,
			SUPPRESS_0_BYTEEN_RSP     => 0,
			ID                        => 0,
			BURSTWRAP_VALUE           => 1,
			CACHE_VALUE               => 0,
			SECURE_ACCESS_BIT         => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0
		)
		port map (
			clk                   => avl_clk_out_clk_clk,                                                     --       clk.clk
			reset                 => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset,            -- clk_reset.reset
			av_address            => cpu_inst_data_master_translator_avalon_universal_master_0_address,       --        av.address
			av_write              => cpu_inst_data_master_translator_avalon_universal_master_0_write,         --          .write
			av_read               => cpu_inst_data_master_translator_avalon_universal_master_0_read,          --          .read
			av_writedata          => cpu_inst_data_master_translator_avalon_universal_master_0_writedata,     --          .writedata
			av_readdata           => cpu_inst_data_master_translator_avalon_universal_master_0_readdata,      --          .readdata
			av_waitrequest        => cpu_inst_data_master_translator_avalon_universal_master_0_waitrequest,   --          .waitrequest
			av_readdatavalid      => cpu_inst_data_master_translator_avalon_universal_master_0_readdatavalid, --          .readdatavalid
			av_byteenable         => cpu_inst_data_master_translator_avalon_universal_master_0_byteenable,    --          .byteenable
			av_burstcount         => cpu_inst_data_master_translator_avalon_universal_master_0_burstcount,    --          .burstcount
			av_debugaccess        => cpu_inst_data_master_translator_avalon_universal_master_0_debugaccess,   --          .debugaccess
			av_lock               => cpu_inst_data_master_translator_avalon_universal_master_0_lock,          --          .lock
			cp_valid              => cpu_inst_data_master_agent_cp_valid,                                     --        cp.valid
			cp_data               => cpu_inst_data_master_agent_cp_data,                                      --          .data
			cp_startofpacket      => cpu_inst_data_master_agent_cp_startofpacket,                             --          .startofpacket
			cp_endofpacket        => cpu_inst_data_master_agent_cp_endofpacket,                               --          .endofpacket
			cp_ready              => cpu_inst_data_master_agent_cp_ready,                                     --          .ready
			rp_valid              => rsp_mux_src_valid,                                                       --        rp.valid
			rp_data               => rsp_mux_src_data,                                                        --          .data
			rp_channel            => rsp_mux_src_channel,                                                     --          .channel
			rp_startofpacket      => rsp_mux_src_startofpacket,                                               --          .startofpacket
			rp_endofpacket        => rsp_mux_src_endofpacket,                                                 --          .endofpacket
			rp_ready              => rsp_mux_src_ready,                                                       --          .ready
			av_response           => open,                                                                    -- (terminated)
			av_writeresponsevalid => open                                                                     -- (terminated)
		);

	sequencer_phy_mgr_inst_avl_agent : component altera_merlin_slave_agent
		generic map (
			PKT_ORI_BURST_SIZE_H      => 91,
			PKT_ORI_BURST_SIZE_L      => 89,
			PKT_RESPONSE_STATUS_H     => 88,
			PKT_RESPONSE_STATUS_L     => 87,
			PKT_BURST_SIZE_H          => 68,
			PKT_BURST_SIZE_L          => 66,
			PKT_TRANS_LOCK            => 60,
			PKT_BEGIN_BURST           => 73,
			PKT_PROTECTION_H          => 82,
			PKT_PROTECTION_L          => 80,
			PKT_BURSTWRAP_H           => 65,
			PKT_BURSTWRAP_L           => 65,
			PKT_BYTE_CNT_H            => 64,
			PKT_BYTE_CNT_L            => 62,
			PKT_ADDR_H                => 55,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 56,
			PKT_TRANS_POSTED          => 57,
			PKT_TRANS_WRITE           => 58,
			PKT_TRANS_READ            => 59,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 76,
			PKT_SRC_ID_L              => 75,
			PKT_DEST_ID_H             => 78,
			PKT_DEST_ID_L             => 77,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 3,
			ST_DATA_W                 => 92,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0
		)
		port map (
			clk                     => avl_clk_out_clk_clk,                                          --             clk.clk
			reset                   => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, --       clk_reset.reset
			m0_address              => sequencer_phy_mgr_inst_avl_agent_m0_address,                  --              m0.address
			m0_burstcount           => sequencer_phy_mgr_inst_avl_agent_m0_burstcount,               --                .burstcount
			m0_byteenable           => sequencer_phy_mgr_inst_avl_agent_m0_byteenable,               --                .byteenable
			m0_debugaccess          => sequencer_phy_mgr_inst_avl_agent_m0_debugaccess,              --                .debugaccess
			m0_lock                 => sequencer_phy_mgr_inst_avl_agent_m0_lock,                     --                .lock
			m0_readdata             => sequencer_phy_mgr_inst_avl_agent_m0_readdata,                 --                .readdata
			m0_readdatavalid        => sequencer_phy_mgr_inst_avl_agent_m0_readdatavalid,            --                .readdatavalid
			m0_read                 => sequencer_phy_mgr_inst_avl_agent_m0_read,                     --                .read
			m0_waitrequest          => sequencer_phy_mgr_inst_avl_agent_m0_waitrequest,              --                .waitrequest
			m0_writedata            => sequencer_phy_mgr_inst_avl_agent_m0_writedata,                --                .writedata
			m0_write                => sequencer_phy_mgr_inst_avl_agent_m0_write,                    --                .write
			rp_endofpacket          => sequencer_phy_mgr_inst_avl_agent_rp_endofpacket,              --              rp.endofpacket
			rp_ready                => sequencer_phy_mgr_inst_avl_agent_rp_ready,                    --                .ready
			rp_valid                => sequencer_phy_mgr_inst_avl_agent_rp_valid,                    --                .valid
			rp_data                 => sequencer_phy_mgr_inst_avl_agent_rp_data,                     --                .data
			rp_startofpacket        => sequencer_phy_mgr_inst_avl_agent_rp_startofpacket,            --                .startofpacket
			cp_ready                => cmd_mux_src_ready,                                            --              cp.ready
			cp_valid                => cmd_mux_src_valid,                                            --                .valid
			cp_data                 => cmd_mux_src_data,                                             --                .data
			cp_startofpacket        => cmd_mux_src_startofpacket,                                    --                .startofpacket
			cp_endofpacket          => cmd_mux_src_endofpacket,                                      --                .endofpacket
			cp_channel              => cmd_mux_src_channel,                                          --                .channel
			rf_sink_ready           => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready,          --         rf_sink.ready
			rf_sink_valid           => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid,          --                .valid
			rf_sink_startofpacket   => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket,  --                .startofpacket
			rf_sink_endofpacket     => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket,    --                .endofpacket
			rf_sink_data            => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data,           --                .data
			rf_source_ready         => sequencer_phy_mgr_inst_avl_agent_rf_source_ready,             --       rf_source.ready
			rf_source_valid         => sequencer_phy_mgr_inst_avl_agent_rf_source_valid,             --                .valid
			rf_source_startofpacket => sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket,     --                .startofpacket
			rf_source_endofpacket   => sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket,       --                .endofpacket
			rf_source_data          => sequencer_phy_mgr_inst_avl_agent_rf_source_data,              --                .data
			rdata_fifo_sink_ready   => avalon_st_adapter_out_0_ready,                                -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => avalon_st_adapter_out_0_valid,                                --                .valid
			rdata_fifo_sink_data    => avalon_st_adapter_out_0_data,                                 --                .data
			rdata_fifo_sink_error   => avalon_st_adapter_out_0_error(0),                             --                .error
			rdata_fifo_src_ready    => sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready,        --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid,        --                .valid
			rdata_fifo_src_data     => sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data,         --                .data
			m0_response             => "00",                                                         --     (terminated)
			m0_writeresponsevalid   => '0'                                                           --     (terminated)
		);

	sequencer_phy_mgr_inst_avl_agent_rsp_fifo : component altera_avalon_sc_fifo
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 93,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0
		)
		port map (
			clk               => avl_clk_out_clk_clk,                                          --       clk.clk
			reset             => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			in_data           => sequencer_phy_mgr_inst_avl_agent_rf_source_data,              --        in.data
			in_valid          => sequencer_phy_mgr_inst_avl_agent_rf_source_valid,             --          .valid
			in_ready          => sequencer_phy_mgr_inst_avl_agent_rf_source_ready,             --          .ready
			in_startofpacket  => sequencer_phy_mgr_inst_avl_agent_rf_source_startofpacket,     --          .startofpacket
			in_endofpacket    => sequencer_phy_mgr_inst_avl_agent_rf_source_endofpacket,       --          .endofpacket
			out_data          => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_data,           --       out.data
			out_valid         => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_valid,          --          .valid
			out_ready         => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_ready,          --          .ready
			out_startofpacket => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_startofpacket,  --          .startofpacket
			out_endofpacket   => sequencer_phy_mgr_inst_avl_agent_rsp_fifo_out_endofpacket,    --          .endofpacket
			csr_address       => "00",                                                         -- (terminated)
			csr_read          => '0',                                                          -- (terminated)
			csr_write         => '0',                                                          -- (terminated)
			csr_readdata      => open,                                                         -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                           -- (terminated)
			almost_full_data  => open,                                                         -- (terminated)
			almost_empty_data => open,                                                         -- (terminated)
			in_empty          => "0",                                                          -- (terminated)
			out_empty         => open,                                                         -- (terminated)
			in_error          => "0",                                                          -- (terminated)
			out_error         => open,                                                         -- (terminated)
			in_channel        => "0",                                                          -- (terminated)
			out_channel       => open                                                          -- (terminated)
		);

	sequencer_rw_mgr_inst_avl_agent : component altera_merlin_slave_agent
		generic map (
			PKT_ORI_BURST_SIZE_H      => 91,
			PKT_ORI_BURST_SIZE_L      => 89,
			PKT_RESPONSE_STATUS_H     => 88,
			PKT_RESPONSE_STATUS_L     => 87,
			PKT_BURST_SIZE_H          => 68,
			PKT_BURST_SIZE_L          => 66,
			PKT_TRANS_LOCK            => 60,
			PKT_BEGIN_BURST           => 73,
			PKT_PROTECTION_H          => 82,
			PKT_PROTECTION_L          => 80,
			PKT_BURSTWRAP_H           => 65,
			PKT_BURSTWRAP_L           => 65,
			PKT_BYTE_CNT_H            => 64,
			PKT_BYTE_CNT_L            => 62,
			PKT_ADDR_H                => 55,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 56,
			PKT_TRANS_POSTED          => 57,
			PKT_TRANS_WRITE           => 58,
			PKT_TRANS_READ            => 59,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 76,
			PKT_SRC_ID_L              => 75,
			PKT_DEST_ID_H             => 78,
			PKT_DEST_ID_L             => 77,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 3,
			ST_DATA_W                 => 92,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0
		)
		port map (
			clk                     => avl_clk_out_clk_clk,                                          --             clk.clk
			reset                   => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, --       clk_reset.reset
			m0_address              => sequencer_rw_mgr_inst_avl_agent_m0_address,                   --              m0.address
			m0_burstcount           => sequencer_rw_mgr_inst_avl_agent_m0_burstcount,                --                .burstcount
			m0_byteenable           => sequencer_rw_mgr_inst_avl_agent_m0_byteenable,                --                .byteenable
			m0_debugaccess          => sequencer_rw_mgr_inst_avl_agent_m0_debugaccess,               --                .debugaccess
			m0_lock                 => sequencer_rw_mgr_inst_avl_agent_m0_lock,                      --                .lock
			m0_readdata             => sequencer_rw_mgr_inst_avl_agent_m0_readdata,                  --                .readdata
			m0_readdatavalid        => sequencer_rw_mgr_inst_avl_agent_m0_readdatavalid,             --                .readdatavalid
			m0_read                 => sequencer_rw_mgr_inst_avl_agent_m0_read,                      --                .read
			m0_waitrequest          => sequencer_rw_mgr_inst_avl_agent_m0_waitrequest,               --                .waitrequest
			m0_writedata            => sequencer_rw_mgr_inst_avl_agent_m0_writedata,                 --                .writedata
			m0_write                => sequencer_rw_mgr_inst_avl_agent_m0_write,                     --                .write
			rp_endofpacket          => sequencer_rw_mgr_inst_avl_agent_rp_endofpacket,               --              rp.endofpacket
			rp_ready                => sequencer_rw_mgr_inst_avl_agent_rp_ready,                     --                .ready
			rp_valid                => sequencer_rw_mgr_inst_avl_agent_rp_valid,                     --                .valid
			rp_data                 => sequencer_rw_mgr_inst_avl_agent_rp_data,                      --                .data
			rp_startofpacket        => sequencer_rw_mgr_inst_avl_agent_rp_startofpacket,             --                .startofpacket
			cp_ready                => cmd_mux_001_src_ready,                                        --              cp.ready
			cp_valid                => cmd_mux_001_src_valid,                                        --                .valid
			cp_data                 => cmd_mux_001_src_data,                                         --                .data
			cp_startofpacket        => cmd_mux_001_src_startofpacket,                                --                .startofpacket
			cp_endofpacket          => cmd_mux_001_src_endofpacket,                                  --                .endofpacket
			cp_channel              => cmd_mux_001_src_channel,                                      --                .channel
			rf_sink_ready           => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready,           --         rf_sink.ready
			rf_sink_valid           => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid,           --                .valid
			rf_sink_startofpacket   => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket,   --                .startofpacket
			rf_sink_endofpacket     => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket,     --                .endofpacket
			rf_sink_data            => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data,            --                .data
			rf_source_ready         => sequencer_rw_mgr_inst_avl_agent_rf_source_ready,              --       rf_source.ready
			rf_source_valid         => sequencer_rw_mgr_inst_avl_agent_rf_source_valid,              --                .valid
			rf_source_startofpacket => sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket,      --                .startofpacket
			rf_source_endofpacket   => sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket,        --                .endofpacket
			rf_source_data          => sequencer_rw_mgr_inst_avl_agent_rf_source_data,               --                .data
			rdata_fifo_sink_ready   => avalon_st_adapter_001_out_0_ready,                            -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => avalon_st_adapter_001_out_0_valid,                            --                .valid
			rdata_fifo_sink_data    => avalon_st_adapter_001_out_0_data,                             --                .data
			rdata_fifo_sink_error   => avalon_st_adapter_001_out_0_error(0),                         --                .error
			rdata_fifo_src_ready    => sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready,         --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid,         --                .valid
			rdata_fifo_src_data     => sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data,          --                .data
			m0_response             => "00",                                                         --     (terminated)
			m0_writeresponsevalid   => '0'                                                           --     (terminated)
		);

	sequencer_rw_mgr_inst_avl_agent_rsp_fifo : component altera_avalon_sc_fifo
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 93,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0
		)
		port map (
			clk               => avl_clk_out_clk_clk,                                          --       clk.clk
			reset             => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			in_data           => sequencer_rw_mgr_inst_avl_agent_rf_source_data,               --        in.data
			in_valid          => sequencer_rw_mgr_inst_avl_agent_rf_source_valid,              --          .valid
			in_ready          => sequencer_rw_mgr_inst_avl_agent_rf_source_ready,              --          .ready
			in_startofpacket  => sequencer_rw_mgr_inst_avl_agent_rf_source_startofpacket,      --          .startofpacket
			in_endofpacket    => sequencer_rw_mgr_inst_avl_agent_rf_source_endofpacket,        --          .endofpacket
			out_data          => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_data,            --       out.data
			out_valid         => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_valid,           --          .valid
			out_ready         => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_ready,           --          .ready
			out_startofpacket => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_startofpacket,   --          .startofpacket
			out_endofpacket   => sequencer_rw_mgr_inst_avl_agent_rsp_fifo_out_endofpacket,     --          .endofpacket
			csr_address       => "00",                                                         -- (terminated)
			csr_read          => '0',                                                          -- (terminated)
			csr_write         => '0',                                                          -- (terminated)
			csr_readdata      => open,                                                         -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                           -- (terminated)
			almost_full_data  => open,                                                         -- (terminated)
			almost_empty_data => open,                                                         -- (terminated)
			in_empty          => "0",                                                          -- (terminated)
			out_empty         => open,                                                         -- (terminated)
			in_error          => "0",                                                          -- (terminated)
			out_error         => open,                                                         -- (terminated)
			in_channel        => "0",                                                          -- (terminated)
			out_channel       => open                                                          -- (terminated)
		);

	sequencer_pll_mgr_inst_avl_agent : component altera_merlin_slave_agent
		generic map (
			PKT_ORI_BURST_SIZE_H      => 91,
			PKT_ORI_BURST_SIZE_L      => 89,
			PKT_RESPONSE_STATUS_H     => 88,
			PKT_RESPONSE_STATUS_L     => 87,
			PKT_BURST_SIZE_H          => 68,
			PKT_BURST_SIZE_L          => 66,
			PKT_TRANS_LOCK            => 60,
			PKT_BEGIN_BURST           => 73,
			PKT_PROTECTION_H          => 82,
			PKT_PROTECTION_L          => 80,
			PKT_BURSTWRAP_H           => 65,
			PKT_BURSTWRAP_L           => 65,
			PKT_BYTE_CNT_H            => 64,
			PKT_BYTE_CNT_L            => 62,
			PKT_ADDR_H                => 55,
			PKT_ADDR_L                => 36,
			PKT_TRANS_COMPRESSED_READ => 56,
			PKT_TRANS_POSTED          => 57,
			PKT_TRANS_WRITE           => 58,
			PKT_TRANS_READ            => 59,
			PKT_DATA_H                => 31,
			PKT_DATA_L                => 0,
			PKT_BYTEEN_H              => 35,
			PKT_BYTEEN_L              => 32,
			PKT_SRC_ID_H              => 76,
			PKT_SRC_ID_L              => 75,
			PKT_DEST_ID_H             => 78,
			PKT_DEST_ID_L             => 77,
			PKT_SYMBOL_W              => 8,
			ST_CHANNEL_W              => 3,
			ST_DATA_W                 => 92,
			AVS_BURSTCOUNT_W          => 3,
			SUPPRESS_0_BYTEEN_CMD     => 0,
			PREVENT_FIFO_OVERFLOW     => 1,
			USE_READRESPONSE          => 0,
			USE_WRITERESPONSE         => 0,
			ECC_ENABLE                => 0
		)
		port map (
			clk                     => avl_clk_out_clk_clk,                                          --             clk.clk
			reset                   => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, --       clk_reset.reset
			m0_address              => sequencer_pll_mgr_inst_avl_agent_m0_address,                  --              m0.address
			m0_burstcount           => sequencer_pll_mgr_inst_avl_agent_m0_burstcount,               --                .burstcount
			m0_byteenable           => sequencer_pll_mgr_inst_avl_agent_m0_byteenable,               --                .byteenable
			m0_debugaccess          => sequencer_pll_mgr_inst_avl_agent_m0_debugaccess,              --                .debugaccess
			m0_lock                 => sequencer_pll_mgr_inst_avl_agent_m0_lock,                     --                .lock
			m0_readdata             => sequencer_pll_mgr_inst_avl_agent_m0_readdata,                 --                .readdata
			m0_readdatavalid        => sequencer_pll_mgr_inst_avl_agent_m0_readdatavalid,            --                .readdatavalid
			m0_read                 => sequencer_pll_mgr_inst_avl_agent_m0_read,                     --                .read
			m0_waitrequest          => sequencer_pll_mgr_inst_avl_agent_m0_waitrequest,              --                .waitrequest
			m0_writedata            => sequencer_pll_mgr_inst_avl_agent_m0_writedata,                --                .writedata
			m0_write                => sequencer_pll_mgr_inst_avl_agent_m0_write,                    --                .write
			rp_endofpacket          => sequencer_pll_mgr_inst_avl_agent_rp_endofpacket,              --              rp.endofpacket
			rp_ready                => sequencer_pll_mgr_inst_avl_agent_rp_ready,                    --                .ready
			rp_valid                => sequencer_pll_mgr_inst_avl_agent_rp_valid,                    --                .valid
			rp_data                 => sequencer_pll_mgr_inst_avl_agent_rp_data,                     --                .data
			rp_startofpacket        => sequencer_pll_mgr_inst_avl_agent_rp_startofpacket,            --                .startofpacket
			cp_ready                => cmd_mux_002_src_ready,                                        --              cp.ready
			cp_valid                => cmd_mux_002_src_valid,                                        --                .valid
			cp_data                 => cmd_mux_002_src_data,                                         --                .data
			cp_startofpacket        => cmd_mux_002_src_startofpacket,                                --                .startofpacket
			cp_endofpacket          => cmd_mux_002_src_endofpacket,                                  --                .endofpacket
			cp_channel              => cmd_mux_002_src_channel,                                      --                .channel
			rf_sink_ready           => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_ready,          --         rf_sink.ready
			rf_sink_valid           => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_valid,          --                .valid
			rf_sink_startofpacket   => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_startofpacket,  --                .startofpacket
			rf_sink_endofpacket     => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_endofpacket,    --                .endofpacket
			rf_sink_data            => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_data,           --                .data
			rf_source_ready         => sequencer_pll_mgr_inst_avl_agent_rf_source_ready,             --       rf_source.ready
			rf_source_valid         => sequencer_pll_mgr_inst_avl_agent_rf_source_valid,             --                .valid
			rf_source_startofpacket => sequencer_pll_mgr_inst_avl_agent_rf_source_startofpacket,     --                .startofpacket
			rf_source_endofpacket   => sequencer_pll_mgr_inst_avl_agent_rf_source_endofpacket,       --                .endofpacket
			rf_source_data          => sequencer_pll_mgr_inst_avl_agent_rf_source_data,              --                .data
			rdata_fifo_sink_ready   => avalon_st_adapter_002_out_0_ready,                            -- rdata_fifo_sink.ready
			rdata_fifo_sink_valid   => avalon_st_adapter_002_out_0_valid,                            --                .valid
			rdata_fifo_sink_data    => avalon_st_adapter_002_out_0_data,                             --                .data
			rdata_fifo_sink_error   => avalon_st_adapter_002_out_0_error(0),                         --                .error
			rdata_fifo_src_ready    => sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_ready,        --  rdata_fifo_src.ready
			rdata_fifo_src_valid    => sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_valid,        --                .valid
			rdata_fifo_src_data     => sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_data,         --                .data
			m0_response             => "00",                                                         --     (terminated)
			m0_writeresponsevalid   => '0'                                                           --     (terminated)
		);

	sequencer_pll_mgr_inst_avl_agent_rsp_fifo : component altera_avalon_sc_fifo
		generic map (
			SYMBOLS_PER_BEAT    => 1,
			BITS_PER_SYMBOL     => 93,
			FIFO_DEPTH          => 2,
			CHANNEL_WIDTH       => 0,
			ERROR_WIDTH         => 0,
			USE_PACKETS         => 1,
			USE_FILL_LEVEL      => 0,
			EMPTY_LATENCY       => 1,
			USE_MEMORY_BLOCKS   => 0,
			USE_STORE_FORWARD   => 0,
			USE_ALMOST_FULL_IF  => 0,
			USE_ALMOST_EMPTY_IF => 0
		)
		port map (
			clk               => avl_clk_out_clk_clk,                                          --       clk.clk
			reset             => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			in_data           => sequencer_pll_mgr_inst_avl_agent_rf_source_data,              --        in.data
			in_valid          => sequencer_pll_mgr_inst_avl_agent_rf_source_valid,             --          .valid
			in_ready          => sequencer_pll_mgr_inst_avl_agent_rf_source_ready,             --          .ready
			in_startofpacket  => sequencer_pll_mgr_inst_avl_agent_rf_source_startofpacket,     --          .startofpacket
			in_endofpacket    => sequencer_pll_mgr_inst_avl_agent_rf_source_endofpacket,       --          .endofpacket
			out_data          => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_data,           --       out.data
			out_valid         => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_valid,          --          .valid
			out_ready         => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_ready,          --          .ready
			out_startofpacket => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_startofpacket,  --          .startofpacket
			out_endofpacket   => sequencer_pll_mgr_inst_avl_agent_rsp_fifo_out_endofpacket,    --          .endofpacket
			csr_address       => "00",                                                         -- (terminated)
			csr_read          => '0',                                                          -- (terminated)
			csr_write         => '0',                                                          -- (terminated)
			csr_readdata      => open,                                                         -- (terminated)
			csr_writedata     => "00000000000000000000000000000000",                           -- (terminated)
			almost_full_data  => open,                                                         -- (terminated)
			almost_empty_data => open,                                                         -- (terminated)
			in_empty          => "0",                                                          -- (terminated)
			out_empty         => open,                                                         -- (terminated)
			in_error          => "0",                                                          -- (terminated)
			out_error         => open,                                                         -- (terminated)
			in_channel        => "0",                                                          -- (terminated)
			out_channel       => open                                                          -- (terminated)
		);

	router : component ddr3controller_s0_mm_interconnect_0_router
		port map (
			sink_ready         => cpu_inst_data_master_agent_cp_ready,                          --      sink.ready
			sink_valid         => cpu_inst_data_master_agent_cp_valid,                          --          .valid
			sink_data          => cpu_inst_data_master_agent_cp_data,                           --          .data
			sink_startofpacket => cpu_inst_data_master_agent_cp_startofpacket,                  --          .startofpacket
			sink_endofpacket   => cpu_inst_data_master_agent_cp_endofpacket,                    --          .endofpacket
			clk                => avl_clk_out_clk_clk,                                          --       clk.clk
			reset              => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready          => router_src_ready,                                             --       src.ready
			src_valid          => router_src_valid,                                             --          .valid
			src_data           => router_src_data,                                              --          .data
			src_channel        => router_src_channel,                                           --          .channel
			src_startofpacket  => router_src_startofpacket,                                     --          .startofpacket
			src_endofpacket    => router_src_endofpacket                                        --          .endofpacket
		);

	router_001 : component ddr3controller_s0_mm_interconnect_0_router_001
		port map (
			sink_ready         => sequencer_phy_mgr_inst_avl_agent_rp_ready,                    --      sink.ready
			sink_valid         => sequencer_phy_mgr_inst_avl_agent_rp_valid,                    --          .valid
			sink_data          => sequencer_phy_mgr_inst_avl_agent_rp_data,                     --          .data
			sink_startofpacket => sequencer_phy_mgr_inst_avl_agent_rp_startofpacket,            --          .startofpacket
			sink_endofpacket   => sequencer_phy_mgr_inst_avl_agent_rp_endofpacket,              --          .endofpacket
			clk                => avl_clk_out_clk_clk,                                          --       clk.clk
			reset              => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready          => router_001_src_ready,                                         --       src.ready
			src_valid          => router_001_src_valid,                                         --          .valid
			src_data           => router_001_src_data,                                          --          .data
			src_channel        => router_001_src_channel,                                       --          .channel
			src_startofpacket  => router_001_src_startofpacket,                                 --          .startofpacket
			src_endofpacket    => router_001_src_endofpacket                                    --          .endofpacket
		);

	router_002 : component ddr3controller_s0_mm_interconnect_0_router_001
		port map (
			sink_ready         => sequencer_rw_mgr_inst_avl_agent_rp_ready,                     --      sink.ready
			sink_valid         => sequencer_rw_mgr_inst_avl_agent_rp_valid,                     --          .valid
			sink_data          => sequencer_rw_mgr_inst_avl_agent_rp_data,                      --          .data
			sink_startofpacket => sequencer_rw_mgr_inst_avl_agent_rp_startofpacket,             --          .startofpacket
			sink_endofpacket   => sequencer_rw_mgr_inst_avl_agent_rp_endofpacket,               --          .endofpacket
			clk                => avl_clk_out_clk_clk,                                          --       clk.clk
			reset              => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready          => router_002_src_ready,                                         --       src.ready
			src_valid          => router_002_src_valid,                                         --          .valid
			src_data           => router_002_src_data,                                          --          .data
			src_channel        => router_002_src_channel,                                       --          .channel
			src_startofpacket  => router_002_src_startofpacket,                                 --          .startofpacket
			src_endofpacket    => router_002_src_endofpacket                                    --          .endofpacket
		);

	router_003 : component ddr3controller_s0_mm_interconnect_0_router_001
		port map (
			sink_ready         => sequencer_pll_mgr_inst_avl_agent_rp_ready,                    --      sink.ready
			sink_valid         => sequencer_pll_mgr_inst_avl_agent_rp_valid,                    --          .valid
			sink_data          => sequencer_pll_mgr_inst_avl_agent_rp_data,                     --          .data
			sink_startofpacket => sequencer_pll_mgr_inst_avl_agent_rp_startofpacket,            --          .startofpacket
			sink_endofpacket   => sequencer_pll_mgr_inst_avl_agent_rp_endofpacket,              --          .endofpacket
			clk                => avl_clk_out_clk_clk,                                          --       clk.clk
			reset              => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready          => router_003_src_ready,                                         --       src.ready
			src_valid          => router_003_src_valid,                                         --          .valid
			src_data           => router_003_src_data,                                          --          .data
			src_channel        => router_003_src_channel,                                       --          .channel
			src_startofpacket  => router_003_src_startofpacket,                                 --          .startofpacket
			src_endofpacket    => router_003_src_endofpacket                                    --          .endofpacket
		);

	cmd_demux : component ddr3controller_s0_mm_interconnect_0_cmd_demux
		port map (
			clk                => avl_clk_out_clk_clk,                                          --       clk.clk
			reset              => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_src_ready,                                             --      sink.ready
			sink_channel       => router_src_channel,                                           --          .channel
			sink_data          => router_src_data,                                              --          .data
			sink_startofpacket => router_src_startofpacket,                                     --          .startofpacket
			sink_endofpacket   => router_src_endofpacket,                                       --          .endofpacket
			sink_valid(0)      => router_src_valid,                                             --          .valid
			src0_ready         => cmd_demux_src0_ready,                                         --      src0.ready
			src0_valid         => cmd_demux_src0_valid,                                         --          .valid
			src0_data          => cmd_demux_src0_data,                                          --          .data
			src0_channel       => cmd_demux_src0_channel,                                       --          .channel
			src0_startofpacket => cmd_demux_src0_startofpacket,                                 --          .startofpacket
			src0_endofpacket   => cmd_demux_src0_endofpacket,                                   --          .endofpacket
			src1_ready         => cmd_demux_src1_ready,                                         --      src1.ready
			src1_valid         => cmd_demux_src1_valid,                                         --          .valid
			src1_data          => cmd_demux_src1_data,                                          --          .data
			src1_channel       => cmd_demux_src1_channel,                                       --          .channel
			src1_startofpacket => cmd_demux_src1_startofpacket,                                 --          .startofpacket
			src1_endofpacket   => cmd_demux_src1_endofpacket,                                   --          .endofpacket
			src2_ready         => cmd_demux_src2_ready,                                         --      src2.ready
			src2_valid         => cmd_demux_src2_valid,                                         --          .valid
			src2_data          => cmd_demux_src2_data,                                          --          .data
			src2_channel       => cmd_demux_src2_channel,                                       --          .channel
			src2_startofpacket => cmd_demux_src2_startofpacket,                                 --          .startofpacket
			src2_endofpacket   => cmd_demux_src2_endofpacket                                    --          .endofpacket
		);

	cmd_mux : component ddr3controller_s0_mm_interconnect_0_cmd_mux
		port map (
			clk                 => avl_clk_out_clk_clk,                                          --       clk.clk
			reset               => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_src_ready,                                            --       src.ready
			src_valid           => cmd_mux_src_valid,                                            --          .valid
			src_data            => cmd_mux_src_data,                                             --          .data
			src_channel         => cmd_mux_src_channel,                                          --          .channel
			src_startofpacket   => cmd_mux_src_startofpacket,                                    --          .startofpacket
			src_endofpacket     => cmd_mux_src_endofpacket,                                      --          .endofpacket
			sink0_ready         => cmd_demux_src0_ready,                                         --     sink0.ready
			sink0_valid         => cmd_demux_src0_valid,                                         --          .valid
			sink0_channel       => cmd_demux_src0_channel,                                       --          .channel
			sink0_data          => cmd_demux_src0_data,                                          --          .data
			sink0_startofpacket => cmd_demux_src0_startofpacket,                                 --          .startofpacket
			sink0_endofpacket   => cmd_demux_src0_endofpacket                                    --          .endofpacket
		);

	cmd_mux_001 : component ddr3controller_s0_mm_interconnect_0_cmd_mux
		port map (
			clk                 => avl_clk_out_clk_clk,                                          --       clk.clk
			reset               => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_001_src_ready,                                        --       src.ready
			src_valid           => cmd_mux_001_src_valid,                                        --          .valid
			src_data            => cmd_mux_001_src_data,                                         --          .data
			src_channel         => cmd_mux_001_src_channel,                                      --          .channel
			src_startofpacket   => cmd_mux_001_src_startofpacket,                                --          .startofpacket
			src_endofpacket     => cmd_mux_001_src_endofpacket,                                  --          .endofpacket
			sink0_ready         => cmd_demux_src1_ready,                                         --     sink0.ready
			sink0_valid         => cmd_demux_src1_valid,                                         --          .valid
			sink0_channel       => cmd_demux_src1_channel,                                       --          .channel
			sink0_data          => cmd_demux_src1_data,                                          --          .data
			sink0_startofpacket => cmd_demux_src1_startofpacket,                                 --          .startofpacket
			sink0_endofpacket   => cmd_demux_src1_endofpacket                                    --          .endofpacket
		);

	cmd_mux_002 : component ddr3controller_s0_mm_interconnect_0_cmd_mux
		port map (
			clk                 => avl_clk_out_clk_clk,                                          --       clk.clk
			reset               => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => cmd_mux_002_src_ready,                                        --       src.ready
			src_valid           => cmd_mux_002_src_valid,                                        --          .valid
			src_data            => cmd_mux_002_src_data,                                         --          .data
			src_channel         => cmd_mux_002_src_channel,                                      --          .channel
			src_startofpacket   => cmd_mux_002_src_startofpacket,                                --          .startofpacket
			src_endofpacket     => cmd_mux_002_src_endofpacket,                                  --          .endofpacket
			sink0_ready         => cmd_demux_src2_ready,                                         --     sink0.ready
			sink0_valid         => cmd_demux_src2_valid,                                         --          .valid
			sink0_channel       => cmd_demux_src2_channel,                                       --          .channel
			sink0_data          => cmd_demux_src2_data,                                          --          .data
			sink0_startofpacket => cmd_demux_src2_startofpacket,                                 --          .startofpacket
			sink0_endofpacket   => cmd_demux_src2_endofpacket                                    --          .endofpacket
		);

	rsp_demux : component ddr3controller_s0_mm_interconnect_0_rsp_demux
		port map (
			clk                => avl_clk_out_clk_clk,                                          --       clk.clk
			reset              => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_001_src_ready,                                         --      sink.ready
			sink_channel       => router_001_src_channel,                                       --          .channel
			sink_data          => router_001_src_data,                                          --          .data
			sink_startofpacket => router_001_src_startofpacket,                                 --          .startofpacket
			sink_endofpacket   => router_001_src_endofpacket,                                   --          .endofpacket
			sink_valid(0)      => router_001_src_valid,                                         --          .valid
			src0_ready         => rsp_demux_src0_ready,                                         --      src0.ready
			src0_valid         => rsp_demux_src0_valid,                                         --          .valid
			src0_data          => rsp_demux_src0_data,                                          --          .data
			src0_channel       => rsp_demux_src0_channel,                                       --          .channel
			src0_startofpacket => rsp_demux_src0_startofpacket,                                 --          .startofpacket
			src0_endofpacket   => rsp_demux_src0_endofpacket                                    --          .endofpacket
		);

	rsp_demux_001 : component ddr3controller_s0_mm_interconnect_0_rsp_demux
		port map (
			clk                => avl_clk_out_clk_clk,                                          --       clk.clk
			reset              => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_002_src_ready,                                         --      sink.ready
			sink_channel       => router_002_src_channel,                                       --          .channel
			sink_data          => router_002_src_data,                                          --          .data
			sink_startofpacket => router_002_src_startofpacket,                                 --          .startofpacket
			sink_endofpacket   => router_002_src_endofpacket,                                   --          .endofpacket
			sink_valid(0)      => router_002_src_valid,                                         --          .valid
			src0_ready         => rsp_demux_001_src0_ready,                                     --      src0.ready
			src0_valid         => rsp_demux_001_src0_valid,                                     --          .valid
			src0_data          => rsp_demux_001_src0_data,                                      --          .data
			src0_channel       => rsp_demux_001_src0_channel,                                   --          .channel
			src0_startofpacket => rsp_demux_001_src0_startofpacket,                             --          .startofpacket
			src0_endofpacket   => rsp_demux_001_src0_endofpacket                                --          .endofpacket
		);

	rsp_demux_002 : component ddr3controller_s0_mm_interconnect_0_rsp_demux
		port map (
			clk                => avl_clk_out_clk_clk,                                          --       clk.clk
			reset              => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			sink_ready         => router_003_src_ready,                                         --      sink.ready
			sink_channel       => router_003_src_channel,                                       --          .channel
			sink_data          => router_003_src_data,                                          --          .data
			sink_startofpacket => router_003_src_startofpacket,                                 --          .startofpacket
			sink_endofpacket   => router_003_src_endofpacket,                                   --          .endofpacket
			sink_valid(0)      => router_003_src_valid,                                         --          .valid
			src0_ready         => rsp_demux_002_src0_ready,                                     --      src0.ready
			src0_valid         => rsp_demux_002_src0_valid,                                     --          .valid
			src0_data          => rsp_demux_002_src0_data,                                      --          .data
			src0_channel       => rsp_demux_002_src0_channel,                                   --          .channel
			src0_startofpacket => rsp_demux_002_src0_startofpacket,                             --          .startofpacket
			src0_endofpacket   => rsp_demux_002_src0_endofpacket                                --          .endofpacket
		);

	rsp_mux : component ddr3controller_s0_mm_interconnect_0_rsp_mux
		port map (
			clk                 => avl_clk_out_clk_clk,                                          --       clk.clk
			reset               => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- clk_reset.reset
			src_ready           => rsp_mux_src_ready,                                            --       src.ready
			src_valid           => rsp_mux_src_valid,                                            --          .valid
			src_data            => rsp_mux_src_data,                                             --          .data
			src_channel         => rsp_mux_src_channel,                                          --          .channel
			src_startofpacket   => rsp_mux_src_startofpacket,                                    --          .startofpacket
			src_endofpacket     => rsp_mux_src_endofpacket,                                      --          .endofpacket
			sink0_ready         => rsp_demux_src0_ready,                                         --     sink0.ready
			sink0_valid         => rsp_demux_src0_valid,                                         --          .valid
			sink0_channel       => rsp_demux_src0_channel,                                       --          .channel
			sink0_data          => rsp_demux_src0_data,                                          --          .data
			sink0_startofpacket => rsp_demux_src0_startofpacket,                                 --          .startofpacket
			sink0_endofpacket   => rsp_demux_src0_endofpacket,                                   --          .endofpacket
			sink1_ready         => rsp_demux_001_src0_ready,                                     --     sink1.ready
			sink1_valid         => rsp_demux_001_src0_valid,                                     --          .valid
			sink1_channel       => rsp_demux_001_src0_channel,                                   --          .channel
			sink1_data          => rsp_demux_001_src0_data,                                      --          .data
			sink1_startofpacket => rsp_demux_001_src0_startofpacket,                             --          .startofpacket
			sink1_endofpacket   => rsp_demux_001_src0_endofpacket,                               --          .endofpacket
			sink2_ready         => rsp_demux_002_src0_ready,                                     --     sink2.ready
			sink2_valid         => rsp_demux_002_src0_valid,                                     --          .valid
			sink2_channel       => rsp_demux_002_src0_channel,                                   --          .channel
			sink2_data          => rsp_demux_002_src0_data,                                      --          .data
			sink2_startofpacket => rsp_demux_002_src0_startofpacket,                             --          .startofpacket
			sink2_endofpacket   => rsp_demux_002_src0_endofpacket                                --          .endofpacket
		);

	avalon_st_adapter : component ddr3controller_s0_mm_interconnect_0_avalon_st_adapter
		generic map (
			inBitsPerSymbol => 34,
			inUsePackets    => 0,
			inDataWidth     => 34,
			inChannelWidth  => 0,
			inErrorWidth    => 0,
			inUseEmptyPort  => 0,
			inUseValid      => 1,
			inUseReady      => 1,
			inReadyLatency  => 0,
			outDataWidth    => 34,
			outChannelWidth => 0,
			outErrorWidth   => 1,
			outUseEmptyPort => 0,
			outUseValid     => 1,
			outUseReady     => 1,
			outReadyLatency => 0
		)
		port map (
			in_clk_0_clk   => avl_clk_out_clk_clk,                                          -- in_clk_0.clk
			in_rst_0_reset => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- in_rst_0.reset
			in_0_data      => sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_data,         --     in_0.data
			in_0_valid     => sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_valid,        --         .valid
			in_0_ready     => sequencer_phy_mgr_inst_avl_agent_rdata_fifo_src_ready,        --         .ready
			out_0_data     => avalon_st_adapter_out_0_data,                                 --    out_0.data
			out_0_valid    => avalon_st_adapter_out_0_valid,                                --         .valid
			out_0_ready    => avalon_st_adapter_out_0_ready,                                --         .ready
			out_0_error    => avalon_st_adapter_out_0_error                                 --         .error
		);

	avalon_st_adapter_001 : component ddr3controller_s0_mm_interconnect_0_avalon_st_adapter
		generic map (
			inBitsPerSymbol => 34,
			inUsePackets    => 0,
			inDataWidth     => 34,
			inChannelWidth  => 0,
			inErrorWidth    => 0,
			inUseEmptyPort  => 0,
			inUseValid      => 1,
			inUseReady      => 1,
			inReadyLatency  => 0,
			outDataWidth    => 34,
			outChannelWidth => 0,
			outErrorWidth   => 1,
			outUseEmptyPort => 0,
			outUseValid     => 1,
			outUseReady     => 1,
			outReadyLatency => 0
		)
		port map (
			in_clk_0_clk   => avl_clk_out_clk_clk,                                          -- in_clk_0.clk
			in_rst_0_reset => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- in_rst_0.reset
			in_0_data      => sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_data,          --     in_0.data
			in_0_valid     => sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_valid,         --         .valid
			in_0_ready     => sequencer_rw_mgr_inst_avl_agent_rdata_fifo_src_ready,         --         .ready
			out_0_data     => avalon_st_adapter_001_out_0_data,                             --    out_0.data
			out_0_valid    => avalon_st_adapter_001_out_0_valid,                            --         .valid
			out_0_ready    => avalon_st_adapter_001_out_0_ready,                            --         .ready
			out_0_error    => avalon_st_adapter_001_out_0_error                             --         .error
		);

	avalon_st_adapter_002 : component ddr3controller_s0_mm_interconnect_0_avalon_st_adapter
		generic map (
			inBitsPerSymbol => 34,
			inUsePackets    => 0,
			inDataWidth     => 34,
			inChannelWidth  => 0,
			inErrorWidth    => 0,
			inUseEmptyPort  => 0,
			inUseValid      => 1,
			inUseReady      => 1,
			inReadyLatency  => 0,
			outDataWidth    => 34,
			outChannelWidth => 0,
			outErrorWidth   => 1,
			outUseEmptyPort => 0,
			outUseValid     => 1,
			outUseReady     => 1,
			outReadyLatency => 0
		)
		port map (
			in_clk_0_clk   => avl_clk_out_clk_clk,                                          -- in_clk_0.clk
			in_rst_0_reset => sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, -- in_rst_0.reset
			in_0_data      => sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_data,         --     in_0.data
			in_0_valid     => sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_valid,        --         .valid
			in_0_ready     => sequencer_pll_mgr_inst_avl_agent_rdata_fifo_src_ready,        --         .ready
			out_0_data     => avalon_st_adapter_002_out_0_data,                             --    out_0.data
			out_0_valid    => avalon_st_adapter_002_out_0_valid,                            --         .valid
			out_0_ready    => avalon_st_adapter_002_out_0_ready,                            --         .ready
			out_0_error    => avalon_st_adapter_002_out_0_error                             --         .error
		);

end architecture rtl; -- of ddr3controller_s0_mm_interconnect_0
