{ "Info" "IQEXE_SEPARATOR" "" "*******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "Design Software" 0 -1 1613933525956 ""}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus Prime " "Running Quartus Prime Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition " "Version 18.1.0 Build 625 09/12/2018 SJ Lite Edition" {  } {  } 0 0 "%1!s!" 0 0 "Design Software" 0 -1 1613933525959 ""} { "Info" "IQEXE_START_BANNER_TIME" "Sun Feb 21 19:52:05 2021 " "Processing started: Sun Feb 21 19:52:05 2021" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "Design Software" 0 -1 1613933525959 ""}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933525959 ""}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off deca-ddr3-test -c deca-ddr3-test " "Command: quartus_map --read_settings_files=on --write_settings_files=off deca-ddr3-test -c deca-ddr3-test" {  } {  } 0 0 "Command: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933525959 ""}
{ "Warning" "WQCU_PARALLEL_USER_SHOULD_SPECIFY_NUM_PROC" "" "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." {  } {  } 0 18236 "Number of processors has not been specified which may cause overloading on shared machines.  Set the global assignment NUM_PARALLEL_PROCESSORS in your QSF to an appropriate value for best performance." 0 0 "Analysis & Synthesis" 0 -1 1613933528567 ""}
{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "4 4 " "Parallel compilation is enabled and will use 4 of the 4 processors detected" {  } {  } 0 20030 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "Analysis & Synthesis" 0 -1 1613933528567 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller.vhd 2 1 " "Found 2 design units, including 1 entities, in source file ddr3controller.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 ddr3controller-rtl " "Found design unit 1: ddr3controller-rtl" {  } { { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 56 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535821 ""} { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller " "Found entity 1: ddr3controller" {  } { { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 11 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535821 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535821 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_0002.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_0002.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_0002 " "Found entity 1: ddr3controller_0002" {  } { { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535823 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535823 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_c0.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_c0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_c0 " "Found entity 1: ddr3controller_c0" {  } { { "ddr3controller/ddr3controller_c0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_c0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535823 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535823 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_mm_st_converter.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_mm_st_converter.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_mm_st_converter " "Found entity 1: alt_mem_ddrx_mm_st_converter" {  } { { "ddr3controller/alt_mem_ddrx_mm_st_converter.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_mm_st_converter.v" 26 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535824 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535824 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_addr_cmd.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_addr_cmd.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_addr_cmd " "Found entity 1: alt_mem_ddrx_addr_cmd" {  } { { "ddr3controller/alt_mem_ddrx_addr_cmd.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_addr_cmd.v" 27 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535825 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535825 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_addr_cmd_wrap " "Found entity 1: alt_mem_ddrx_addr_cmd_wrap" {  } { { "ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535828 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535828 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_ddr2_odt_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_ddr2_odt_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_ddr2_odt_gen " "Found entity 1: alt_mem_ddrx_ddr2_odt_gen" {  } { { "ddr3controller/alt_mem_ddrx_ddr2_odt_gen.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ddr2_odt_gen.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535829 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535829 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_ddr3_odt_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_ddr3_odt_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_ddr3_odt_gen " "Found entity 1: alt_mem_ddrx_ddr3_odt_gen" {  } { { "ddr3controller/alt_mem_ddrx_ddr3_odt_gen.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ddr3_odt_gen.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535829 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535829 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_lpddr2_addr_cmd.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_lpddr2_addr_cmd.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_lpddr2_addr_cmd " "Found entity 1: alt_mem_ddrx_lpddr2_addr_cmd" {  } { { "ddr3controller/alt_mem_ddrx_lpddr2_addr_cmd.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_lpddr2_addr_cmd.v" 23 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535830 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535830 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_odt_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_odt_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_odt_gen " "Found entity 1: alt_mem_ddrx_odt_gen" {  } { { "ddr3controller/alt_mem_ddrx_odt_gen.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_odt_gen.v" 20 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535831 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535831 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "i I alt_mem_ddrx_rdwr_data_tmg.v(114) " "Verilog HDL Declaration information at alt_mem_ddrx_rdwr_data_tmg.v(114): object \"i\" differs only in case from object \"I\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_rdwr_data_tmg.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rdwr_data_tmg.v" 114 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535836 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_rdwr_data_tmg.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_rdwr_data_tmg.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_rdwr_data_tmg " "Found entity 1: alt_mem_ddrx_rdwr_data_tmg" {  } { { "ddr3controller/alt_mem_ddrx_rdwr_data_tmg.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rdwr_data_tmg.v" 35 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535837 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535837 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_arbiter.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_arbiter.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_arbiter " "Found entity 1: alt_mem_ddrx_arbiter" {  } { { "ddr3controller/alt_mem_ddrx_arbiter.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_arbiter.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535838 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535838 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_burst_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_burst_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_burst_gen " "Found entity 1: alt_mem_ddrx_burst_gen" {  } { { "ddr3controller/alt_mem_ddrx_burst_gen.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_burst_gen.v" 20 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535841 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535841 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_cmd_gen.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_cmd_gen.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_cmd_gen " "Found entity 1: alt_mem_ddrx_cmd_gen" {  } { { "ddr3controller/alt_mem_ddrx_cmd_gen.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_cmd_gen.v" 20 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535844 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535844 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_CAS_WR_LAT cfg_cas_wr_lat alt_mem_ddrx_csr.v(61) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(61): object \"CFG_CAS_WR_LAT\" differs only in case from object \"cfg_cas_wr_lat\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 61 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ADD_LAT cfg_add_lat alt_mem_ddrx_csr.v(62) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(62): object \"CFG_ADD_LAT\" differs only in case from object \"cfg_add_lat\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 62 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TCL cfg_tcl alt_mem_ddrx_csr.v(63) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(63): object \"CFG_TCL\" differs only in case from object \"cfg_tcl\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 63 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_BURST_LENGTH cfg_burst_length alt_mem_ddrx_csr.v(64) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(64): object \"CFG_BURST_LENGTH\" differs only in case from object \"cfg_burst_length\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 64 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRRD cfg_trrd alt_mem_ddrx_csr.v(65) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(65): object \"CFG_TRRD\" differs only in case from object \"cfg_trrd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 65 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TFAW cfg_tfaw alt_mem_ddrx_csr.v(66) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(66): object \"CFG_TFAW\" differs only in case from object \"cfg_tfaw\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 66 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRFC cfg_trfc alt_mem_ddrx_csr.v(67) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(67): object \"CFG_TRFC\" differs only in case from object \"cfg_trfc\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 67 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TREFI cfg_trefi alt_mem_ddrx_csr.v(68) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(68): object \"CFG_TREFI\" differs only in case from object \"cfg_trefi\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 68 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRCD cfg_trcd alt_mem_ddrx_csr.v(69) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(69): object \"CFG_TRCD\" differs only in case from object \"cfg_trcd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 69 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRP cfg_trp alt_mem_ddrx_csr.v(70) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(70): object \"CFG_TRP\" differs only in case from object \"cfg_trp\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 70 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TWR cfg_twr alt_mem_ddrx_csr.v(71) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(71): object \"CFG_TWR\" differs only in case from object \"cfg_twr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 71 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TWTR cfg_twtr alt_mem_ddrx_csr.v(72) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(72): object \"CFG_TWTR\" differs only in case from object \"cfg_twtr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 72 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRTP cfg_trtp alt_mem_ddrx_csr.v(73) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(73): object \"CFG_TRTP\" differs only in case from object \"cfg_trtp\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 73 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRAS cfg_tras alt_mem_ddrx_csr.v(74) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(74): object \"CFG_TRAS\" differs only in case from object \"cfg_tras\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 74 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRC cfg_trc alt_mem_ddrx_csr.v(75) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(75): object \"CFG_TRC\" differs only in case from object \"cfg_trc\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 75 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_AUTO_PD_CYCLES cfg_auto_pd_cycles alt_mem_ddrx_csr.v(76) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(76): object \"CFG_AUTO_PD_CYCLES\" differs only in case from object \"cfg_auto_pd_cycles\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 76 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ADDR_ORDER cfg_addr_order alt_mem_ddrx_csr.v(79) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(79): object \"CFG_ADDR_ORDER\" differs only in case from object \"cfg_addr_order\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 79 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_REORDER_DATA cfg_reorder_data alt_mem_ddrx_csr.v(80) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(80): object \"CFG_REORDER_DATA\" differs only in case from object \"cfg_reorder_data\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 80 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_STARVE_LIMIT cfg_starve_limit alt_mem_ddrx_csr.v(81) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(81): object \"CFG_STARVE_LIMIT\" differs only in case from object \"cfg_starve_limit\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 81 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_COL_ADDR_WIDTH cfg_col_addr_width alt_mem_ddrx_csr.v(33) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(33): object \"CFG_COL_ADDR_WIDTH\" differs only in case from object \"cfg_col_addr_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 33 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ROW_ADDR_WIDTH cfg_row_addr_width alt_mem_ddrx_csr.v(32) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(32): object \"CFG_ROW_ADDR_WIDTH\" differs only in case from object \"cfg_row_addr_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 32 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_BANK_ADDR_WIDTH cfg_bank_addr_width alt_mem_ddrx_csr.v(34) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(34): object \"CFG_BANK_ADDR_WIDTH\" differs only in case from object \"cfg_bank_addr_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 34 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_CS_ADDR_WIDTH cfg_cs_addr_width alt_mem_ddrx_csr.v(31) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(31): object \"CFG_CS_ADDR_WIDTH\" differs only in case from object \"cfg_cs_addr_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 31 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535846 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_ECC cfg_enable_ecc alt_mem_ddrx_csr.v(36) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(36): object \"CFG_ENABLE_ECC\" differs only in case from object \"cfg_enable_ecc\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 36 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535847 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_AUTO_CORR cfg_enable_auto_corr alt_mem_ddrx_csr.v(37) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(37): object \"CFG_ENABLE_AUTO_CORR\" differs only in case from object \"cfg_enable_auto_corr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 37 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535847 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_REGDIMM_ENABLE cfg_regdimm_enable alt_mem_ddrx_csr.v(38) " "Verilog HDL Declaration information at alt_mem_ddrx_csr.v(38): object \"CFG_REGDIMM_ENABLE\" differs only in case from object \"cfg_regdimm_enable\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 38 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535847 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_csr.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_csr.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_csr " "Found entity 1: alt_mem_ddrx_csr" {  } { { "ddr3controller/alt_mem_ddrx_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_csr.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535847 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535847 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_buffer.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_buffer " "Found entity 1: alt_mem_ddrx_buffer" {  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535847 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535847 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_buffer_manager.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_buffer_manager.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_buffer_manager " "Found entity 1: alt_mem_ddrx_buffer_manager" {  } { { "ddr3controller/alt_mem_ddrx_buffer_manager.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer_manager.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535848 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535848 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_burst_tracking.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_burst_tracking.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_burst_tracking " "Found entity 1: alt_mem_ddrx_burst_tracking" {  } { { "ddr3controller/alt_mem_ddrx_burst_tracking.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_burst_tracking.v" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535848 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535848 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_dataid_manager.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_dataid_manager.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_dataid_manager " "Found entity 1: alt_mem_ddrx_dataid_manager" {  } { { "ddr3controller/alt_mem_ddrx_dataid_manager.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_dataid_manager.v" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535850 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535850 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_fifo " "Found entity 1: alt_mem_ddrx_fifo" {  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535850 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535850 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_list.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_list.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_list " "Found entity 1: alt_mem_ddrx_list" {  } { { "ddr3controller/alt_mem_ddrx_list.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_list.v" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535851 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535851 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_rdata_path.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_rdata_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_rdata_path " "Found entity 1: alt_mem_ddrx_rdata_path" {  } { { "ddr3controller/alt_mem_ddrx_rdata_path.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rdata_path.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535853 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535853 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_wdata_path.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_wdata_path.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_wdata_path " "Found entity 1: alt_mem_ddrx_wdata_path" {  } { { "ddr3controller/alt_mem_ddrx_wdata_path.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_wdata_path.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535855 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535855 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_ecc_decoder.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_ecc_decoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_ecc_decoder " "Found entity 1: alt_mem_ddrx_ecc_decoder" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535856 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535856 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v 3 3 " "Found 3 design units, including 3 entities, in source file ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_ecc_decoder_32_decode " "Found entity 1: alt_mem_ddrx_ecc_decoder_32_decode" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" 63 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535858 ""} { "Info" "ISGN_ENTITY_NAME" "2 alt_mem_ddrx_ecc_decoder_32_altecc_decoder " "Found entity 2: alt_mem_ddrx_ecc_decoder_32_altecc_decoder" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" 238 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535858 ""} { "Info" "ISGN_ENTITY_NAME" "3 alt_mem_ddrx_ecc_decoder_32 " "Found entity 3: alt_mem_ddrx_ecc_decoder_32" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" 412 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535858 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535858 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_ecc_decoder_64_syn.v 3 3 " "Found 3 design units, including 3 entities, in source file ddr3controller/alt_mem_ddrx_ecc_decoder_64_syn.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_ecc_decoder_64_decode " "Found entity 1: alt_mem_ddrx_ecc_decoder_64_decode" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder_64_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder_64_syn.v" 63 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535861 ""} { "Info" "ISGN_ENTITY_NAME" "2 alt_mem_ddrx_ecc_decoder_64_altecc_decoder " "Found entity 2: alt_mem_ddrx_ecc_decoder_64_altecc_decoder" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder_64_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder_64_syn.v" 390 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535861 ""} { "Info" "ISGN_ENTITY_NAME" "3 alt_mem_ddrx_ecc_decoder_64 " "Found entity 3: alt_mem_ddrx_ecc_decoder_64" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder_64_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder_64_syn.v" 630 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535861 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535861 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_ecc_encoder.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_ecc_encoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_ecc_encoder " "Found entity 1: alt_mem_ddrx_ecc_encoder" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535862 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535862 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_ecc_encoder_32_syn.v 2 2 " "Found 2 design units, including 2 entities, in source file ddr3controller/alt_mem_ddrx_ecc_encoder_32_syn.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_ecc_encoder_32_altecc_encoder " "Found entity 1: alt_mem_ddrx_ecc_encoder_32_altecc_encoder" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_32_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_32_syn.v" 59 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535862 ""} { "Info" "ISGN_ENTITY_NAME" "2 alt_mem_ddrx_ecc_encoder_32 " "Found entity 2: alt_mem_ddrx_ecc_encoder_32" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_32_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_32_syn.v" 229 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535862 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535862 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_ecc_encoder_64_syn.v 2 2 " "Found 2 design units, including 2 entities, in source file ddr3controller/alt_mem_ddrx_ecc_encoder_64_syn.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_ecc_encoder_64_altecc_encoder " "Found entity 1: alt_mem_ddrx_ecc_encoder_64_altecc_encoder" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_64_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_64_syn.v" 59 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535863 ""} { "Info" "ISGN_ENTITY_NAME" "2 alt_mem_ddrx_ecc_encoder_64 " "Found entity 2: alt_mem_ddrx_ecc_encoder_64" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_64_syn.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_64_syn.v" 328 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535863 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535863 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_LOCAL_DATA_WIDTH cfg_local_data_width alt_mem_ddrx_ecc_encoder_decoder_wrapper.v(20) " "Verilog HDL Declaration information at alt_mem_ddrx_ecc_encoder_decoder_wrapper.v(20): object \"CFG_LOCAL_DATA_WIDTH\" differs only in case from object \"cfg_local_data_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" 20 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535865 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_LOCAL_DM_WIDTH cfg_local_dm_width alt_mem_ddrx_ecc_encoder_decoder_wrapper.v(158) " "Verilog HDL Declaration information at alt_mem_ddrx_ecc_encoder_decoder_wrapper.v(158): object \"CFG_LOCAL_DM_WIDTH\" differs only in case from object \"cfg_local_dm_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" 158 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535865 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_ecc_encoder_decoder_wrapper " "Found entity 1: alt_mem_ddrx_ecc_encoder_decoder_wrapper" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535865 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535865 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_axi_st_converter.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_axi_st_converter.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_axi_st_converter " "Found entity 1: alt_mem_ddrx_axi_st_converter" {  } { { "ddr3controller/alt_mem_ddrx_axi_st_converter.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_axi_st_converter.v" 15 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535867 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535867 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_input_if.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_input_if.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_input_if " "Found entity 1: alt_mem_ddrx_input_if" {  } { { "ddr3controller/alt_mem_ddrx_input_if.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_input_if.v" 15 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535868 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535868 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_rank_timer.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_rank_timer.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_rank_timer " "Found entity 1: alt_mem_ddrx_rank_timer" {  } { { "ddr3controller/alt_mem_ddrx_rank_timer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rank_timer.v" 20 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535871 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535871 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_sideband.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_sideband.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_sideband " "Found entity 1: alt_mem_ddrx_sideband" {  } { { "ddr3controller/alt_mem_ddrx_sideband.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_sideband.v" 20 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535873 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535873 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_tbp.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_tbp.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_tbp " "Found entity 1: alt_mem_ddrx_tbp" {  } { { "ddr3controller/alt_mem_ddrx_tbp.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_tbp.v" 20 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535879 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535879 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_timing_param.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_timing_param.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_timing_param " "Found entity 1: alt_mem_ddrx_timing_param" {  } { { "ddr3controller/alt_mem_ddrx_timing_param.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_timing_param.v" 20 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535881 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535881 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_OUTPUT_REGD cfg_output_regd alt_mem_ddrx_controller.v(43) " "Verilog HDL Declaration information at alt_mem_ddrx_controller.v(43): object \"CFG_OUTPUT_REGD\" differs only in case from object \"cfg_output_regd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 43 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535885 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_controller.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_controller.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_controller " "Found entity 1: alt_mem_ddrx_controller" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535885 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535885 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TYPE cfg_type alt_mem_ddrx_controller_st_top.v(150) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(150): object \"CFG_TYPE\" differs only in case from object \"cfg_type\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 150 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535887 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_BURST_LENGTH cfg_burst_length alt_mem_ddrx_controller_st_top.v(152) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(152): object \"CFG_BURST_LENGTH\" differs only in case from object \"cfg_burst_length\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 152 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ADDR_ORDER cfg_addr_order alt_mem_ddrx_controller_st_top.v(157) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(157): object \"CFG_ADDR_ORDER\" differs only in case from object \"cfg_addr_order\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 157 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_ECC cfg_enable_ecc alt_mem_ddrx_controller_st_top.v(271) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(271): object \"CFG_ENABLE_ECC\" differs only in case from object \"cfg_enable_ecc\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 271 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_AUTO_CORR cfg_enable_auto_corr alt_mem_ddrx_controller_st_top.v(272) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(272): object \"CFG_ENABLE_AUTO_CORR\" differs only in case from object \"cfg_enable_auto_corr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 272 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_GEN_SBE cfg_gen_sbe alt_mem_ddrx_controller_st_top.v(182) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(182): object \"CFG_GEN_SBE\" differs only in case from object \"cfg_gen_sbe\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 182 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_GEN_DBE cfg_gen_dbe alt_mem_ddrx_controller_st_top.v(183) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(183): object \"CFG_GEN_DBE\" differs only in case from object \"cfg_gen_dbe\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 183 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_REORDER_DATA cfg_reorder_data alt_mem_ddrx_controller_st_top.v(154) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(154): object \"CFG_REORDER_DATA\" differs only in case from object \"cfg_reorder_data\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 154 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_USER_RFSH cfg_user_rfsh alt_mem_ddrx_controller_st_top.v(305) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(305): object \"CFG_USER_RFSH\" differs only in case from object \"cfg_user_rfsh\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 305 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_REGDIMM_ENABLE cfg_regdimm_enable alt_mem_ddrx_controller_st_top.v(306) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(306): object \"CFG_REGDIMM_ENABLE\" differs only in case from object \"cfg_regdimm_enable\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 306 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_BURST_INTERRUPT cfg_enable_burst_interrupt alt_mem_ddrx_controller_st_top.v(307) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(307): object \"CFG_ENABLE_BURST_INTERRUPT\" differs only in case from object \"cfg_enable_burst_interrupt\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 307 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_BURST_TERMINATE cfg_enable_burst_terminate alt_mem_ddrx_controller_st_top.v(308) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(308): object \"CFG_ENABLE_BURST_TERMINATE\" differs only in case from object \"cfg_enable_burst_terminate\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 308 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_DQS_TRACKING cfg_enable_dqs_tracking alt_mem_ddrx_controller_st_top.v(203) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(203): object \"CFG_ENABLE_DQS_TRACKING\" differs only in case from object \"cfg_enable_dqs_tracking\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 203 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_OUTPUT_REGD cfg_output_regd alt_mem_ddrx_controller_st_top.v(303) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(303): object \"CFG_OUTPUT_REGD\" differs only in case from object \"cfg_output_regd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 303 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_NO_DM cfg_enable_no_dm alt_mem_ddrx_controller_st_top.v(199) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(199): object \"CFG_ENABLE_NO_DM\" differs only in case from object \"cfg_enable_no_dm\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 199 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_ECC_CODE_OVERWRITES cfg_enable_ecc_code_overwrites alt_mem_ddrx_controller_st_top.v(274) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(274): object \"CFG_ENABLE_ECC_CODE_OVERWRITES\" differs only in case from object \"cfg_enable_ecc_code_overwrites\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 274 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_CAS_WR_LAT cfg_cas_wr_lat alt_mem_ddrx_controller_st_top.v(255) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(255): object \"CFG_CAS_WR_LAT\" differs only in case from object \"cfg_cas_wr_lat\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 255 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ADD_LAT cfg_add_lat alt_mem_ddrx_controller_st_top.v(256) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(256): object \"CFG_ADD_LAT\" differs only in case from object \"cfg_add_lat\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 256 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TCL cfg_tcl alt_mem_ddrx_controller_st_top.v(257) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(257): object \"CFG_TCL\" differs only in case from object \"cfg_tcl\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 257 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRRD cfg_trrd alt_mem_ddrx_controller_st_top.v(258) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(258): object \"CFG_TRRD\" differs only in case from object \"cfg_trrd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 258 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TFAW cfg_tfaw alt_mem_ddrx_controller_st_top.v(259) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(259): object \"CFG_TFAW\" differs only in case from object \"cfg_tfaw\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 259 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRFC cfg_trfc alt_mem_ddrx_controller_st_top.v(260) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(260): object \"CFG_TRFC\" differs only in case from object \"cfg_trfc\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 260 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TREFI cfg_trefi alt_mem_ddrx_controller_st_top.v(261) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(261): object \"CFG_TREFI\" differs only in case from object \"cfg_trefi\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 261 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRCD cfg_trcd alt_mem_ddrx_controller_st_top.v(262) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(262): object \"CFG_TRCD\" differs only in case from object \"cfg_trcd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 262 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRP cfg_trp alt_mem_ddrx_controller_st_top.v(263) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(263): object \"CFG_TRP\" differs only in case from object \"cfg_trp\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 263 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TWR cfg_twr alt_mem_ddrx_controller_st_top.v(264) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(264): object \"CFG_TWR\" differs only in case from object \"cfg_twr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 264 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TWTR cfg_twtr alt_mem_ddrx_controller_st_top.v(265) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(265): object \"CFG_TWTR\" differs only in case from object \"cfg_twtr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 265 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRTP cfg_trtp alt_mem_ddrx_controller_st_top.v(266) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(266): object \"CFG_TRTP\" differs only in case from object \"cfg_trtp\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 266 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRAS cfg_tras alt_mem_ddrx_controller_st_top.v(267) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(267): object \"CFG_TRAS\" differs only in case from object \"cfg_tras\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 267 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TRC cfg_trc alt_mem_ddrx_controller_st_top.v(268) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(268): object \"CFG_TRC\" differs only in case from object \"cfg_trc\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 268 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_AUTO_PD_CYCLES cfg_auto_pd_cycles alt_mem_ddrx_controller_st_top.v(269) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(269): object \"CFG_AUTO_PD_CYCLES\" differs only in case from object \"cfg_auto_pd_cycles\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 269 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_SELF_RFSH_EXIT_CYCLES cfg_self_rfsh_exit_cycles alt_mem_ddrx_controller_st_top.v(174) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(174): object \"CFG_SELF_RFSH_EXIT_CYCLES\" differs only in case from object \"cfg_self_rfsh_exit_cycles\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 174 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_PDN_EXIT_CYCLES cfg_pdn_exit_cycles alt_mem_ddrx_controller_st_top.v(175) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(175): object \"CFG_PDN_EXIT_CYCLES\" differs only in case from object \"cfg_pdn_exit_cycles\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 175 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_POWER_SAVING_EXIT_CYCLES cfg_power_saving_exit_cycles alt_mem_ddrx_controller_st_top.v(176) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(176): object \"CFG_POWER_SAVING_EXIT_CYCLES\" differs only in case from object \"cfg_power_saving_exit_cycles\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 176 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_MEM_CLK_ENTRY_CYCLES cfg_mem_clk_entry_cycles alt_mem_ddrx_controller_st_top.v(177) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(177): object \"CFG_MEM_CLK_ENTRY_CYCLES\" differs only in case from object \"cfg_mem_clk_entry_cycles\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 177 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TMRD cfg_tmrd alt_mem_ddrx_controller_st_top.v(270) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(270): object \"CFG_TMRD\" differs only in case from object \"cfg_tmrd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 270 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_COL_ADDR_WIDTH cfg_col_addr_width alt_mem_ddrx_controller_st_top.v(251) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(251): object \"CFG_COL_ADDR_WIDTH\" differs only in case from object \"cfg_col_addr_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 251 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ROW_ADDR_WIDTH cfg_row_addr_width alt_mem_ddrx_controller_st_top.v(252) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(252): object \"CFG_ROW_ADDR_WIDTH\" differs only in case from object \"cfg_row_addr_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 252 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_BANK_ADDR_WIDTH cfg_bank_addr_width alt_mem_ddrx_controller_st_top.v(253) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(253): object \"CFG_BANK_ADDR_WIDTH\" differs only in case from object \"cfg_bank_addr_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 253 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_CS_ADDR_WIDTH cfg_cs_addr_width alt_mem_ddrx_controller_st_top.v(254) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(254): object \"CFG_CS_ADDR_WIDTH\" differs only in case from object \"cfg_cs_addr_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 254 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_ENABLE_INTR cfg_enable_intr alt_mem_ddrx_controller_st_top.v(184) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(184): object \"CFG_ENABLE_INTR\" differs only in case from object \"cfg_enable_intr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 184 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_MASK_SBE_INTR cfg_mask_sbe_intr alt_mem_ddrx_controller_st_top.v(185) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(185): object \"CFG_MASK_SBE_INTR\" differs only in case from object \"cfg_mask_sbe_intr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 185 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_MASK_DBE_INTR cfg_mask_dbe_intr alt_mem_ddrx_controller_st_top.v(186) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(186): object \"CFG_MASK_DBE_INTR\" differs only in case from object \"cfg_mask_dbe_intr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 186 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_CLR_INTR cfg_clr_intr alt_mem_ddrx_controller_st_top.v(188) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(188): object \"CFG_CLR_INTR\" differs only in case from object \"cfg_clr_intr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 188 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_CAL_REQ cfg_cal_req alt_mem_ddrx_controller_st_top.v(275) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(275): object \"CFG_CAL_REQ\" differs only in case from object \"cfg_cal_req\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 275 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_ACT_TO_RDWR cfg_extra_ctl_clk_act_to_rdwr alt_mem_ddrx_controller_st_top.v(276) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(276): object \"CFG_EXTRA_CTL_CLK_ACT_TO_RDWR\" differs only in case from object \"cfg_extra_ctl_clk_act_to_rdwr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 276 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_ACT_TO_PCH cfg_extra_ctl_clk_act_to_pch alt_mem_ddrx_controller_st_top.v(277) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(277): object \"CFG_EXTRA_CTL_CLK_ACT_TO_PCH\" differs only in case from object \"cfg_extra_ctl_clk_act_to_pch\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 277 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_ACT_TO_ACT cfg_extra_ctl_clk_act_to_act alt_mem_ddrx_controller_st_top.v(278) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(278): object \"CFG_EXTRA_CTL_CLK_ACT_TO_ACT\" differs only in case from object \"cfg_extra_ctl_clk_act_to_act\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 278 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_RD_TO_RD cfg_extra_ctl_clk_rd_to_rd alt_mem_ddrx_controller_st_top.v(279) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(279): object \"CFG_EXTRA_CTL_CLK_RD_TO_RD\" differs only in case from object \"cfg_extra_ctl_clk_rd_to_rd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 279 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP cfg_extra_ctl_clk_rd_to_rd_diff_chip alt_mem_ddrx_controller_st_top.v(280) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(280): object \"CFG_EXTRA_CTL_CLK_RD_TO_RD_DIFF_CHIP\" differs only in case from object \"cfg_extra_ctl_clk_rd_to_rd_diff_chip\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 280 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535888 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_RD_TO_WR cfg_extra_ctl_clk_rd_to_wr alt_mem_ddrx_controller_st_top.v(281) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(281): object \"CFG_EXTRA_CTL_CLK_RD_TO_WR\" differs only in case from object \"cfg_extra_ctl_clk_rd_to_wr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 281 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_RD_TO_WR_BC cfg_extra_ctl_clk_rd_to_wr_bc alt_mem_ddrx_controller_st_top.v(282) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(282): object \"CFG_EXTRA_CTL_CLK_RD_TO_WR_BC\" differs only in case from object \"cfg_extra_ctl_clk_rd_to_wr_bc\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 282 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP cfg_extra_ctl_clk_rd_to_wr_diff_chip alt_mem_ddrx_controller_st_top.v(283) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(283): object \"CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP\" differs only in case from object \"cfg_extra_ctl_clk_rd_to_wr_diff_chip\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 283 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_RD_TO_PCH cfg_extra_ctl_clk_rd_to_pch alt_mem_ddrx_controller_st_top.v(284) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(284): object \"CFG_EXTRA_CTL_CLK_RD_TO_PCH\" differs only in case from object \"cfg_extra_ctl_clk_rd_to_pch\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 284 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID cfg_extra_ctl_clk_rd_ap_to_valid alt_mem_ddrx_controller_st_top.v(285) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(285): object \"CFG_EXTRA_CTL_CLK_RD_AP_TO_VALID\" differs only in case from object \"cfg_extra_ctl_clk_rd_ap_to_valid\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 285 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_WR_TO_WR cfg_extra_ctl_clk_wr_to_wr alt_mem_ddrx_controller_st_top.v(286) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(286): object \"CFG_EXTRA_CTL_CLK_WR_TO_WR\" differs only in case from object \"cfg_extra_ctl_clk_wr_to_wr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 286 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP cfg_extra_ctl_clk_wr_to_wr_diff_chip alt_mem_ddrx_controller_st_top.v(287) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(287): object \"CFG_EXTRA_CTL_CLK_WR_TO_WR_DIFF_CHIP\" differs only in case from object \"cfg_extra_ctl_clk_wr_to_wr_diff_chip\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 287 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_WR_TO_RD cfg_extra_ctl_clk_wr_to_rd alt_mem_ddrx_controller_st_top.v(288) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(288): object \"CFG_EXTRA_CTL_CLK_WR_TO_RD\" differs only in case from object \"cfg_extra_ctl_clk_wr_to_rd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 288 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_WR_TO_RD_BC cfg_extra_ctl_clk_wr_to_rd_bc alt_mem_ddrx_controller_st_top.v(289) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(289): object \"CFG_EXTRA_CTL_CLK_WR_TO_RD_BC\" differs only in case from object \"cfg_extra_ctl_clk_wr_to_rd_bc\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 289 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP cfg_extra_ctl_clk_wr_to_rd_diff_chip alt_mem_ddrx_controller_st_top.v(290) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(290): object \"CFG_EXTRA_CTL_CLK_WR_TO_RD_DIFF_CHIP\" differs only in case from object \"cfg_extra_ctl_clk_wr_to_rd_diff_chip\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 290 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_WR_TO_PCH cfg_extra_ctl_clk_wr_to_pch alt_mem_ddrx_controller_st_top.v(291) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(291): object \"CFG_EXTRA_CTL_CLK_WR_TO_PCH\" differs only in case from object \"cfg_extra_ctl_clk_wr_to_pch\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 291 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID cfg_extra_ctl_clk_wr_ap_to_valid alt_mem_ddrx_controller_st_top.v(292) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(292): object \"CFG_EXTRA_CTL_CLK_WR_AP_TO_VALID\" differs only in case from object \"cfg_extra_ctl_clk_wr_ap_to_valid\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 292 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_PCH_TO_VALID cfg_extra_ctl_clk_pch_to_valid alt_mem_ddrx_controller_st_top.v(293) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(293): object \"CFG_EXTRA_CTL_CLK_PCH_TO_VALID\" differs only in case from object \"cfg_extra_ctl_clk_pch_to_valid\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 293 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID cfg_extra_ctl_clk_pch_all_to_valid alt_mem_ddrx_controller_st_top.v(294) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(294): object \"CFG_EXTRA_CTL_CLK_PCH_ALL_TO_VALID\" differs only in case from object \"cfg_extra_ctl_clk_pch_all_to_valid\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 294 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK cfg_extra_ctl_clk_act_to_act_diff_bank alt_mem_ddrx_controller_st_top.v(295) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(295): object \"CFG_EXTRA_CTL_CLK_ACT_TO_ACT_DIFF_BANK\" differs only in case from object \"cfg_extra_ctl_clk_act_to_act_diff_bank\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 295 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT cfg_extra_ctl_clk_four_act_to_act alt_mem_ddrx_controller_st_top.v(296) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(296): object \"CFG_EXTRA_CTL_CLK_FOUR_ACT_TO_ACT\" differs only in case from object \"cfg_extra_ctl_clk_four_act_to_act\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 296 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_ARF_TO_VALID cfg_extra_ctl_clk_arf_to_valid alt_mem_ddrx_controller_st_top.v(297) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(297): object \"CFG_EXTRA_CTL_CLK_ARF_TO_VALID\" differs only in case from object \"cfg_extra_ctl_clk_arf_to_valid\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 297 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_PDN_TO_VALID cfg_extra_ctl_clk_pdn_to_valid alt_mem_ddrx_controller_st_top.v(298) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(298): object \"CFG_EXTRA_CTL_CLK_PDN_TO_VALID\" differs only in case from object \"cfg_extra_ctl_clk_pdn_to_valid\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 298 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_SRF_TO_VALID cfg_extra_ctl_clk_srf_to_valid alt_mem_ddrx_controller_st_top.v(299) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(299): object \"CFG_EXTRA_CTL_CLK_SRF_TO_VALID\" differs only in case from object \"cfg_extra_ctl_clk_srf_to_valid\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 299 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL cfg_extra_ctl_clk_srf_to_zq_cal alt_mem_ddrx_controller_st_top.v(300) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(300): object \"CFG_EXTRA_CTL_CLK_SRF_TO_ZQ_CAL\" differs only in case from object \"cfg_extra_ctl_clk_srf_to_zq_cal\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 300 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_ARF_PERIOD cfg_extra_ctl_clk_arf_period alt_mem_ddrx_controller_st_top.v(301) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(301): object \"CFG_EXTRA_CTL_CLK_ARF_PERIOD\" differs only in case from object \"cfg_extra_ctl_clk_arf_period\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 301 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_EXTRA_CTL_CLK_PDN_PERIOD cfg_extra_ctl_clk_pdn_period alt_mem_ddrx_controller_st_top.v(302) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(302): object \"CFG_EXTRA_CTL_CLK_PDN_PERIOD\" differs only in case from object \"cfg_extra_ctl_clk_pdn_period\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 302 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_STARVE_LIMIT cfg_starve_limit alt_mem_ddrx_controller_st_top.v(156) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(156): object \"CFG_STARVE_LIMIT\" differs only in case from object \"cfg_starve_limit\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 156 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_WRITE_ODT_CHIP cfg_write_odt_chip alt_mem_ddrx_controller_st_top.v(193) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(193): object \"CFG_WRITE_ODT_CHIP\" differs only in case from object \"cfg_write_odt_chip\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 193 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_READ_ODT_CHIP cfg_read_odt_chip alt_mem_ddrx_controller_st_top.v(194) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(194): object \"CFG_READ_ODT_CHIP\" differs only in case from object \"cfg_read_odt_chip\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 194 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_INTERFACE_WIDTH cfg_interface_width alt_mem_ddrx_controller_st_top.v(151) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(151): object \"CFG_INTERFACE_WIDTH\" differs only in case from object \"cfg_interface_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 151 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_DEVICE_WIDTH cfg_device_width alt_mem_ddrx_controller_st_top.v(153) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(153): object \"CFG_DEVICE_WIDTH\" differs only in case from object \"cfg_device_width\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 153 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_TCCD cfg_tccd alt_mem_ddrx_controller_st_top.v(172) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(172): object \"CFG_TCCD\" differs only in case from object \"cfg_tccd\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 172 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "CFG_MASK_CORR_DROPPED_INTR cfg_mask_corr_dropped_intr alt_mem_ddrx_controller_st_top.v(304) " "Verilog HDL Declaration information at alt_mem_ddrx_controller_st_top.v(304): object \"CFG_MASK_CORR_DROPPED_INTR\" differs only in case from object \"cfg_mask_corr_dropped_intr\" in the same scope" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 304 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_ddrx_controller_st_top.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_ddrx_controller_st_top.v" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_ddrx_controller_st_top " "Found entity 1: alt_mem_ddrx_controller_st_top" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 24 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535889 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535889 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/alt_mem_if_nextgen_ddr3_controller_core.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/alt_mem_if_nextgen_ddr3_controller_core.sv" { { "Info" "ISGN_ENTITY_NAME" "1 alt_mem_if_nextgen_ddr3_controller_core " "Found entity 1: alt_mem_if_nextgen_ddr3_controller_core" {  } { { "ddr3controller/alt_mem_if_nextgen_ddr3_controller_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_if_nextgen_ddr3_controller_core.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535890 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535890 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_s0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0 " "Found entity 1: ddr3controller_s0" {  } { { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535891 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535891 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 " "Found entity 1: ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv" 66 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535892 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535892 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0_mm_interconnect_0_avalon_st_adapter " "Found entity 1: ddr3controller_s0_mm_interconnect_0_avalon_st_adapter" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535892 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535892 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0_mm_interconnect_0_rsp_mux " "Found entity 1: ddr3controller_s0_mm_interconnect_0_rsp_mux" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_mux.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_mux.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535893 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535893 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0_mm_interconnect_0_rsp_demux " "Found entity 1: ddr3controller_s0_mm_interconnect_0_rsp_demux" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_demux.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535894 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535894 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/altera_merlin_arbitrator.sv 2 2 " "Found 2 design units, including 2 entities, in source file ddr3controller/altera_merlin_arbitrator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_arbitrator " "Found entity 1: altera_merlin_arbitrator" {  } { { "ddr3controller/altera_merlin_arbitrator.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_arbitrator.sv" 103 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535894 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_merlin_arb_adder " "Found entity 2: altera_merlin_arb_adder" {  } { { "ddr3controller/altera_merlin_arbitrator.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_arbitrator.sv" 228 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535894 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535894 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0_mm_interconnect_0_cmd_mux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_s0_mm_interconnect_0_cmd_mux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0_mm_interconnect_0_cmd_mux " "Found entity 1: ddr3controller_s0_mm_interconnect_0_cmd_mux" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_cmd_mux.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_cmd_mux.sv" 51 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535895 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535895 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0_mm_interconnect_0_cmd_demux.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_s0_mm_interconnect_0_cmd_demux.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0_mm_interconnect_0_cmd_demux " "Found entity 1: ddr3controller_s0_mm_interconnect_0_cmd_demux" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_cmd_demux.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_cmd_demux.sv" 43 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535895 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535895 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ddr3controller_s0_mm_interconnect_0_router_001.sv(48) " "Verilog HDL Declaration information at ddr3controller_s0_mm_interconnect_0_router_001.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535896 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ddr3controller_s0_mm_interconnect_0_router_001.sv(49) " "Verilog HDL Declaration information at ddr3controller_s0_mm_interconnect_0_router_001.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535896 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv 2 2 " "Found 2 design units, including 2 entities, in source file ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0_mm_interconnect_0_router_001_default_decode " "Found entity 1: ddr3controller_s0_mm_interconnect_0_router_001_default_decode" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535896 ""} { "Info" "ISGN_ENTITY_NAME" "2 ddr3controller_s0_mm_interconnect_0_router_001 " "Found entity 2: ddr3controller_s0_mm_interconnect_0_router_001" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535896 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535896 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_WR_CHANNEL default_wr_channel ddr3controller_s0_mm_interconnect_0_router.sv(48) " "Verilog HDL Declaration information at ddr3controller_s0_mm_interconnect_0_router.sv(48): object \"DEFAULT_WR_CHANNEL\" differs only in case from object \"default_wr_channel\" in the same scope" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" 48 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535897 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "DEFAULT_RD_CHANNEL default_rd_channel ddr3controller_s0_mm_interconnect_0_router.sv(49) " "Verilog HDL Declaration information at ddr3controller_s0_mm_interconnect_0_router.sv(49): object \"DEFAULT_RD_CHANNEL\" differs only in case from object \"default_rd_channel\" in the same scope" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" 49 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535897 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv 2 2 " "Found 2 design units, including 2 entities, in source file ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0_mm_interconnect_0_router_default_decode " "Found entity 1: ddr3controller_s0_mm_interconnect_0_router_default_decode" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" 45 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535897 ""} { "Info" "ISGN_ENTITY_NAME" "2 ddr3controller_s0_mm_interconnect_0_router " "Found entity 2: ddr3controller_s0_mm_interconnect_0_router" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" 84 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535897 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535897 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/altera_avalon_sc_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/altera_avalon_sc_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 altera_avalon_sc_fifo " "Found entity 1: altera_avalon_sc_fifo" {  } { { "ddr3controller/altera_avalon_sc_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_avalon_sc_fifo.v" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535898 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535898 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/altera_merlin_burst_uncompressor.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/altera_merlin_burst_uncompressor.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_burst_uncompressor " "Found entity 1: altera_merlin_burst_uncompressor" {  } { { "ddr3controller/altera_merlin_burst_uncompressor.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_burst_uncompressor.sv" 40 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535899 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535899 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/altera_merlin_slave_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/altera_merlin_slave_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_agent " "Found entity 1: altera_merlin_slave_agent" {  } { { "ddr3controller/altera_merlin_slave_agent.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_slave_agent.sv" 34 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535900 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535900 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/altera_merlin_master_agent.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/altera_merlin_master_agent.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_agent " "Found entity 1: altera_merlin_master_agent" {  } { { "ddr3controller/altera_merlin_master_agent.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_master_agent.sv" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535901 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535901 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/altera_merlin_slave_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/altera_merlin_slave_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_slave_translator " "Found entity 1: altera_merlin_slave_translator" {  } { { "ddr3controller/altera_merlin_slave_translator.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_slave_translator.sv" 35 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535902 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535902 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/altera_merlin_master_translator.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/altera_merlin_master_translator.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_merlin_master_translator " "Found entity 1: altera_merlin_master_translator" {  } { { "ddr3controller/altera_merlin_master_translator.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_master_translator.sv" 32 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535903 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535903 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_s0_mm_interconnect_0.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_s0_mm_interconnect_0.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_s0_mm_interconnect_0 " "Found entity 1: ddr3controller_s0_mm_interconnect_0" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 9 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535905 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535905 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_write_decoder.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_write_decoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_write_decoder " "Found entity 1: rw_manager_write_decoder" {  } { { "ddr3controller/rw_manager_write_decoder.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_write_decoder.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535906 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535906 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_read_datapath.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_read_datapath.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_read_datapath " "Found entity 1: rw_manager_read_datapath" {  } { { "ddr3controller/rw_manager_read_datapath.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_read_datapath.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535906 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535906 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_ram_csr.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_ram_csr.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_ram_csr " "Found entity 1: rw_manager_ram_csr" {  } { { "ddr3controller/rw_manager_ram_csr.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ram_csr.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535907 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535907 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_ram.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_ram.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_ram " "Found entity 1: rw_manager_ram" {  } { { "ddr3controller/rw_manager_ram.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ram.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535907 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535907 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_pattern_fifo.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_pattern_fifo.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_pattern_fifo " "Found entity 1: rw_manager_pattern_fifo" {  } { { "ddr3controller/rw_manager_pattern_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_pattern_fifo.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535908 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535908 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_lfsr12.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_lfsr12.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_lfsr12 " "Found entity 1: rw_manager_lfsr12" {  } { { "ddr3controller/rw_manager_lfsr12.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_lfsr12.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535908 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535908 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_lfsr36.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_lfsr36.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_lfsr36 " "Found entity 1: rw_manager_lfsr36" {  } { { "ddr3controller/rw_manager_lfsr36.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_lfsr36.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535909 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535909 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_lfsr72.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_lfsr72.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_lfsr72 " "Found entity 1: rw_manager_lfsr72" {  } { { "ddr3controller/rw_manager_lfsr72.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_lfsr72.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535909 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535909 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_jumplogic.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_jumplogic.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_jumplogic " "Found entity 1: rw_manager_jumplogic" {  } { { "ddr3controller/rw_manager_jumplogic.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_jumplogic.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535910 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535910 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_inst_ROM_reg.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_inst_ROM_reg.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_inst_ROM_reg " "Found entity 1: rw_manager_inst_ROM_reg" {  } { { "ddr3controller/rw_manager_inst_ROM_reg.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_inst_ROM_reg.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535910 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535910 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_generic.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_generic.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_generic " "Found entity 1: rw_manager_generic" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535912 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535912 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_dm_decoder.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_dm_decoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_dm_decoder " "Found entity 1: rw_manager_dm_decoder" {  } { { "ddr3controller/rw_manager_dm_decoder.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_dm_decoder.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535912 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535912 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_di_buffer_wrap.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_di_buffer_wrap.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_di_buffer_wrap " "Found entity 1: rw_manager_di_buffer_wrap" {  } { { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535913 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535913 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_di_buffer.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_di_buffer.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_di_buffer " "Found entity 1: rw_manager_di_buffer" {  } { { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535913 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535913 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_datamux.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_datamux.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_datamux " "Found entity 1: rw_manager_datamux" {  } { { "ddr3controller/rw_manager_datamux.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_datamux.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535914 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535914 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_data_decoder.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_data_decoder.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_data_decoder " "Found entity 1: rw_manager_data_decoder" {  } { { "ddr3controller/rw_manager_data_decoder.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_data_decoder.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535914 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535914 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_data_broadcast.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_data_broadcast.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_data_broadcast " "Found entity 1: rw_manager_data_broadcast" {  } { { "ddr3controller/rw_manager_data_broadcast.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_data_broadcast.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535915 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535915 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "RATE rate rw_manager_core.sv(76) " "Verilog HDL Declaration information at rw_manager_core.sv(76): object \"RATE\" differs only in case from object \"rate\" in the same scope" {  } { { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 76 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535916 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_core.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_core.sv" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_core " "Found entity 1: rw_manager_core" {  } { { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535916 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535916 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_bitcheck.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_bitcheck.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_bitcheck " "Found entity 1: rw_manager_bitcheck" {  } { { "ddr3controller/rw_manager_bitcheck.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_bitcheck.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535917 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535917 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_ac_ROM_reg.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_ac_ROM_reg.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_ac_ROM_reg " "Found entity 1: rw_manager_ac_ROM_reg" {  } { { "ddr3controller/rw_manager_ac_ROM_reg.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ac_ROM_reg.v" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535917 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535917 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_ddr3.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_ddr3.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_ddr3 " "Found entity 1: rw_manager_ddr3" {  } { { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535918 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535918 ""}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "sequencer_phy_mgr.sv(398) " "Verilog HDL information at sequencer_phy_mgr.sv(398): always construct contains both blocking and non-blocking assignments" {  } { { "ddr3controller/sequencer_phy_mgr.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/sequencer_phy_mgr.sv" 398 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "Analysis & Synthesis" 0 -1 1613933535919 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/sequencer_phy_mgr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/sequencer_phy_mgr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer_phy_mgr " "Found entity 1: sequencer_phy_mgr" {  } { { "ddr3controller/sequencer_phy_mgr.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/sequencer_phy_mgr.sv" 73 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535919 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535919 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/sequencer_pll_mgr.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/sequencer_pll_mgr.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer_pll_mgr " "Found entity 1: sequencer_pll_mgr" {  } { { "ddr3controller/sequencer_pll_mgr.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/sequencer_pll_mgr.sv" 30 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535920 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535920 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/sequencer_m10.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/sequencer_m10.sv" { { "Info" "ISGN_ENTITY_NAME" "1 sequencer_m10 " "Found entity 1: sequencer_m10" {  } { { "ddr3controller/sequencer_m10.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/sequencer_m10.sv" 30 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535921 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535921 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/altera_mem_if_sequencer_rst.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/altera_mem_if_sequencer_rst.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altera_mem_if_sequencer_rst " "Found entity 1: altera_mem_if_sequencer_rst" {  } { { "ddr3controller/altera_mem_if_sequencer_rst.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_mem_if_sequencer_rst.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535922 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535922 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_m10_ac_ROM.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_m10_ac_ROM.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_m10_ac_ROM " "Found entity 1: rw_manager_m10_ac_ROM" {  } { { "ddr3controller/rw_manager_m10_ac_ROM.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_m10_ac_ROM.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535923 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535923 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/rw_manager_m10_inst_ROM.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/rw_manager_m10_inst_ROM.v" { { "Info" "ISGN_ENTITY_NAME" "1 rw_manager_m10_inst_ROM " "Found entity 1: rw_manager_m10_inst_ROM" {  } { { "ddr3controller/rw_manager_m10_inst_ROM.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_m10_inst_ROM.v" 2 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535923 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535923 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/afi_mux_ddr3_ddrx.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/afi_mux_ddr3_ddrx.v" { { "Info" "ISGN_ENTITY_NAME" "1 afi_mux_ddr3_ddrx " "Found entity 1: afi_mux_ddr3_ddrx" {  } { { "ddr3controller/afi_mux_ddr3_ddrx.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/afi_mux_ddr3_ddrx.v" 23 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535924 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535924 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_clock_pair_generator.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_clock_pair_generator.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_clock_pair_generator " "Found entity 1: ddr3controller_p0_clock_pair_generator" {  } { { "ddr3controller/ddr3controller_p0_clock_pair_generator.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_clock_pair_generator.v" 28 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535950 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535950 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_read_valid_selector.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_read_valid_selector.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_read_valid_selector " "Found entity 1: ddr3controller_p0_read_valid_selector" {  } { { "ddr3controller/ddr3controller_p0_read_valid_selector.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_read_valid_selector.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535951 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535951 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_addr_cmd_datapath.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_addr_cmd_datapath " "Found entity 1: ddr3controller_p0_addr_cmd_datapath" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535951 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535951 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_reset_m10.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_reset_m10.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_reset_m10 " "Found entity 1: ddr3controller_p0_reset_m10" {  } { { "ddr3controller/ddr3controller_p0_reset_m10.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_reset_m10.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535952 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535952 ""}
{ "Info" "IVRFX_L3_VERI_OBJ_DIFF_ONLY_IN_CASE" "INVERT_HR_CLOCK invert_hr_clock ddr3controller_p0_memphy_m10.sv(134) " "Verilog HDL Declaration information at ddr3controller_p0_memphy_m10.sv(134): object \"INVERT_HR_CLOCK\" differs only in case from object \"invert_hr_clock\" in the same scope" {  } { { "ddr3controller/ddr3controller_p0_memphy_m10.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_memphy_m10.sv" 134 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0 "Analysis & Synthesis" 0 -1 1613933535953 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_memphy_m10.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_memphy_m10.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_memphy_m10 " "Found entity 1: ddr3controller_p0_memphy_m10" {  } { { "ddr3controller/ddr3controller_p0_memphy_m10.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_memphy_m10.sv" 21 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535953 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535953 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_dqdqs_pads_m10 " "Found entity 1: ddr3controller_p0_dqdqs_pads_m10" {  } { { "ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv" 19 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535954 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535954 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_reset_sync.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_reset_sync.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_reset_sync " "Found entity 1: ddr3controller_p0_reset_sync" {  } { { "ddr3controller/ddr3controller_p0_reset_sync.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_reset_sync.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535954 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535954 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_fr_cycle_shifter.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_fr_cycle_shifter.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_fr_cycle_shifter " "Found entity 1: ddr3controller_p0_fr_cycle_shifter" {  } { { "ddr3controller/ddr3controller_p0_fr_cycle_shifter.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_fr_cycle_shifter.v" 37 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535955 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535955 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_read_datapath_m10.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_read_datapath_m10.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_read_datapath_m10 " "Found entity 1: ddr3controller_p0_read_datapath_m10" {  } { { "ddr3controller/ddr3controller_p0_read_datapath_m10.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_read_datapath_m10.sv" 25 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535956 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535956 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_write_datapath_m10.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_write_datapath_m10.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_write_datapath_m10 " "Found entity 1: ddr3controller_p0_write_datapath_m10" {  } { { "ddr3controller/ddr3controller_p0_write_datapath_m10.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_write_datapath_m10.v" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535956 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535956 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_simple_ddio_out_m10.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_simple_ddio_out_m10.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_simple_ddio_out_m10 " "Found entity 1: ddr3controller_p0_simple_ddio_out_m10" {  } { { "ddr3controller/ddr3controller_p0_simple_ddio_out_m10.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_simple_ddio_out_m10.sv" 35 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535957 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535957 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/max10emif_dcfifo.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/max10emif_dcfifo.sv" { { "Info" "ISGN_ENTITY_NAME" "1 max10emif_dcfifo " "Found entity 1: max10emif_dcfifo" {  } { { "ddr3controller/max10emif_dcfifo.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/max10emif_dcfifo.sv" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535957 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535957 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_iss_probe.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_iss_probe.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_iss_probe " "Found entity 1: ddr3controller_p0_iss_probe" {  } { { "ddr3controller/ddr3controller_p0_iss_probe.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_iss_probe.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535958 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535958 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v 2 2 " "Found 2 design units, including 2 entities, in source file ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_addr_cmd_pads_m10 " "Found entity 1: ddr3controller_p0_addr_cmd_pads_m10" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" 17 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535959 ""} { "Info" "ISGN_ENTITY_NAME" "2 addr_cmd_pad_m10 " "Found entity 2: addr_cmd_pad_m10" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" 418 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535959 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535959 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0_flop_mem.v 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0_flop_mem.v" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0_flop_mem " "Found entity 1: ddr3controller_p0_flop_mem" {  } { { "ddr3controller/ddr3controller_p0_flop_mem.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_flop_mem.v" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535960 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535960 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_p0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_p0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_p0 " "Found entity 1: ddr3controller_p0" {  } { { "ddr3controller/ddr3controller_p0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0.sv" 18 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535961 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535961 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/altera_gpio_lite.sv 2 2 " "Found 2 design units, including 2 entities, in source file ddr3controller/altera_gpio_lite.sv" { { "Info" "ISGN_ENTITY_NAME" "1 altgpio_one_bit " "Found entity 1: altgpio_one_bit" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 16 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535962 ""} { "Info" "ISGN_ENTITY_NAME" "2 altera_gpio_lite " "Found entity 2: altera_gpio_lite" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 940 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535962 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535962 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ddr3controller/ddr3controller_pll0.sv 1 1 " "Found 1 design units, including 1 entities, in source file ddr3controller/ddr3controller_pll0.sv" { { "Info" "ISGN_ENTITY_NAME" "1 ddr3controller_pll0 " "Found entity 1: ddr3controller_pll0" {  } { { "ddr3controller/ddr3controller_pll0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_pll0.sv" 22 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535963 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535963 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd 2 1 " "Found 2 design units, including 1 entities, in source file /home/mhu/projects/fpga/deca-ddr3-test/top.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 top-RTL " "Found design unit 1: top-RTL" {  } { { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 38 -1 0 } }  } 0 12022 "Found design unit %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535964 ""} { "Info" "ISGN_ENTITY_NAME" "1 top " "Found entity 1: top" {  } { { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 8 -1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933535964 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933535964 ""}
{ "Info" "ISGN_START_ELABORATION_TOP" "top " "Elaborating entity \"top\" for the top level hierarchy" {  } {  } 0 12127 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0 "Analysis & Synthesis" 0 -1 1613933536211 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "local_cal_fail top.vhd(54) " "Verilog HDL or VHDL warning at top.vhd(54): object \"local_cal_fail\" assigned a value but never read" {  } { { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 54 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536213 "|top"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "pll_locked top.vhd(55) " "Verilog HDL or VHDL warning at top.vhd(55): object \"pll_locked\" assigned a value but never read" {  } { { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 55 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536213 "|top"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller ddr3controller:ddr3controller_1 " "Elaborating entity \"ddr3controller\" for hierarchy \"ddr3controller:ddr3controller_1\"" {  } { { "../top.vhd" "ddr3controller_1" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536249 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_0002 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst " "Elaborating entity \"ddr3controller_0002\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\"" {  } { { "ddr3controller.vhd" "ddr3controller_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536253 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_pll0 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0 " "Elaborating entity \"ddr3controller_pll0\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\"" {  } { { "ddr3controller/ddr3controller_0002.v" "pll0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 159 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536257 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy " "Elaborating entity \"altpll\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\"" {  } { { "ddr3controller/ddr3controller_pll0.sv" "upll_memphy" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_pll0.sv" 140 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536288 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\"" {  } { { "ddr3controller/ddr3controller_pll0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_pll0.sv" 140 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536289 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "bandwidth_type AUTO " "Parameter \"bandwidth_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_divide_by 1 " "Parameter \"clk4_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_duty_cycle 50 " "Parameter \"clk4_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_multiply_by 3 " "Parameter \"clk4_multiply_by\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk4_phase_shift 0 " "Parameter \"clk4_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_divide_by 1 " "Parameter \"clk0_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_duty_cycle 50 " "Parameter \"clk0_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_multiply_by 6 " "Parameter \"clk0_multiply_by\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk0_phase_shift 0 " "Parameter \"clk0_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_divide_by 1 " "Parameter \"clk1_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_duty_cycle 50 " "Parameter \"clk1_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_multiply_by 6 " "Parameter \"clk1_multiply_by\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk1_phase_shift 2500 " "Parameter \"clk1_phase_shift\" = \"2500\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_divide_by 1 " "Parameter \"clk2_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_duty_cycle 50 " "Parameter \"clk2_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_multiply_by 6 " "Parameter \"clk2_multiply_by\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk2_phase_shift 0 " "Parameter \"clk2_phase_shift\" = \"0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_divide_by 1 " "Parameter \"clk3_divide_by\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_duty_cycle 50 " "Parameter \"clk3_duty_cycle\" = \"50\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_multiply_by 6 " "Parameter \"clk3_multiply_by\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clk3_phase_shift 2500 " "Parameter \"clk3_phase_shift\" = \"2500\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "compensate_clock CLK1 " "Parameter \"compensate_clock\" = \"CLK1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "inclk0_input_frequency 20000 " "Parameter \"inclk0_input_frequency\" = \"20000\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family MAX 10 " "Parameter \"intended_device_family\" = \"MAX 10\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altpll " "Parameter \"lpm_type\" = \"altpll\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode NORMAL " "Parameter \"operation_mode\" = \"NORMAL\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "pll_type AUTO " "Parameter \"pll_type\" = \"AUTO\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_activeclock PORT_UNUSED " "Parameter \"port_activeclock\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_areset PORT_USED " "Parameter \"port_areset\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad0 PORT_UNUSED " "Parameter \"port_clkbad0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkbad1 PORT_UNUSED " "Parameter \"port_clkbad1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkloss PORT_UNUSED " "Parameter \"port_clkloss\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkswitch PORT_UNUSED " "Parameter \"port_clkswitch\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_configupdate PORT_UNUSED " "Parameter \"port_configupdate\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_fbin PORT_UNUSED " "Parameter \"port_fbin\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk0 PORT_USED " "Parameter \"port_inclk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_inclk1 PORT_UNUSED " "Parameter \"port_inclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_locked PORT_USED " "Parameter \"port_locked\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pfdena PORT_UNUSED " "Parameter \"port_pfdena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasecounterselect PORT_USED " "Parameter \"port_phasecounterselect\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasedone PORT_USED " "Parameter \"port_phasedone\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phasestep PORT_USED " "Parameter \"port_phasestep\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_phaseupdown PORT_USED " "Parameter \"port_phaseupdown\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_pllena PORT_UNUSED " "Parameter \"port_pllena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanaclr PORT_UNUSED " "Parameter \"port_scanaclr\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclk PORT_USED " "Parameter \"port_scanclk\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanclkena PORT_UNUSED " "Parameter \"port_scanclkena\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandata PORT_UNUSED " "Parameter \"port_scandata\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandataout PORT_UNUSED " "Parameter \"port_scandataout\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scandone PORT_UNUSED " "Parameter \"port_scandone\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanread PORT_UNUSED " "Parameter \"port_scanread\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_scanwrite PORT_UNUSED " "Parameter \"port_scanwrite\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk0 PORT_USED " "Parameter \"port_clk0\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk1 PORT_USED " "Parameter \"port_clk1\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk2 PORT_USED " "Parameter \"port_clk2\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk3 PORT_USED " "Parameter \"port_clk3\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk4 PORT_USED " "Parameter \"port_clk4\" = \"PORT_USED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clk5 PORT_UNUSED " "Parameter \"port_clk5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena0 PORT_UNUSED " "Parameter \"port_clkena0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena1 PORT_UNUSED " "Parameter \"port_clkena1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena2 PORT_UNUSED " "Parameter \"port_clkena2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena3 PORT_UNUSED " "Parameter \"port_clkena3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena4 PORT_UNUSED " "Parameter \"port_clkena4\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_clkena5 PORT_UNUSED " "Parameter \"port_clkena5\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk0 PORT_UNUSED " "Parameter \"port_extclk0\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk1 PORT_UNUSED " "Parameter \"port_extclk1\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk2 PORT_UNUSED " "Parameter \"port_extclk2\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "port_extclk3 PORT_UNUSED " "Parameter \"port_extclk3\" = \"PORT_UNUSED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "self_reset_on_loss_lock OFF " "Parameter \"self_reset_on_loss_lock\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "vco_frequency_control MANUAL_PHASE " "Parameter \"vco_frequency_control\" = \"MANUAL_PHASE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "vco_phase_shift_step 104 " "Parameter \"vco_phase_shift_step\" = \"104\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_clock 5 " "Parameter \"width_clock\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_phasecounterselect 3 " "Parameter \"width_phasecounterselect\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536290 ""}  } { { "ddr3controller/ddr3controller_pll0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_pll0.sv" 140 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933536290 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_t0j3.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_t0j3.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_t0j3 " "Found entity 1: altpll_t0j3" {  } { { "db/altpll_t0j3.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 39 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536319 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536319 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_t0j3 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated " "Elaborating entity \"altpll_t0j3\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\"" {  } { { "altpll.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536320 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_dyn_phase_le_qrn.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_dyn_phase_le_qrn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_dyn_phase_le_qrn " "Found entity 1: altpll_dyn_phase_le_qrn" {  } { { "db/altpll_dyn_phase_le_qrn.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_dyn_phase_le_qrn.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536324 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536324 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_dyn_phase_le_qrn ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_qrn:altpll_dyn_phase_le2 " "Elaborating entity \"altpll_dyn_phase_le_qrn\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_qrn:altpll_dyn_phase_le2\"" {  } { { "db/altpll_t0j3.tdf" "altpll_dyn_phase_le2" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 52 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536325 ""}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "datad " "Variable or input pin \"datad\" is defined but never used." {  } { { "db/altpll_dyn_phase_le_qrn.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_dyn_phase_le_qrn.tdf" 33 2 0 } } { "db/altpll_t0j3.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 52 2 0 } } { "altpll.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } { "ddr3controller/ddr3controller_pll0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_pll0.sv" 140 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 159 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 104 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 85 0 0 } }  } 0 287013 "Variable or input pin \"%1!s!\" is defined but never used." 0 0 "Analysis & Synthesis" 0 -1 1613933536325 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_pll0:pll0|altpll:upll_memphy|altpll_t0j3:auto_generated|altpll_dyn_phase_le_qrn:altpll_dyn_phase_le2"}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_dyn_phase_le_rrn.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_dyn_phase_le_rrn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_dyn_phase_le_rrn " "Found entity 1: altpll_dyn_phase_le_rrn" {  } { { "db/altpll_dyn_phase_le_rrn.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_dyn_phase_le_rrn.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536329 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536329 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_dyn_phase_le_rrn ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_rrn:altpll_dyn_phase_le4 " "Elaborating entity \"altpll_dyn_phase_le_rrn\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_rrn:altpll_dyn_phase_le4\"" {  } { { "db/altpll_t0j3.tdf" "altpll_dyn_phase_le4" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 53 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536330 ""}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "datad " "Variable or input pin \"datad\" is defined but never used." {  } { { "db/altpll_dyn_phase_le_rrn.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_dyn_phase_le_rrn.tdf" 33 2 0 } } { "db/altpll_t0j3.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 53 2 0 } } { "altpll.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } { "ddr3controller/ddr3controller_pll0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_pll0.sv" 140 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 159 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 104 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 85 0 0 } }  } 0 287013 "Variable or input pin \"%1!s!\" is defined but never used." 0 0 "Analysis & Synthesis" 0 -1 1613933536330 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_pll0:pll0|altpll:upll_memphy|altpll_t0j3:auto_generated|altpll_dyn_phase_le_rrn:altpll_dyn_phase_le4"}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altpll_dyn_phase_le_srn.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altpll_dyn_phase_le_srn.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altpll_dyn_phase_le_srn " "Found entity 1: altpll_dyn_phase_le_srn" {  } { { "db/altpll_dyn_phase_le_srn.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_dyn_phase_le_srn.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536334 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536334 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altpll_dyn_phase_le_srn ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_srn:altpll_dyn_phase_le5 " "Elaborating entity \"altpll_dyn_phase_le_srn\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_srn:altpll_dyn_phase_le5\"" {  } { { "db/altpll_t0j3.tdf" "altpll_dyn_phase_le5" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 54 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536335 ""}
{ "Warning" "WTDFX_UNREFERENCED_NODE" "datad " "Variable or input pin \"datad\" is defined but never used." {  } { { "db/altpll_dyn_phase_le_srn.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_dyn_phase_le_srn.tdf" 33 2 0 } } { "db/altpll_t0j3.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 54 2 0 } } { "altpll.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altpll.tdf" 897 3 0 } } { "ddr3controller/ddr3controller_pll0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_pll0.sv" 140 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 159 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 104 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 85 0 0 } }  } 0 287013 "Variable or input pin \"%1!s!\" is defined but never used." 0 0 "Analysis & Synthesis" 0 -1 1613933536335 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_pll0:pll0|altpll:upll_memphy|altpll_t0j3:auto_generated|altpll_dyn_phase_le_srn:altpll_dyn_phase_le5"}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_ocd.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_ocd.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_ocd " "Found entity 1: cntr_ocd" {  } { { "db/cntr_ocd.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_ocd.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536362 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536362 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_ocd ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|cntr_ocd:phasestep_counter " "Elaborating entity \"cntr_ocd\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|cntr_ocd:phasestep_counter\"" {  } { { "db/altpll_t0j3.tdf" "phasestep_counter" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 60 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536363 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_erb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_erb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_erb " "Found entity 1: cmpr_erb" {  } { { "db/cmpr_erb.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cmpr_erb.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536389 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536389 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_erb ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|cntr_ocd:phasestep_counter\|cmpr_erb:cmpr12 " "Elaborating entity \"cmpr_erb\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|cntr_ocd:phasestep_counter\|cmpr_erb:cmpr12\"" {  } { { "db/cntr_ocd.tdf" "cmpr12" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_ocd.tdf" 37 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536390 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_uqd.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_uqd.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_uqd " "Found entity 1: cntr_uqd" {  } { { "db/cntr_uqd.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_uqd.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536418 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536418 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_uqd ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|cntr_uqd:pll_internal_phasestep " "Elaborating entity \"cntr_uqd\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|cntr_uqd:pll_internal_phasestep\"" {  } { { "db/altpll_t0j3.tdf" "pll_internal_phasestep" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 61 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536419 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_frb.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_frb.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_frb " "Found entity 1: cmpr_frb" {  } { { "db/cmpr_frb.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cmpr_frb.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536445 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536445 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_frb ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|cntr_uqd:pll_internal_phasestep\|cmpr_frb:cmpr14 " "Elaborating entity \"cmpr_frb\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|cntr_uqd:pll_internal_phasestep\|cmpr_frb:cmpr14\"" {  } { { "db/cntr_uqd.tdf" "cmpr14" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_uqd.tdf" 38 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536446 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0 " "Elaborating entity \"ddr3controller_p0\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\"" {  } { { "ddr3controller/ddr3controller_0002.v" "p0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 234 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536450 ""}
{ "Info" "IVRFX_VERI_DISPLAY_SYSTEM_CALL_INFO" "Using Regular core emif simulation models ddr3controller_p0.sv(339) " "Verilog HDL Display System Task info at ddr3controller_p0.sv(339): Using Regular core emif simulation models" {  } { { "ddr3controller/ddr3controller_p0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0.sv" 339 0 0 } }  } 0 10648 "Verilog HDL Display System Task info at %2!s!: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536451 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0"}
{ "Warning" "WVRFX_L2_VDB_DRIVERLESS_OUTPUT_PORT" "phy_read_fifo_q ddr3controller_p0.sv(331) " "Output port \"phy_read_fifo_q\" at ddr3controller_p0.sv(331) has no driver" {  } { { "ddr3controller/ddr3controller_p0.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0.sv" 331 0 0 } }  } 0 10034 "Output port \"%1!s!\" at %2!s! has no driver" 0 0 "Analysis & Synthesis" 0 -1 1613933536451 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_memphy_m10 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy " "Elaborating entity \"ddr3controller_p0_memphy_m10\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\"" {  } { { "ddr3controller/ddr3controller_p0.sv" "umemphy" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0.sv" 445 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536452 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_reset_m10 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_reset_m10:ureset " "Elaborating entity \"ddr3controller_p0_reset_m10\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_reset_m10:ureset\"" {  } { { "ddr3controller/ddr3controller_p0_memphy_m10.sv" "ureset" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_memphy_m10.sv" 302 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536455 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_reset_sync ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_reset_m10:ureset\|ddr3controller_p0_reset_sync:ureset_afi_clk " "Elaborating entity \"ddr3controller_p0_reset_sync\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_reset_m10:ureset\|ddr3controller_p0_reset_sync:ureset_afi_clk\"" {  } { { "ddr3controller/ddr3controller_p0_reset_m10.v" "ureset_afi_clk" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_reset_m10.v" 60 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536456 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_reset_sync ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_reset_m10:ureset\|ddr3controller_p0_reset_sync:ureset_ctl_reset_clk " "Elaborating entity \"ddr3controller_p0_reset_sync\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_reset_m10:ureset\|ddr3controller_p0_reset_sync:ureset_ctl_reset_clk\"" {  } { { "ddr3controller/ddr3controller_p0_reset_m10.v" "ureset_ctl_reset_clk" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_reset_m10.v" 68 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536458 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_reset_sync ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_reset_m10:ureset\|ddr3controller_p0_reset_sync:ureset_resync_clk " "Elaborating entity \"ddr3controller_p0_reset_sync\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_reset_m10:ureset\|ddr3controller_p0_reset_sync:ureset_resync_clk\"" {  } { { "ddr3controller/ddr3controller_p0_reset_m10.v" "ureset_resync_clk" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_reset_m10.v" 77 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536459 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_addr_cmd_datapath ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath " "Elaborating entity \"ddr3controller_p0_addr_cmd_datapath\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath\"" {  } { { "ddr3controller/ddr3controller_p0_memphy_m10.sv" "uaddr_cmd_datapath" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_memphy_m10.sv" 340 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536461 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_fr_cycle_shifter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath\|ddr3controller_p0_fr_cycle_shifter:uaddr_cmd_shift_address " "Elaborating entity \"ddr3controller_p0_fr_cycle_shifter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath\|ddr3controller_p0_fr_cycle_shifter:uaddr_cmd_shift_address\"" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" "uaddr_cmd_shift_address" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" 127 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536462 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_fr_cycle_shifter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath\|ddr3controller_p0_fr_cycle_shifter:uaddr_cmd_shift_bank " "Elaborating entity \"ddr3controller_p0_fr_cycle_shifter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath\|ddr3controller_p0_fr_cycle_shifter:uaddr_cmd_shift_bank\"" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" "uaddr_cmd_shift_bank" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" 140 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536464 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_fr_cycle_shifter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath\|ddr3controller_p0_fr_cycle_shifter:uaddr_cmd_shift_cke " "Elaborating entity \"ddr3controller_p0_fr_cycle_shifter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath\|ddr3controller_p0_fr_cycle_shifter:uaddr_cmd_shift_cke\"" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" "uaddr_cmd_shift_cke" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" 150 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536465 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_fr_cycle_shifter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath\|ddr3controller_p0_fr_cycle_shifter:uaddr_cmd_shift_cs_n " "Elaborating entity \"ddr3controller_p0_fr_cycle_shifter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_datapath:uaddr_cmd_datapath\|ddr3controller_p0_fr_cycle_shifter:uaddr_cmd_shift_cs_n\"" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" "uaddr_cmd_shift_cs_n" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_datapath.v" 160 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536466 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_write_datapath_m10 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_write_datapath_m10:uwrite_datapath " "Elaborating entity \"ddr3controller_p0_write_datapath_m10\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_write_datapath_m10:uwrite_datapath\"" {  } { { "ddr3controller/ddr3controller_p0_memphy_m10.sv" "uwrite_datapath" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_memphy_m10.sv" 379 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536471 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_fr_cycle_shifter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_write_datapath_m10:uwrite_datapath\|ddr3controller_p0_fr_cycle_shifter:bs_wr_grp\[0\].dq_shifter " "Elaborating entity \"ddr3controller_p0_fr_cycle_shifter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_write_datapath_m10:uwrite_datapath\|ddr3controller_p0_fr_cycle_shifter:bs_wr_grp\[0\].dq_shifter\"" {  } { { "ddr3controller/ddr3controller_p0_write_datapath_m10.v" "bs_wr_grp\[0\].dq_shifter" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_write_datapath_m10.v" 138 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536473 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_fr_cycle_shifter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_write_datapath_m10:uwrite_datapath\|ddr3controller_p0_fr_cycle_shifter:bs_wr_grp\[0\].wrdata_mask_shifter " "Elaborating entity \"ddr3controller_p0_fr_cycle_shifter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_write_datapath_m10:uwrite_datapath\|ddr3controller_p0_fr_cycle_shifter:bs_wr_grp\[0\].wrdata_mask_shifter\"" {  } { { "ddr3controller/ddr3controller_p0_write_datapath_m10.v" "bs_wr_grp\[0\].wrdata_mask_shifter" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_write_datapath_m10.v" 147 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536475 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_fr_cycle_shifter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_write_datapath_m10:uwrite_datapath\|ddr3controller_p0_fr_cycle_shifter:bs_wr_grp\[0\].wrdata_en_shifter " "Elaborating entity \"ddr3controller_p0_fr_cycle_shifter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_write_datapath_m10:uwrite_datapath\|ddr3controller_p0_fr_cycle_shifter:bs_wr_grp\[0\].wrdata_en_shifter\"" {  } { { "ddr3controller/ddr3controller_p0_write_datapath_m10.v" "bs_wr_grp\[0\].wrdata_en_shifter" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_write_datapath_m10.v" 156 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536476 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_read_datapath_m10 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_read_datapath_m10:uread_datapath " "Elaborating entity \"ddr3controller_p0_read_datapath_m10\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_read_datapath_m10:uread_datapath\"" {  } { { "ddr3controller/ddr3controller_p0_memphy_m10.sv" "uread_datapath" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_memphy_m10.sv" 411 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536481 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "4 2 ddr3controller_p0_read_datapath_m10.sv(184) " "Verilog HDL assignment warning at ddr3controller_p0_read_datapath_m10.sv(184): truncated value with size 4 to match size of target (2)" {  } { { "ddr3controller/ddr3controller_p0_read_datapath_m10.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_read_datapath_m10.sv" 184 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1613933536482 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_read_datapath_m10:uread_datapath"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "max10emif_dcfifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_read_datapath_m10:uread_datapath\|max10emif_dcfifo:rdata_fifo " "Elaborating entity \"max10emif_dcfifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_read_datapath_m10:uread_datapath\|max10emif_dcfifo:rdata_fifo\"" {  } { { "ddr3controller/ddr3controller_p0_read_datapath_m10.sv" "rdata_fifo" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_read_datapath_m10.sv" 164 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536483 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_addr_cmd_pads_m10 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads " "Elaborating entity \"ddr3controller_p0_addr_cmd_pads_m10\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\"" {  } { { "ddr3controller/ddr3controller_p0_memphy_m10.sv" "uaddr_cmd_pads" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_memphy_m10.sv" 470 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536485 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "addr_cmd_pad_m10 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|addr_cmd_pad_m10:address_gen\[0\].uaddress_pad " "Elaborating entity \"addr_cmd_pad_m10\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|addr_cmd_pad_m10:address_gen\[0\].uaddress_pad\"" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" "address_gen\[0\].uaddress_pad" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536487 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_simple_ddio_out_m10 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|addr_cmd_pad_m10:address_gen\[0\].uaddress_pad\|ddr3controller_p0_simple_ddio_out_m10:hr_to_fr_lo " "Elaborating entity \"ddr3controller_p0_simple_ddio_out_m10\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|addr_cmd_pad_m10:address_gen\[0\].uaddress_pad\|ddr3controller_p0_simple_ddio_out_m10:hr_to_fr_lo\"" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" "hr_to_fr_lo" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" 454 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536488 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_gpio_lite ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|addr_cmd_pad_m10:address_gen\[0\].uaddress_pad\|altera_gpio_lite:uadc_pad " "Elaborating entity \"altera_gpio_lite\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|addr_cmd_pad_m10:address_gen\[0\].uaddress_pad\|altera_gpio_lite:uadc_pad\"" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" "uadc_pad" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" 510 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536490 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altgpio_one_bit ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|addr_cmd_pad_m10:address_gen\[0\].uaddress_pad\|altera_gpio_lite:uadc_pad\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i " "Elaborating entity \"altgpio_one_bit\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|addr_cmd_pad_m10:address_gen\[0\].uaddress_pad\|altera_gpio_lite:uadc_pad\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i\"" {  } { { "ddr3controller/altera_gpio_lite.sv" "gpio_one_bit.i_loop\[0\].altgpio_bit_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 1115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536491 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "nsleep_in altera_gpio_lite.sv(82) " "Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object \"nsleep_in\" assigned a value but never read" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 82 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536492 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads|addr_cmd_pad_m10:address_gen[0].uaddress_pad|altera_gpio_lite:uadc_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "oe_outclocken_wire altera_gpio_lite.sv(334) " "Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object \"oe_outclocken_wire\" assigned a value but never read" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 334 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536492 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads|addr_cmd_pad_m10:address_gen[0].uaddress_pad|altera_gpio_lite:uadc_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_gpio_lite ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|altera_gpio_lite:clock_gen\[0\].umem_ck_pad " "Elaborating entity \"altera_gpio_lite\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|altera_gpio_lite:clock_gen\[0\].umem_ck_pad\"" {  } { { "ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" "clock_gen\[0\].umem_ck_pad" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_addr_cmd_pads_m10.v" 411 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536603 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altgpio_one_bit ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|altera_gpio_lite:clock_gen\[0\].umem_ck_pad\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i " "Elaborating entity \"altgpio_one_bit\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads\|altera_gpio_lite:clock_gen\[0\].umem_ck_pad\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i\"" {  } { { "ddr3controller/altera_gpio_lite.sv" "gpio_one_bit.i_loop\[0\].altgpio_bit_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 1115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536604 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "nsleep_in altera_gpio_lite.sv(82) " "Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object \"nsleep_in\" assigned a value but never read" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 82 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536605 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads|altera_gpio_lite:clock_gen[0].umem_ck_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "oe_outclocken_wire altera_gpio_lite.sv(334) " "Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object \"oe_outclocken_wire\" assigned a value but never read" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 334 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536605 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads|altera_gpio_lite:clock_gen[0].umem_ck_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "ddr_input altera_gpio_lite.sv(525) " "Verilog HDL warning at altera_gpio_lite.sv(525): object ddr_input used but never assigned" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 525 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1613933536605 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads|altera_gpio_lite:clock_gen[0].umem_ck_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "inclock_wire altera_gpio_lite.sv(526) " "Verilog HDL or VHDL warning at altera_gpio_lite.sv(526): object \"inclock_wire\" assigned a value but never read" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 526 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536605 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads|altera_gpio_lite:clock_gen[0].umem_ck_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "inclocken_wire altera_gpio_lite.sv(540) " "Verilog HDL or VHDL warning at altera_gpio_lite.sv(540): object \"inclocken_wire\" assigned a value but never read" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 540 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536605 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads|altera_gpio_lite:clock_gen[0].umem_ck_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "ddr_input 0 altera_gpio_lite.sv(525) " "Net \"ddr_input\" at altera_gpio_lite.sv(525) has no driver or initial value, using a default initial value '0'" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 525 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1613933536605 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_addr_cmd_pads_m10:uaddr_cmd_pads|altera_gpio_lite:clock_gen[0].umem_ck_pad|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_p0_dqdqs_pads_m10 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs " "Elaborating entity \"ddr3controller_p0_dqdqs_pads_m10\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\"" {  } { { "ddr3controller/ddr3controller_p0_memphy_m10.sv" "dq_ddio\[0\].ubidir_dq_dqs" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_memphy_m10.sv" 552 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536607 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_gpio_lite ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:dq_ddio_io " "Elaborating entity \"altera_gpio_lite\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:dq_ddio_io\"" {  } { { "ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv" "dq_ddio_io" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv" 244 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536628 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altgpio_one_bit ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:dq_ddio_io\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i " "Elaborating entity \"altgpio_one_bit\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:dq_ddio_io\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i\"" {  } { { "ddr3controller/altera_gpio_lite.sv" "gpio_one_bit.i_loop\[0\].altgpio_bit_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 1115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536631 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_gpio_lite ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:dqs_ddio_io " "Elaborating entity \"altera_gpio_lite\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:dqs_ddio_io\"" {  } { { "ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv" "dqs_ddio_io" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv" 330 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536641 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altgpio_one_bit ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:dqs_ddio_io\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i " "Elaborating entity \"altgpio_one_bit\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:dqs_ddio_io\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i\"" {  } { { "ddr3controller/altera_gpio_lite.sv" "gpio_one_bit.i_loop\[0\].altgpio_bit_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 1115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536643 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_gpio_lite ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:extra_ddio_out " "Elaborating entity \"altera_gpio_lite\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:extra_ddio_out\"" {  } { { "ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv" "extra_ddio_out" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_p0_dqdqs_pads_m10.sv" 412 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536647 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altgpio_one_bit ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:extra_ddio_out\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i " "Elaborating entity \"altgpio_one_bit\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_dqdqs_pads_m10:dq_ddio\[0\].ubidir_dq_dqs\|altera_gpio_lite:extra_ddio_out\|altgpio_one_bit:gpio_one_bit.i_loop\[0\].altgpio_bit_i\"" {  } { { "ddr3controller/altera_gpio_lite.sv" "gpio_one_bit.i_loop\[0\].altgpio_bit_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 1115 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536649 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "nsleep_in altera_gpio_lite.sv(82) " "Verilog HDL or VHDL warning at altera_gpio_lite.sv(82): object \"nsleep_in\" assigned a value but never read" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 82 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536649 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_dqdqs_pads_m10:dq_ddio[0].ubidir_dq_dqs|altera_gpio_lite:extra_ddio_out|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "oe_outclocken_wire altera_gpio_lite.sv(334) " "Verilog HDL or VHDL warning at altera_gpio_lite.sv(334): object \"oe_outclocken_wire\" assigned a value but never read" {  } { { "ddr3controller/altera_gpio_lite.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_gpio_lite.sv" 334 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536649 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_p0:p0|ddr3controller_p0_memphy_m10:umemphy|ddr3controller_p0_dqdqs_pads_m10:dq_ddio[0].ubidir_dq_dqs|altera_gpio_lite:extra_ddio_out|altgpio_one_bit:gpio_one_bit.i_loop[0].altgpio_bit_i"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "afi_mux_ddr3_ddrx ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|afi_mux_ddr3_ddrx:m0 " "Elaborating entity \"afi_mux_ddr3_ddrx\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|afi_mux_ddr3_ddrx:m0\"" {  } { { "ddr3controller/ddr3controller_0002.v" "m0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 314 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536686 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0 " "Elaborating entity \"ddr3controller_s0\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\"" {  } { { "ddr3controller/ddr3controller_0002.v" "s0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536690 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_mem_if_sequencer_rst ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|altera_mem_if_sequencer_rst:sequencer_rst " "Elaborating entity \"altera_mem_if_sequencer_rst\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|altera_mem_if_sequencer_rst:sequencer_rst\"" {  } { { "ddr3controller/ddr3controller_s0.v" "sequencer_rst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 96 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536692 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer_m10 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|sequencer_m10:cpu_inst " "Elaborating entity \"sequencer_m10\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|sequencer_m10:cpu_inst\"" {  } { { "ddr3controller/ddr3controller_s0.v" "cpu_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 120 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536694 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "start_ddr2_init sequencer_m10.sv(128) " "Verilog HDL or VHDL warning at sequencer_m10.sv(128): object \"start_ddr2_init\" assigned a value but never read" {  } { { "ddr3controller/sequencer_m10.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/sequencer_m10.sv" 128 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536699 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|sequencer_m10:cpu_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "start_lpddr2_init sequencer_m10.sv(130) " "Verilog HDL or VHDL warning at sequencer_m10.sv(130): object \"start_lpddr2_init\" assigned a value but never read" {  } { { "ddr3controller/sequencer_m10.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/sequencer_m10.sv" 130 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536699 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|sequencer_m10:cpu_inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer_pll_mgr ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|sequencer_pll_mgr:sequencer_pll_mgr_inst " "Elaborating entity \"sequencer_pll_mgr\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|sequencer_pll_mgr:sequencer_pll_mgr_inst\"" {  } { { "ddr3controller/ddr3controller_s0.v" "sequencer_pll_mgr_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 141 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536700 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "sequencer_phy_mgr ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|sequencer_phy_mgr:sequencer_phy_mgr_inst " "Elaborating entity \"sequencer_phy_mgr\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|sequencer_phy_mgr:sequencer_phy_mgr_inst\"" {  } { { "ddr3controller/ddr3controller_s0.v" "sequencer_phy_mgr_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 190 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536702 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_ddr3 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst " "Elaborating entity \"rw_manager_ddr3\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\"" {  } { { "ddr3controller/ddr3controller_s0.v" "sequencer_rw_mgr_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536705 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_generic ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst " "Elaborating entity \"rw_manager_generic\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\"" {  } { { "ddr3controller/rw_manager_ddr3.v" "rw_mgr_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536706 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "jump_ptr_0_reg rw_manager_generic.sv(155) " "Verilog HDL or VHDL warning at rw_manager_generic.sv(155): object \"jump_ptr_0_reg\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 155 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536708 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "jump_ptr_1_reg rw_manager_generic.sv(156) " "Verilog HDL or VHDL warning at rw_manager_generic.sv(156): object \"jump_ptr_1_reg\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 156 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536708 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "jump_cntr_0_reg rw_manager_generic.sv(157) " "Verilog HDL or VHDL warning at rw_manager_generic.sv(157): object \"jump_cntr_0_reg\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 157 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536708 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "jump_cntr_1_reg rw_manager_generic.sv(158) " "Verilog HDL or VHDL warning at rw_manager_generic.sv(158): object \"jump_cntr_1_reg\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 158 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536708 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "cs_mask_reg rw_manager_generic.sv(159) " "Verilog HDL or VHDL warning at rw_manager_generic.sv(159): object \"cs_mask_reg\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 159 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536708 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "all_refresh_done rw_manager_generic.sv(163) " "Verilog HDL warning at rw_manager_generic.sv(163): object all_refresh_done used but never assigned" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 163 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1613933536708 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst"}
{ "Warning" "WVRFX_VERI_2106_UNCONVERTED" "restore_done rw_manager_generic.sv(164) " "Verilog HDL warning at rw_manager_generic.sv(164): object restore_done used but never assigned" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 164 0 0 } }  } 0 10858 "Verilog HDL warning at %2!s!: object %1!s! used but never assigned" 0 0 "Analysis & Synthesis" 0 -1 1613933536708 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "all_refresh_done 0 rw_manager_generic.sv(163) " "Net \"all_refresh_done\" at rw_manager_generic.sv(163) has no driver or initial value, using a default initial value '0'" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 163 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1613933536708 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst"}
{ "Warning" "WVRFX_VDB_DRIVERLESS_NET" "restore_done 0 rw_manager_generic.sv(164) " "Net \"restore_done\" at rw_manager_generic.sv(164) has no driver or initial value, using a default initial value '0'" {  } { { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 164 0 0 } }  } 0 10030 "Net \"%1!s!\" at %3!s! has no driver or initial value, using a default initial value '%2!c!'" 0 0 "Analysis & Synthesis" 0 -1 1613933536708 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_core ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst " "Elaborating entity \"rw_manager_core\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\"" {  } { { "ddr3controller/rw_manager_generic.sv" "rw_mgr_core_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536709 ""}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "inst_ROM_wrdata rw_manager_core.sv(192) " "Verilog HDL or VHDL warning at rw_manager_core.sv(192): object \"inst_ROM_wrdata\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 192 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536711 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "inst_ROM_wraddress rw_manager_core.sv(193) " "Verilog HDL or VHDL warning at rw_manager_core.sv(193): object \"inst_ROM_wraddress\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 193 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536711 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ac_ROM_wrdata_to_rom rw_manager_core.sv(194) " "Verilog HDL or VHDL warning at rw_manager_core.sv(194): object \"ac_ROM_wrdata_to_rom\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 194 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536711 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ac_ROM_wraddress rw_manager_core.sv(196) " "Verilog HDL or VHDL warning at rw_manager_core.sv(196): object \"ac_ROM_wraddress\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 196 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536711 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "inst_ROM_wren rw_manager_core.sv(323) " "Verilog HDL or VHDL warning at rw_manager_core.sv(323): object \"inst_ROM_wren\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 323 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536711 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst"}
{ "Warning" "WVRFX_L2_HDL_OBJECT_ASSIGNED_NOT_READ" "ac_ROM_wren rw_manager_core.sv(324) " "Verilog HDL or VHDL warning at rw_manager_core.sv(324): object \"ac_ROM_wren\" assigned a value but never read" {  } { { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 324 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0 "Analysis & Synthesis" 0 -1 1613933536711 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_m10_inst_ROM ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_m10_inst_ROM:inst_ROM_i " "Elaborating entity \"rw_manager_m10_inst_ROM\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_m10_inst_ROM:inst_ROM_i\"" {  } { { "ddr3controller/rw_manager_core.sv" "inst_ROM_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 411 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536712 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_m10_ac_ROM ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_m10_ac_ROM:ac_ROM_i " "Elaborating entity \"rw_manager_m10_ac_ROM\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_m10_ac_ROM:ac_ROM_i\"" {  } { { "ddr3controller/rw_manager_core.sv" "ac_ROM_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 452 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536713 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_di_buffer_wrap ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i " "Elaborating entity \"rw_manager_di_buffer_wrap\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\"" {  } { { "ddr3controller/rw_manager_core.sv" "di_buffer_wrap_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536715 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_di_buffer ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i " "Elaborating entity \"rw_manager_di_buffer\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\"" {  } { { "ddr3controller/rw_manager_di_buffer_wrap.v" "rw_manager_di_buffer_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536716 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/rw_manager_di_buffer.v" "altsyncram_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536735 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536736 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix III " "Parameter \"intended_device_family\" = \"Stratix III\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 4 " "Parameter \"numwords_a\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 4 " "Parameter \"numwords_b\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type MLAB " "Parameter \"ram_block_type\" = \"MLAB\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 2 " "Parameter \"widthad_a\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 2 " "Parameter \"widthad_b\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 32 " "Parameter \"width_a\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 32 " "Parameter \"width_b\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536736 ""}  } { { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933536736 ""}
{ "Warning" "WTDFX_ASSERTION" "Device family MAX10 does not have MLAB blocks -- using available memory blocks " "Assertion warning: Device family MAX10 does not have MLAB blocks -- using available memory blocks" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 1075 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536767 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_uok1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_uok1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_uok1 " "Found entity 1: altsyncram_uok1" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536767 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536767 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_uok1 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated " "Elaborating entity \"altsyncram_uok1\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536768 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_write_decoder ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i " "Elaborating entity \"rw_manager_write_decoder\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i\"" {  } { { "ddr3controller/rw_manager_core.sv" "write_decoder_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 502 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536773 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_data_decoder ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i\|rw_manager_data_decoder:DO_decoder " "Elaborating entity \"rw_manager_data_decoder\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i\|rw_manager_data_decoder:DO_decoder\"" {  } { { "ddr3controller/rw_manager_write_decoder.v" "DO_decoder" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_write_decoder.v" 59 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536774 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_dm_decoder ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i\|rw_manager_dm_decoder:DM_decoder_i " "Elaborating entity \"rw_manager_dm_decoder\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i\|rw_manager_dm_decoder:DM_decoder_i\"" {  } { { "ddr3controller/rw_manager_write_decoder.v" "DM_decoder_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_write_decoder.v" 68 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536776 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_lfsr36 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i\|rw_manager_lfsr36:do_lfsr_i " "Elaborating entity \"rw_manager_lfsr36\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i\|rw_manager_lfsr36:do_lfsr_i\"" {  } { { "ddr3controller/rw_manager_write_decoder.v" "do_lfsr_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_write_decoder.v" 86 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536777 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_lfsr12 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i\|rw_manager_lfsr12:dm_lfsr_i " "Elaborating entity \"rw_manager_lfsr12\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_write_decoder:write_decoder_i\|rw_manager_lfsr12:dm_lfsr_i\"" {  } { { "ddr3controller/rw_manager_write_decoder.v" "dm_lfsr_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_write_decoder.v" 96 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536779 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_read_datapath ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i " "Elaborating entity \"rw_manager_read_datapath\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\"" {  } { { "ddr3controller/rw_manager_core.sv" "read_datapath_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 524 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536780 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_bitcheck ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_bitcheck:bitcheck_i " "Elaborating entity \"rw_manager_bitcheck\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_bitcheck:bitcheck_i\"" {  } { { "ddr3controller/rw_manager_read_datapath.v" "bitcheck_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_read_datapath.v" 107 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536782 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_pattern_fifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i " "Elaborating entity \"rw_manager_pattern_fifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i\"" {  } { { "ddr3controller/rw_manager_read_datapath.v" "pattern_fifo_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_read_datapath.v" 133 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536788 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/rw_manager_pattern_fifo.v" "altsyncram_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_pattern_fifo.v" 71 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536793 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/rw_manager_pattern_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_pattern_fifo.v" 71 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536794 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i\|altsyncram:altsyncram_component " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_a BYPASS " "Parameter \"clock_enable_input_a\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_input_b BYPASS " "Parameter \"clock_enable_input_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "clock_enable_output_b BYPASS " "Parameter \"clock_enable_output_b\" = \"BYPASS\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix IV " "Parameter \"intended_device_family\" = \"Stratix IV\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 32 " "Parameter \"numwords_a\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 32 " "Parameter \"numwords_b\" = \"32\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "ram_block_type MLAB " "Parameter \"ram_block_type\" = \"MLAB\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 5 " "Parameter \"widthad_a\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 5 " "Parameter \"widthad_b\" = \"5\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 9 " "Parameter \"width_a\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 9 " "Parameter \"width_b\" = \"9\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536794 ""}  } { { "ddr3controller/rw_manager_pattern_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_pattern_fifo.v" 71 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933536794 ""}
{ "Warning" "WTDFX_ASSERTION" "Device family MAX10 does not have MLAB blocks -- using available memory blocks " "Assertion warning: Device family MAX10 does not have MLAB blocks -- using available memory blocks" {  } { { "db/altsyncram_epk1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_epk1.tdf" 339 2 0 } }  } 0 287001 "Assertion warning: %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536821 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_epk1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_epk1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_epk1 " "Found entity 1: altsyncram_epk1" {  } { { "db/altsyncram_epk1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_epk1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536821 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536821 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_epk1 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i\|altsyncram:altsyncram_component\|altsyncram_epk1:auto_generated " "Elaborating entity \"altsyncram_epk1\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_read_datapath:read_datapath_i\|rw_manager_pattern_fifo:pattern_fifo_i\|altsyncram:altsyncram_component\|altsyncram_epk1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536822 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_data_broadcast ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_data_broadcast:data_broadcast_i " "Elaborating entity \"rw_manager_data_broadcast\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_data_broadcast:data_broadcast_i\"" {  } { { "ddr3controller/rw_manager_core.sv" "data_broadcast_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 533 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536826 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_jumplogic ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_jumplogic:jumplogic_i " "Elaborating entity \"rw_manager_jumplogic\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_jumplogic:jumplogic_i\"" {  } { { "ddr3controller/rw_manager_core.sv" "jumplogic_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 560 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536828 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "rw_manager_datamux ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_datamux:mux_iter\[0\].datamux_i " "Elaborating entity \"rw_manager_datamux\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_datamux:mux_iter\[0\].datamux_i\"" {  } { { "ddr3controller/rw_manager_core.sv" "mux_iter\[0\].datamux_i" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 574 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536831 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0 " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\"" {  } { { "ddr3controller/ddr3controller_s0.v" "mm_interconnect_0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 287 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536836 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_translator ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_translator:cpu_inst_data_master_translator " "Elaborating entity \"altera_merlin_master_translator\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_translator:cpu_inst_data_master_translator\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "cpu_inst_data_master_translator" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 297 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536844 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_translator ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:sequencer_phy_mgr_inst_avl_translator " "Elaborating entity \"altera_merlin_slave_translator\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_translator:sequencer_phy_mgr_inst_avl_translator\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "sequencer_phy_mgr_inst_avl_translator" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 361 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536846 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_master_agent ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_agent:cpu_inst_data_master_agent " "Elaborating entity \"altera_merlin_master_agent\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_master_agent:cpu_inst_data_master_agent\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "cpu_inst_data_master_agent" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 570 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536850 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_slave_agent ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:sequencer_phy_mgr_inst_avl_agent " "Elaborating entity \"altera_merlin_slave_agent\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:sequencer_phy_mgr_inst_avl_agent\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "sequencer_phy_mgr_inst_avl_agent" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 654 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536852 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_burst_uncompressor ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:sequencer_phy_mgr_inst_avl_agent\|altera_merlin_burst_uncompressor:uncompressor " "Elaborating entity \"altera_merlin_burst_uncompressor\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_merlin_slave_agent:sequencer_phy_mgr_inst_avl_agent\|altera_merlin_burst_uncompressor:uncompressor\"" {  } { { "ddr3controller/altera_merlin_slave_agent.sv" "uncompressor" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_slave_agent.sv" 608 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536854 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_avalon_sc_fifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:sequencer_phy_mgr_inst_avl_agent_rsp_fifo " "Elaborating entity \"altera_avalon_sc_fifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|altera_avalon_sc_fifo:sequencer_phy_mgr_inst_avl_agent_rsp_fifo\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "sequencer_phy_mgr_inst_avl_agent_rsp_fifo" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 695 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536856 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_router ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_router:router " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_router\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_router:router\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "router" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 961 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536863 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_router_default_decode ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_router:router\|ddr3controller_s0_mm_interconnect_0_router_default_decode:the_default_decode " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_router_default_decode\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_router:router\|ddr3controller_s0_mm_interconnect_0_router_default_decode:the_default_decode\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" "the_default_decode" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router.sv" 181 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536865 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_router_001 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_router_001:router_001 " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_router_001\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_router_001:router_001\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "router_001" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 977 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536866 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_router_001_default_decode ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_router_001:router_001\|ddr3controller_s0_mm_interconnect_0_router_001_default_decode:the_default_decode " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_router_001_default_decode\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_router_001:router_001\|ddr3controller_s0_mm_interconnect_0_router_001_default_decode:the_default_decode\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" "the_default_decode" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_router_001.sv" 173 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536867 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_cmd_demux ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_cmd_demux:cmd_demux " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_cmd_demux\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_cmd_demux:cmd_demux\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "cmd_demux" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 1038 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536871 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_cmd_mux ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_cmd_mux:cmd_mux " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_cmd_mux\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_cmd_mux:cmd_mux\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "cmd_mux" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 1055 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536873 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_rsp_demux ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_rsp_demux:rsp_demux " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_rsp_demux\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_rsp_demux:rsp_demux\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "rsp_demux" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 1106 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536875 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_rsp_mux ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_rsp_mux:rsp_mux " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_rsp_mux\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_rsp_mux:rsp_mux\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "rsp_mux" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 1169 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536878 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arbitrator ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb " "Elaborating entity \"altera_merlin_arbitrator\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_mux.sv" "arb" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_rsp_mux.sv" 326 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536879 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altera_merlin_arb_adder ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder " "Elaborating entity \"altera_merlin_arb_adder\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_rsp_mux:rsp_mux\|altera_merlin_arbitrator:arb\|altera_merlin_arb_adder:adder\"" {  } { { "ddr3controller/altera_merlin_arbitrator.sv" "adder" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_arbitrator.sv" 169 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536881 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_avalon_st_adapter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_avalon_st_adapter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0.v" "avalon_st_adapter" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0.v" 1198 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536882 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0 " "Elaborating entity \"ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|ddr3controller_s0_mm_interconnect_0:mm_interconnect_0\|ddr3controller_s0_mm_interconnect_0_avalon_st_adapter:avalon_st_adapter\|ddr3controller_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0:error_adapter_0\"" {  } { { "ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter.v" "error_adapter_0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0_mm_interconnect_0_avalon_st_adapter.v" 200 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536884 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "ddr3controller_c0 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0 " "Elaborating entity \"ddr3controller_c0\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\"" {  } { { "ddr3controller/ddr3controller_0002.v" "c0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 410 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536889 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_if_nextgen_ddr3_controller_core ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0 " "Elaborating entity \"alt_mem_if_nextgen_ddr3_controller_core\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\"" {  } { { "ddr3controller/ddr3controller_c0.v" "ng0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_c0.v" 258 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536893 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_controller_st_top ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst " "Elaborating entity \"alt_mem_ddrx_controller_st_top\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\"" {  } { { "ddr3controller/alt_mem_if_nextgen_ddr3_controller_core.sv" "alt_mem_ddrx_controller_top_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_if_nextgen_ddr3_controller_core.sv" 528 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536896 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_controller ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst " "Elaborating entity \"alt_mem_ddrx_controller\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller_st_top.v" "controller_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller_st_top.v" 1206 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536899 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_input_if ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_input_if:input_if_inst " "Elaborating entity \"alt_mem_ddrx_input_if\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_input_if:input_if_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "input_if_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 1149 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536907 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_cmd_gen ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_cmd_gen:cmd_gen_inst " "Elaborating entity \"alt_mem_ddrx_cmd_gen\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_cmd_gen:cmd_gen_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "cmd_gen_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 1273 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536909 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_tbp ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_tbp:tbp_inst " "Elaborating entity \"alt_mem_ddrx_tbp\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_tbp:tbp_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "tbp_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 1413 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536914 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_arbiter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_arbiter:arbiter_inst " "Elaborating entity \"alt_mem_ddrx_arbiter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_arbiter:arbiter_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "arbiter_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 1522 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536920 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_burst_gen ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_burst_gen:burst_gen_inst " "Elaborating entity \"alt_mem_ddrx_burst_gen\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_burst_gen:burst_gen_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "burst_gen_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 1626 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536923 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_addr_cmd_wrap ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst " "Elaborating entity \"alt_mem_ddrx_addr_cmd_wrap\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "addr_cmd_wrap_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 1723 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536927 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_addr_cmd ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst\|alt_mem_ddrx_addr_cmd:gen_bg_afi_signal_decode\[0\].alt_mem_ddrx_addr_cmd_inst " "Elaborating entity \"alt_mem_ddrx_addr_cmd\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst\|alt_mem_ddrx_addr_cmd:gen_bg_afi_signal_decode\[0\].alt_mem_ddrx_addr_cmd_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" "gen_bg_afi_signal_decode\[0\].alt_mem_ddrx_addr_cmd_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" 584 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536930 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_odt_gen ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst\|alt_mem_ddrx_odt_gen:gen_bg_afi_signal_decode\[0\].odt_gen_inst " "Elaborating entity \"alt_mem_ddrx_odt_gen\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst\|alt_mem_ddrx_odt_gen:gen_bg_afi_signal_decode\[0\].odt_gen_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" "gen_bg_afi_signal_decode\[0\].odt_gen_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" 723 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536933 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ddr2_odt_gen ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst\|alt_mem_ddrx_odt_gen:gen_bg_afi_signal_decode\[0\].odt_gen_inst\|alt_mem_ddrx_ddr2_odt_gen:ddr2_odt_gen\[0\].alt_mem_ddrx_ddr2_odt_gen_inst " "Elaborating entity \"alt_mem_ddrx_ddr2_odt_gen\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst\|alt_mem_ddrx_odt_gen:gen_bg_afi_signal_decode\[0\].odt_gen_inst\|alt_mem_ddrx_ddr2_odt_gen:ddr2_odt_gen\[0\].alt_mem_ddrx_ddr2_odt_gen_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_odt_gen.v" "ddr2_odt_gen\[0\].alt_mem_ddrx_ddr2_odt_gen_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_odt_gen.v" 217 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536934 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ddr3_odt_gen ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst\|alt_mem_ddrx_odt_gen:gen_bg_afi_signal_decode\[0\].odt_gen_inst\|alt_mem_ddrx_ddr3_odt_gen:ddr3_odt_gen\[0\].alt_mem_ddrx_ddr3_odt_gen_inst " "Elaborating entity \"alt_mem_ddrx_ddr3_odt_gen\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst\|alt_mem_ddrx_odt_gen:gen_bg_afi_signal_decode\[0\].odt_gen_inst\|alt_mem_ddrx_ddr3_odt_gen:ddr3_odt_gen\[0\].alt_mem_ddrx_ddr3_odt_gen_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_odt_gen.v" "ddr3_odt_gen\[0\].alt_mem_ddrx_ddr3_odt_gen_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_odt_gen.v" 250 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536937 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_rdwr_data_tmg ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdwr_data_tmg:rdwr_data_tmg_inst " "Elaborating entity \"alt_mem_ddrx_rdwr_data_tmg\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdwr_data_tmg:rdwr_data_tmg_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "rdwr_data_tmg_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 1835 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536944 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_wdata_path ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst " "Elaborating entity \"alt_mem_ddrx_wdata_path\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "wdata_path_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 1983 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536952 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_list ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_list:wdatap_list_freeid_inst " "Elaborating entity \"alt_mem_ddrx_list\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_list:wdatap_list_freeid_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_wdata_path.v" "wdatap_list_freeid_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_wdata_path.v" 494 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536956 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_list ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_list:wdatap_list_allocated_id_inst " "Elaborating entity \"alt_mem_ddrx_list\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_list:wdatap_list_allocated_id_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_wdata_path.v" "wdatap_list_allocated_id_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_wdata_path.v" 517 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536958 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_burst_tracking ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_burst_tracking:wdatap_burst_tracking_inst " "Elaborating entity \"alt_mem_ddrx_burst_tracking\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_burst_tracking:wdatap_burst_tracking_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_wdata_path.v" "wdatap_burst_tracking_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_wdata_path.v" 542 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536959 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_dataid_manager ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_dataid_manager:wdatap_dataid_manager_inst " "Elaborating entity \"alt_mem_ddrx_dataid_manager\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_dataid_manager:wdatap_dataid_manager_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_wdata_path.v" "wdatap_dataid_manager_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_wdata_path.v" 614 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536961 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_buffer ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst " "Elaborating entity \"alt_mem_ddrx_buffer\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_wdata_path.v" "wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_wdata_path.v" 644 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536966 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "altsyncram_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 112 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536970 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 112 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933536971 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst\|altsyncram:altsyncram_component " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix " "Parameter \"intended_device_family\" = \"Stratix\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 64 " "Parameter \"numwords_a\" = \"64\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 64 " "Parameter \"numwords_b\" = \"64\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 6 " "Parameter \"widthad_a\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 6 " "Parameter \"widthad_b\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 16 " "Parameter \"width_a\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 16 " "Parameter \"width_b\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933536971 ""}  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 112 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933536971 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_l0l1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_l0l1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_l0l1 " "Found entity 1: altsyncram_l0l1" {  } { { "db/altsyncram_l0l1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_l0l1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933536999 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933536999 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_l0l1 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst\|altsyncram:altsyncram_component\|altsyncram_l0l1:auto_generated " "Elaborating entity \"altsyncram_l0l1\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_data_inst\|altsyncram:altsyncram_component\|altsyncram_l0l1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537000 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_buffer ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst " "Elaborating entity \"alt_mem_ddrx_buffer\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_wdata_path.v" "wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_wdata_path.v" 667 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537004 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "altsyncram_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 112 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537008 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 112 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537009 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst\|altsyncram:altsyncram_component " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix " "Parameter \"intended_device_family\" = \"Stratix\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 64 " "Parameter \"numwords_a\" = \"64\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 64 " "Parameter \"numwords_b\" = \"64\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 6 " "Parameter \"widthad_a\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 6 " "Parameter \"widthad_b\" = \"6\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 2 " "Parameter \"width_a\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 2 " "Parameter \"width_b\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537009 ""}  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 112 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933537009 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_btk1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_btk1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_btk1 " "Found entity 1: altsyncram_btk1" {  } { { "db/altsyncram_btk1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_btk1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537037 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537037 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_btk1 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst\|altsyncram:altsyncram_component\|altsyncram_btk1:auto_generated " "Elaborating entity \"altsyncram_btk1\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_buffer:wdata_buffer_per_dwidth_ratio\[0\].wdata_buffer_per_dqs_group\[0\].wdatap_buffer_be_inst\|altsyncram:altsyncram_component\|altsyncram_btk1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537038 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_fifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst " "Elaborating entity \"alt_mem_ddrx_fifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_wdata_path.v" "rmw_data_fifo_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_wdata_path.v" 935 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537089 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component " "Elaborating entity \"scfifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\"" {  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "gen_fifo_instance.scfifo_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537202 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\"" {  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537202 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix IV " "Parameter \"intended_device_family\" = \"Stratix IV\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 4 " "Parameter \"lpm_numwords\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 100 " "Parameter \"lpm_width\" = \"100\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 2 " "Parameter \"lpm_widthu\" = \"2\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537202 ""}  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933537202 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_2k31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_2k31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_2k31 " "Found entity 1: scfifo_2k31" {  } { { "db/scfifo_2k31.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/scfifo_2k31.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537229 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537229 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_2k31 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated " "Elaborating entity \"scfifo_2k31\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537230 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_bv21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_bv21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_bv21 " "Found entity 1: a_dpfifo_bv21" {  } { { "db/a_dpfifo_bv21.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_bv21.tdf" 32 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537234 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537234 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_bv21 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo " "Elaborating entity \"a_dpfifo_bv21\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\"" {  } { { "db/scfifo_2k31.tdf" "dpfifo" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/scfifo_2k31.tdf" 37 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537236 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_hkg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_hkg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_hkg1 " "Found entity 1: altsyncram_hkg1" {  } { { "db/altsyncram_hkg1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_hkg1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537276 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537276 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_hkg1 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|altsyncram_hkg1:FIFOram " "Elaborating entity \"altsyncram_hkg1\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|altsyncram_hkg1:FIFOram\"" {  } { { "db/a_dpfifo_bv21.tdf" "FIFOram" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_bv21.tdf" 45 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537277 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_578.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_578.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_578 " "Found entity 1: cmpr_578" {  } { { "db/cmpr_578.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cmpr_578.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537304 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537304 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_578 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cmpr_578:almost_full_comparer " "Elaborating entity \"cmpr_578\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cmpr_578:almost_full_comparer\"" {  } { { "db/a_dpfifo_bv21.tdf" "almost_full_comparer" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_bv21.tdf" 54 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537305 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_578 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cmpr_578:three_comparison " "Elaborating entity \"cmpr_578\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cmpr_578:three_comparison\"" {  } { { "db/a_dpfifo_bv21.tdf" "three_comparison" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_bv21.tdf" 55 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537308 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_i2b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_i2b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_i2b " "Found entity 1: cntr_i2b" {  } { { "db/cntr_i2b.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_i2b.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537334 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537334 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_i2b ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cntr_i2b:rd_ptr_msb " "Elaborating entity \"cntr_i2b\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cntr_i2b:rd_ptr_msb\"" {  } { { "db/a_dpfifo_bv21.tdf" "rd_ptr_msb" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_bv21.tdf" 56 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537335 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_v27.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_v27.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_v27 " "Found entity 1: cntr_v27" {  } { { "db/cntr_v27.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_v27.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537362 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537362 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_v27 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cntr_v27:usedw_counter " "Elaborating entity \"cntr_v27\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cntr_v27:usedw_counter\"" {  } { { "db/a_dpfifo_bv21.tdf" "usedw_counter" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_bv21.tdf" 57 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537363 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_j2b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_j2b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_j2b " "Found entity 1: cntr_j2b" {  } { { "db/cntr_j2b.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_j2b.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537390 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537390 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_j2b ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cntr_j2b:wr_ptr " "Elaborating entity \"cntr_j2b\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_wdata_path:wdata_path_inst\|alt_mem_ddrx_fifo:rmw_data_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_2k31:auto_generated\|a_dpfifo_bv21:dpfifo\|cntr_j2b:wr_ptr\"" {  } { { "db/a_dpfifo_bv21.tdf" "wr_ptr" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_bv21.tdf" 58 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537391 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_rdata_path ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst " "Elaborating entity \"alt_mem_ddrx_rdata_path\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "rdata_path_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 2082 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537396 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_fifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo " "Elaborating entity \"alt_mem_ddrx_fifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\"" {  } { { "ddr3controller/alt_mem_ddrx_rdata_path.v" "pending_rd_fifo" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rdata_path.v" 596 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537400 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component " "Elaborating entity \"scfifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\"" {  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "gen_fifo_instance.scfifo_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537500 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\"" {  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537501 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix IV " "Parameter \"intended_device_family\" = \"Stratix IV\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 16 " "Parameter \"lpm_numwords\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 46 " "Parameter \"lpm_width\" = \"46\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 4 " "Parameter \"lpm_widthu\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537501 ""}  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933537501 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_gk31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_gk31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_gk31 " "Found entity 1: scfifo_gk31" {  } { { "db/scfifo_gk31.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/scfifo_gk31.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537528 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537528 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_gk31 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated " "Elaborating entity \"scfifo_gk31\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537529 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_pv21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_pv21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_pv21 " "Found entity 1: a_dpfifo_pv21" {  } { { "db/a_dpfifo_pv21.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_pv21.tdf" 32 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537533 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537533 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_pv21 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo " "Elaborating entity \"a_dpfifo_pv21\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\"" {  } { { "db/scfifo_gk31.tdf" "dpfifo" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/scfifo_gk31.tdf" 37 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537534 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_dlg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_dlg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_dlg1 " "Found entity 1: altsyncram_dlg1" {  } { { "db/altsyncram_dlg1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_dlg1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537567 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537567 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_dlg1 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|altsyncram_dlg1:FIFOram " "Elaborating entity \"altsyncram_dlg1\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|altsyncram_dlg1:FIFOram\"" {  } { { "db/a_dpfifo_pv21.tdf" "FIFOram" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_pv21.tdf" 45 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537568 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_778.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_778.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_778 " "Found entity 1: cmpr_778" {  } { { "db/cmpr_778.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cmpr_778.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537595 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537595 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_778 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cmpr_778:almost_full_comparer " "Elaborating entity \"cmpr_778\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cmpr_778:almost_full_comparer\"" {  } { { "db/a_dpfifo_pv21.tdf" "almost_full_comparer" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_pv21.tdf" 54 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537596 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_778 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cmpr_778:three_comparison " "Elaborating entity \"cmpr_778\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cmpr_778:three_comparison\"" {  } { { "db/a_dpfifo_pv21.tdf" "three_comparison" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_pv21.tdf" 55 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537599 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_k2b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_k2b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_k2b " "Found entity 1: cntr_k2b" {  } { { "db/cntr_k2b.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_k2b.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537625 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537625 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_k2b ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cntr_k2b:rd_ptr_msb " "Elaborating entity \"cntr_k2b\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cntr_k2b:rd_ptr_msb\"" {  } { { "db/a_dpfifo_pv21.tdf" "rd_ptr_msb" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_pv21.tdf" 56 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537626 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_137.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_137.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_137 " "Found entity 1: cntr_137" {  } { { "db/cntr_137.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_137.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537653 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537653 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_137 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cntr_137:usedw_counter " "Elaborating entity \"cntr_137\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cntr_137:usedw_counter\"" {  } { { "db/a_dpfifo_pv21.tdf" "usedw_counter" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_pv21.tdf" 57 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537654 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_l2b.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_l2b.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_l2b " "Found entity 1: cntr_l2b" {  } { { "db/cntr_l2b.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_l2b.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537682 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537682 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_l2b ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cntr_l2b:wr_ptr " "Elaborating entity \"cntr_l2b\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:pending_rd_fifo\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_gk31:auto_generated\|a_dpfifo_pv21:dpfifo\|cntr_l2b:wr_ptr\"" {  } { { "db/a_dpfifo_pv21.tdf" "wr_ptr" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_pv21.tdf" 58 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537683 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_fifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst " "Elaborating entity \"alt_mem_ddrx_fifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_rdata_path.v" "errcmd_fifo_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rdata_path.v" 824 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537688 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component " "Elaborating entity \"scfifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\"" {  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "gen_fifo_instance.scfifo_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537788 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\"" {  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537788 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix IV " "Parameter \"intended_device_family\" = \"Stratix IV\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 8 " "Parameter \"lpm_numwords\" = \"8\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 40 " "Parameter \"lpm_width\" = \"40\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 3 " "Parameter \"lpm_widthu\" = \"3\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933537788 ""}  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933537788 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_qi31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_qi31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_qi31 " "Found entity 1: scfifo_qi31" {  } { { "db/scfifo_qi31.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/scfifo_qi31.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537814 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537814 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_qi31 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated " "Elaborating entity \"scfifo_qi31\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537815 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_3u21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_3u21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_3u21 " "Found entity 1: a_dpfifo_3u21" {  } { { "db/a_dpfifo_3u21.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_3u21.tdf" 32 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537819 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537819 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_3u21 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo " "Elaborating entity \"a_dpfifo_3u21\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo\"" {  } { { "db/scfifo_qi31.tdf" "dpfifo" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/scfifo_qi31.tdf" 37 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537820 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_1ig1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_1ig1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_1ig1 " "Found entity 1: altsyncram_1ig1" {  } { { "db/altsyncram_1ig1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_1ig1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537852 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537852 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_1ig1 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo\|altsyncram_1ig1:FIFOram " "Elaborating entity \"altsyncram_1ig1\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo\|altsyncram_1ig1:FIFOram\"" {  } { { "db/a_dpfifo_3u21.tdf" "FIFOram" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_3u21.tdf" 45 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537854 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cmpr_678.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cmpr_678.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cmpr_678 " "Found entity 1: cmpr_678" {  } { { "db/cmpr_678.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cmpr_678.tdf" 22 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537880 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537880 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_678 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo\|cmpr_678:almost_full_comparer " "Elaborating entity \"cmpr_678\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo\|cmpr_678:almost_full_comparer\"" {  } { { "db/a_dpfifo_3u21.tdf" "almost_full_comparer" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_3u21.tdf" 54 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537882 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cmpr_678 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo\|cmpr_678:three_comparison " "Elaborating entity \"cmpr_678\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo\|cmpr_678:three_comparison\"" {  } { { "db/a_dpfifo_3u21.tdf" "three_comparison" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_3u21.tdf" 55 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537884 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/cntr_037.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/cntr_037.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 cntr_037 " "Found entity 1: cntr_037" {  } { { "db/cntr_037.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/cntr_037.tdf" 25 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933537912 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933537912 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "cntr_037 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo\|cntr_037:usedw_counter " "Elaborating entity \"cntr_037\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:errcmd_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_qi31:auto_generated\|a_dpfifo_3u21:dpfifo\|cntr_037:usedw_counter\"" {  } { { "db/a_dpfifo_3u21.tdf" "usedw_counter" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_3u21.tdf" 57 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537913 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_list ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_list:gen_rdata_return_inorder.list_freeid_inst " "Elaborating entity \"alt_mem_ddrx_list\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_list:gen_rdata_return_inorder.list_freeid_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_rdata_path.v" "gen_rdata_return_inorder.list_freeid_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rdata_path.v" 1052 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537919 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_list ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_list:gen_rdata_return_inorder.list_allocated_id_inst " "Elaborating entity \"alt_mem_ddrx_list\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_list:gen_rdata_return_inorder.list_allocated_id_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_rdata_path.v" "gen_rdata_return_inorder.list_allocated_id_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rdata_path.v" 1075 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537922 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_fifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst " "Elaborating entity \"alt_mem_ddrx_fifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_rdata_path.v" "gen_rdata_return_inorder.inordr_info_fifo_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rdata_path.v" 1099 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933537925 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component " "Elaborating entity \"scfifo\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\"" {  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "gen_fifo_instance.scfifo_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538025 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\"" {  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538025 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "add_ram_output_register ON " "Parameter \"add_ram_output_register\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix IV " "Parameter \"intended_device_family\" = \"Stratix IV\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_numwords 16 " "Parameter \"lpm_numwords\" = \"16\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_showahead ON " "Parameter \"lpm_showahead\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type scfifo " "Parameter \"lpm_type\" = \"scfifo\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_width 11 " "Parameter \"lpm_width\" = \"11\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_widthu 4 " "Parameter \"lpm_widthu\" = \"4\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "overflow_checking OFF " "Parameter \"overflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "underflow_checking OFF " "Parameter \"underflow_checking\" = \"OFF\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "use_eab ON " "Parameter \"use_eab\" = \"ON\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538026 ""}  } { { "ddr3controller/alt_mem_ddrx_fifo.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_fifo.v" 138 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933538026 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/scfifo_8k31.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/scfifo_8k31.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 scfifo_8k31 " "Found entity 1: scfifo_8k31" {  } { { "db/scfifo_8k31.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/scfifo_8k31.tdf" 24 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933538052 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933538052 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "scfifo_8k31 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_8k31:auto_generated " "Elaborating entity \"scfifo_8k31\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_8k31:auto_generated\"" {  } { { "scfifo.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/scfifo.tdf" 299 3 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538053 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/a_dpfifo_hv21.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/a_dpfifo_hv21.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_dpfifo_hv21 " "Found entity 1: a_dpfifo_hv21" {  } { { "db/a_dpfifo_hv21.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_hv21.tdf" 32 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933538057 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933538057 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "a_dpfifo_hv21 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_8k31:auto_generated\|a_dpfifo_hv21:dpfifo " "Elaborating entity \"a_dpfifo_hv21\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_8k31:auto_generated\|a_dpfifo_hv21:dpfifo\"" {  } { { "db/scfifo_8k31.tdf" "dpfifo" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/scfifo_8k31.tdf" 37 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538058 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_tkg1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_tkg1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_tkg1 " "Found entity 1: altsyncram_tkg1" {  } { { "db/altsyncram_tkg1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_tkg1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933538086 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933538086 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_tkg1 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_8k31:auto_generated\|a_dpfifo_hv21:dpfifo\|altsyncram_tkg1:FIFOram " "Elaborating entity \"altsyncram_tkg1\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_fifo:gen_rdata_return_inorder.inordr_info_fifo_inst\|scfifo:gen_fifo_instance.scfifo_component\|scfifo_8k31:auto_generated\|a_dpfifo_hv21:dpfifo\|altsyncram_tkg1:FIFOram\"" {  } { { "db/a_dpfifo_hv21.tdf" "FIFOram" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/a_dpfifo_hv21.tdf" 45 2 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538087 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_buffer ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst " "Elaborating entity \"alt_mem_ddrx_buffer\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_rdata_path.v" "gen_rdata_return_inorder.in_order_buffer_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_rdata_path.v" 1171 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538101 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst\|altsyncram:altsyncram_component " "Elaborating entity \"altsyncram\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "altsyncram_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 112 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538105 ""}
{ "Info" "ISGN_ELABORATION_HEADER" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst\|altsyncram:altsyncram_component " "Elaborated megafunction instantiation \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst\|altsyncram:altsyncram_component\"" {  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 112 0 0 } }  } 0 12130 "Elaborated megafunction instantiation \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538106 ""}
{ "Info" "ISGN_MEGAFN_PARAM_TOP" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst\|altsyncram:altsyncram_component " "Instantiated megafunction \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst\|altsyncram:altsyncram_component\" with the following parameter:" { { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_a NONE " "Parameter \"address_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_aclr_b NONE " "Parameter \"address_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "address_reg_b CLOCK0 " "Parameter \"address_reg_b\" = \"CLOCK0\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "indata_aclr_a NONE " "Parameter \"indata_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "intended_device_family Stratix " "Parameter \"intended_device_family\" = \"Stratix\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "lpm_type altsyncram " "Parameter \"lpm_type\" = \"altsyncram\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_a 128 " "Parameter \"numwords_a\" = \"128\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "numwords_b 128 " "Parameter \"numwords_b\" = \"128\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "operation_mode DUAL_PORT " "Parameter \"operation_mode\" = \"DUAL_PORT\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_aclr_b NONE " "Parameter \"outdata_aclr_b\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "outdata_reg_b UNREGISTERED " "Parameter \"outdata_reg_b\" = \"UNREGISTERED\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "power_up_uninitialized FALSE " "Parameter \"power_up_uninitialized\" = \"FALSE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "read_during_write_mode_mixed_ports DONT_CARE " "Parameter \"read_during_write_mode_mixed_ports\" = \"DONT_CARE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_a 7 " "Parameter \"widthad_a\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "widthad_b 7 " "Parameter \"widthad_b\" = \"7\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_a 65 " "Parameter \"width_a\" = \"65\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_b 65 " "Parameter \"width_b\" = \"65\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "width_byteena_a 1 " "Parameter \"width_byteena_a\" = \"1\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""} { "Info" "ISGN_MEGAFN_PARAM_SUB" "wrcontrol_aclr_a NONE " "Parameter \"wrcontrol_aclr_a\" = \"NONE\"" {  } {  } 0 12134 "Parameter \"%1!s!\" = \"%2!s!\"" 0 0 "Design Software" 0 -1 1613933538106 ""}  } { { "ddr3controller/alt_mem_ddrx_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_buffer.v" 112 0 0 } }  } 0 12133 "Instantiated megafunction \"%1!s!\" with the following parameter:" 0 0 "Analysis & Synthesis" 0 -1 1613933538106 ""}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "db/altsyncram_14l1.tdf 1 1 " "Found 1 design units, including 1 entities, in source file db/altsyncram_14l1.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altsyncram_14l1 " "Found entity 1: altsyncram_14l1" {  } { { "db/altsyncram_14l1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_14l1.tdf" 27 1 0 } }  } 0 12023 "Found entity %1!d!: %2!s!" 0 0 "Design Software" 0 -1 1613933538142 ""}  } {  } 0 12021 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933538142 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "altsyncram_14l1 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst\|altsyncram:altsyncram_component\|altsyncram_14l1:auto_generated " "Elaborating entity \"altsyncram_14l1\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rdata_path:rdata_path_inst\|alt_mem_ddrx_buffer:gen_rdata_return_inorder.in_order_buffer_inst\|altsyncram:altsyncram_component\|altsyncram_14l1:auto_generated\"" {  } { { "altsyncram.tdf" "auto_generated" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538143 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ecc_encoder_decoder_wrapper ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst " "Elaborating entity \"alt_mem_ddrx_ecc_encoder_decoder_wrapper\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "ecc_encoder_decoder_wrapper_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 2166 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538148 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ecc_encoder ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_encoder:encoder_inst_per_drate\[0\].encoder_inst " "Elaborating entity \"alt_mem_ddrx_ecc_encoder\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_encoder:encoder_inst_per_drate\[0\].encoder_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" "encoder_inst_per_drate\[0\].encoder_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" 695 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538152 ""}
{ "Warning" "WVRFX_L2_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 alt_mem_ddrx_ecc_encoder.v(203) " "Verilog HDL assignment warning at alt_mem_ddrx_ecc_encoder.v(203): truncated value with size 32 to match size of target (8)" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder.v" 203 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0 "Analysis & Synthesis" 0 -1 1613933538153 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_c0:c0|alt_mem_if_nextgen_ddr3_controller_core:ng0|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst|alt_mem_ddrx_controller:controller_inst|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst|alt_mem_ddrx_ecc_encoder:encoder_inst_per_drate[0].encoder_inst"}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ecc_encoder_32 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_encoder:encoder_inst_per_drate\[0\].encoder_inst\|alt_mem_ddrx_ecc_encoder_32:encoder_inst " "Elaborating entity \"alt_mem_ddrx_ecc_encoder_32\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_encoder:encoder_inst_per_drate\[0\].encoder_inst\|alt_mem_ddrx_ecc_encoder_32:encoder_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder.v" "encoder_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder.v" 219 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538154 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ecc_encoder_32_altecc_encoder ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_encoder:encoder_inst_per_drate\[0\].encoder_inst\|alt_mem_ddrx_ecc_encoder_32:encoder_inst\|alt_mem_ddrx_ecc_encoder_32_altecc_encoder:alt_mem_ddrx_ecc_encoder_32_altecc_encoder_component " "Elaborating entity \"alt_mem_ddrx_ecc_encoder_32_altecc_encoder\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_encoder:encoder_inst_per_drate\[0\].encoder_inst\|alt_mem_ddrx_ecc_encoder_32:encoder_inst\|alt_mem_ddrx_ecc_encoder_32_altecc_encoder:alt_mem_ddrx_ecc_encoder_32_altecc_encoder_component\"" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_32_syn.v" "alt_mem_ddrx_ecc_encoder_32_altecc_encoder_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_32_syn.v" 258 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538155 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ecc_decoder ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_decoder:decoder_inst_per_drate\[0\].decoder_inst " "Elaborating entity \"alt_mem_ddrx_ecc_decoder\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_decoder:decoder_inst_per_drate\[0\].decoder_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" "decoder_inst_per_drate\[0\].decoder_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v" 793 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538192 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ecc_decoder_32 ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_decoder:decoder_inst_per_drate\[0\].decoder_inst\|alt_mem_ddrx_ecc_decoder_32:decoder_inst " "Elaborating entity \"alt_mem_ddrx_ecc_decoder_32\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_decoder:decoder_inst_per_drate\[0\].decoder_inst\|alt_mem_ddrx_ecc_decoder_32:decoder_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder.v" "decoder_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder.v" 342 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538194 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ecc_decoder_32_altecc_decoder ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_decoder:decoder_inst_per_drate\[0\].decoder_inst\|alt_mem_ddrx_ecc_decoder_32:decoder_inst\|alt_mem_ddrx_ecc_decoder_32_altecc_decoder:alt_mem_ddrx_ecc_decoder_32_altecc_decoder_component " "Elaborating entity \"alt_mem_ddrx_ecc_decoder_32_altecc_decoder\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_decoder:decoder_inst_per_drate\[0\].decoder_inst\|alt_mem_ddrx_ecc_decoder_32:decoder_inst\|alt_mem_ddrx_ecc_decoder_32_altecc_decoder:alt_mem_ddrx_ecc_decoder_32_altecc_decoder_component\"" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" "alt_mem_ddrx_ecc_decoder_32_altecc_decoder_component" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" 459 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538195 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_ecc_decoder_32_decode ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_decoder:decoder_inst_per_drate\[0\].decoder_inst\|alt_mem_ddrx_ecc_decoder_32:decoder_inst\|alt_mem_ddrx_ecc_decoder_32_altecc_decoder:alt_mem_ddrx_ecc_decoder_32_altecc_decoder_component\|alt_mem_ddrx_ecc_decoder_32_decode:error_bit_decoder " "Elaborating entity \"alt_mem_ddrx_ecc_decoder_32_decode\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_ecc_encoder_decoder_wrapper:ecc_encoder_decoder_wrapper_inst\|alt_mem_ddrx_ecc_decoder:decoder_inst_per_drate\[0\].decoder_inst\|alt_mem_ddrx_ecc_decoder_32:decoder_inst\|alt_mem_ddrx_ecc_decoder_32_altecc_decoder:alt_mem_ddrx_ecc_decoder_32_altecc_decoder_component\|alt_mem_ddrx_ecc_decoder_32_decode:error_bit_decoder\"" {  } { { "ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" "error_bit_decoder" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_ecc_decoder_32_syn.v" 345 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538197 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_sideband ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_sideband:sideband_inst " "Elaborating entity \"alt_mem_ddrx_sideband\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_sideband:sideband_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "sideband_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 2259 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538214 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_rank_timer ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rank_timer:rank_timer_inst " "Elaborating entity \"alt_mem_ddrx_rank_timer\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_rank_timer:rank_timer_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "rank_timer_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 2331 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538219 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_timing_param ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_timing_param:timing_param_inst " "Elaborating entity \"alt_mem_ddrx_timing_param\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_if_nextgen_ddr3_controller_core:ng0\|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst\|alt_mem_ddrx_controller:controller_inst\|alt_mem_ddrx_timing_param:timing_param_inst\"" {  } { { "ddr3controller/alt_mem_ddrx_controller.v" "timing_param_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_controller.v" 2511 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538222 ""}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "alt_mem_ddrx_mm_st_converter ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_ddrx_mm_st_converter:a0 " "Elaborating entity \"alt_mem_ddrx_mm_st_converter\" for hierarchy \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_c0:c0\|alt_mem_ddrx_mm_st_converter:a0\"" {  } { { "ddr3controller/ddr3controller_c0.v" "a0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_c0.v" 307 0 0 } }  } 0 12128 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933538229 ""}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "bg_to_lmr gen_bg_afi_signal_decode\[1\].alt_mem_ddrx_addr_cmd_inst 8 3 " "Port \"bg_to_lmr\" on the entity instantiation of \"gen_bg_afi_signal_decode\[1\].alt_mem_ddrx_addr_cmd_inst\" is connected to a signal of width 8. The formal width of the signal in the module is 3.  The extra bits will be ignored." {  } { { "ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" "gen_bg_afi_signal_decode\[1\].alt_mem_ddrx_addr_cmd_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" 584 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  The extra bits will be ignored." 0 0 "Analysis & Synthesis" 0 -1 1613933539237 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_c0:c0|alt_mem_if_nextgen_ddr3_controller_core:ng0|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst|alt_mem_ddrx_controller:controller_inst|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst|alt_mem_ddrx_addr_cmd:gen_bg_afi_signal_decode[1].alt_mem_ddrx_addr_cmd_inst"}
{ "Warning" "WSGN_WIDTH_MISMATCH_INPUT_PORT_TOO_NARROW" "bg_to_lmr gen_bg_afi_signal_decode\[0\].alt_mem_ddrx_addr_cmd_inst 8 3 " "Port \"bg_to_lmr\" on the entity instantiation of \"gen_bg_afi_signal_decode\[0\].alt_mem_ddrx_addr_cmd_inst\" is connected to a signal of width 8. The formal width of the signal in the module is 3.  The extra bits will be ignored." {  } { { "ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" "gen_bg_afi_signal_decode\[0\].alt_mem_ddrx_addr_cmd_inst" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_addr_cmd_wrap.v" 584 0 0 } }  } 0 12020 "Port \"%1!s!\" on the entity instantiation of \"%2!s!\" is connected to a signal of width %3!d!. The formal width of the signal in the module is %4!d!.  The extra bits will be ignored." 0 0 "Analysis & Synthesis" 0 -1 1613933539238 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_c0:c0|alt_mem_if_nextgen_ddr3_controller_core:ng0|alt_mem_ddrx_controller_st_top:alt_mem_ddrx_controller_top_inst|alt_mem_ddrx_controller:controller_inst|alt_mem_ddrx_addr_cmd_wrap:addr_cmd_wrap_inst|alt_mem_ddrx_addr_cmd:gen_bg_afi_signal_decode[0].alt_mem_ddrx_addr_cmd_inst"}
{ "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_HDR" "" "Synthesized away the following node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_SUB_HDR" "RAM " "Synthesized away the following RAM node(s):" { { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[8\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[8\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 285 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a8"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[9\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[9\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 316 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a9"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[10\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[10\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 347 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a10"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[11\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[11\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 378 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a11"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[12\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[12\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 409 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a12"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[13\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[13\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 440 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a13"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" 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"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[15\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[15\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 502 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a15"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[16\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[16\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 533 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a16"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[17\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[17\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 564 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a17"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[18\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[18\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 595 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a18"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[19\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[19\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 626 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a19"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a21"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[22\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[22\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 719 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a22"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[23\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[23\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 750 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a23"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[24\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[24\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 781 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a24"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[25\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[25\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 812 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a25"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[26\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[26\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 843 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a26"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[27\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[27\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 874 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 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"/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a27"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[28\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[28\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 905 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a28"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[29\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[29\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 936 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a29"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[30\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[30\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 967 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a30"} { "Warning" "WCDB_SGATE_CDB_SGATE_SWEPT_NODE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[31\] " "Synthesized away node \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_di_buffer_wrap:di_buffer_wrap_i\|rw_manager_di_buffer:rw_manager_di_buffer_i\|altsyncram:altsyncram_component\|altsyncram_uok1:auto_generated\|q_b\[31\]\"" {  } { { "db/altsyncram_uok1.tdf" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altsyncram_uok1.tdf" 998 2 0 } } { "altsyncram.tdf" "" { Text "/home/mhu/intelFPGA_lite/18.1/quartus/libraries/megafunctions/altsyncram.tdf" 791 4 0 } } { "ddr3controller/rw_manager_di_buffer.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer.v" 114 0 0 } } { "ddr3controller/rw_manager_di_buffer_wrap.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_di_buffer_wrap.v" 54 0 0 } } { "ddr3controller/rw_manager_core.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_core.sv" 483 0 0 } } { "ddr3controller/rw_manager_generic.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_generic.sv" 343 0 0 } } { "ddr3controller/rw_manager_ddr3.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_ddr3.v" 159 0 0 } } { "ddr3controller/ddr3controller_s0.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_s0.v" 257 0 0 } } { "ddr3controller/ddr3controller_0002.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/ddr3controller_0002.v" 367 0 0 } } { "ddr3controller.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller.vhd" 108 0 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 138 0 0 } }  } 0 14320 "Synthesized away node \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933540210 "|top|ddr3controller:ddr3controller_1|ddr3controller_0002:ddr3controller_inst|ddr3controller_s0:s0|rw_manager_ddr3:sequencer_rw_mgr_inst|rw_manager_generic:rw_mgr_inst|rw_manager_core:rw_mgr_core_inst|rw_manager_di_buffer_wrap:di_buffer_wrap_i|rw_manager_di_buffer:rw_manager_di_buffer_i|altsyncram:altsyncram_component|altsyncram_uok1:auto_generated|ram_block1a31"}  } {  } 0 14285 "Synthesized away the following %1!s! node(s):" 0 0 "Design Software" 0 -1 1613933540210 ""}  } {  } 0 14284 "Synthesized away the following node(s):" 0 0 "Analysis & Synthesis" 0 -1 1613933540210 ""}
{ "Warning" "WSSC_TIMING_DRIVEN_SYNTHESIS_SKIPPED_FOR_TIMING_NETLIST" "" "Timing-Driven Synthesis is skipped because it could not initialize the timing netlist" {  } {  } 0 330000 "Timing-Driven Synthesis is skipped because it could not initialize the timing netlist" 0 0 "Analysis & Synthesis" 0 -1 1613933541244 ""}
{ "Info" "IINFER_UNINFERRED_RAM_SUMMARY" "2 " "Found 2 instances of uninferred RAM logic" { { "Info" "IINFER_MIF_NOT_SUPPORTED_FOR_HARDCOPY" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_m10_inst_ROM:inst_ROM_i\|Ram0 " "RAM logic \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_s0:s0\|rw_manager_ddr3:sequencer_rw_mgr_inst\|rw_manager_generic:rw_mgr_inst\|rw_manager_core:rw_mgr_core_inst\|rw_manager_m10_inst_ROM:inst_ROM_i\|Ram0\" is uninferred because MIF is not supported for the selected family" {  } { { "ddr3controller/rw_manager_m10_inst_ROM.v" "Ram0" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_m10_inst_ROM.v" 17 -1 0 } }  } 0 276013 "RAM logic \"%1!s!\" is uninferred because MIF is not supported for the selected family" 0 0 "Design Software" 0 -1 1613933543151 ""} { "Info" "IINFER_RAM_UNINFERRED_DUE_TO_SIZE" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_read_datapath_m10:uread_datapath\|max10emif_dcfifo:rdata_fifo\|fifo " "RAM logic \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_p0:p0\|ddr3controller_p0_memphy_m10:umemphy\|ddr3controller_p0_read_datapath_m10:uread_datapath\|max10emif_dcfifo:rdata_fifo\|fifo\" is uninferred due to inappropriate RAM size" {  } { { "ddr3controller/max10emif_dcfifo.sv" "fifo" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/max10emif_dcfifo.sv" 62 -1 0 } }  } 0 276004 "RAM logic \"%1!s!\" is uninferred due to inappropriate RAM size" 0 0 "Design Software" 0 -1 1613933543151 ""}  } {  } 0 276014 "Found %1!d! instances of uninferred RAM logic" 0 0 "Analysis & Synthesis" 0 -1 1613933543151 ""}
{ "Info" "IMLS_MLS_PRESET_POWER_UP" "" "Registers with preset signals will power-up high" {  } { { "ddr3controller/alt_mem_ddrx_list.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_list.v" 137 -1 0 } } { "../top.vhd" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/top.vhd" 49 -1 0 } } { "ddr3controller/sequencer_phy_mgr.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/sequencer_phy_mgr.sv" 150 -1 0 } } { "ddr3controller/rw_manager_lfsr12.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_lfsr12.v" 32 -1 0 } } { "ddr3controller/sequencer_phy_mgr.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/sequencer_phy_mgr.sv" 277 -1 0 } } { "ddr3controller/rw_manager_lfsr36.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/rw_manager_lfsr36.v" 32 -1 0 } } { "ddr3controller/altera_merlin_master_agent.sv" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/altera_merlin_master_agent.sv" 239 -1 0 } } { "ddr3controller/alt_mem_ddrx_sideband.v" "" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/ddr3controller/alt_mem_ddrx_sideband.v" 1099 -1 0 } }  } 0 13000 "Registers with preset signals will power-up high" 0 0 "Analysis & Synthesis" 0 -1 1613933547447 ""}
{ "Info" "IMLS_MLS_DEV_CLRN_SETS_REGISTERS" "" "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" {  } {  } 0 13003 "DEV_CLRn pin will set, and not reset, register with preset signal due to NOT Gate Push-Back" 0 0 "Analysis & Synthesis" 0 -1 1613933547447 ""}
{ "Info" "ISUTIL_TIMING_DRIVEN_SYNTHESIS_RUNNING" "" "Timing-Driven Synthesis is running" {  } {  } 0 286030 "Timing-Driven Synthesis is running" 0 0 "Analysis & Synthesis" 0 -1 1613933550543 ""}
{ "Info" "ISCL_SCL_LOST_FANOUT_MSG_HDR" "2130 " "2130 registers lost all their fanouts during netlist optimizations." {  } {  } 0 17049 "%1!d! registers lost all their fanouts during netlist optimizations." 0 0 "Analysis & Synthesis" 0 -1 1613933556536 ""}
{ "Info" "ISCL_SCL_WANNA_REM_USR_WIRE" "" "Found the following redundant logic cells in design" { { "Info" "ISCL_SCL_CELL_NAME" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_qrn:altpll_dyn_phase_le2\|combout " "Logic cell \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_qrn:altpll_dyn_phase_le2\|combout\"" {  } { { "db/altpll_dyn_phase_le_qrn.tdf" "le_comb8" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_dyn_phase_le_qrn.tdf" 36 2 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933556576 ""} { "Info" "ISCL_SCL_CELL_NAME" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_rrn:altpll_dyn_phase_le4\|combout " "Logic cell \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_rrn:altpll_dyn_phase_le4\|combout\"" {  } { { "db/altpll_dyn_phase_le_rrn.tdf" "le_comb9" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_dyn_phase_le_rrn.tdf" 36 2 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933556576 ""} { "Info" "ISCL_SCL_CELL_NAME" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_srn:altpll_dyn_phase_le5\|combout " "Logic cell \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|altpll_dyn_phase_le_srn:altpll_dyn_phase_le5\|combout\"" {  } { { "db/altpll_dyn_phase_le_srn.tdf" "le_comb10" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_dyn_phase_le_srn.tdf" 36 2 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933556576 ""} { "Info" "ISCL_SCL_CELL_NAME" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|remap_decoy_le3a\[0\] " "Logic cell \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|remap_decoy_le3a\[0\]\"" {  } { { "db/altpll_t0j3.tdf" "remap_decoy_le3a\[0\]" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 59 18 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933556576 ""} { "Info" "ISCL_SCL_CELL_NAME" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|remap_decoy_le3a\[1\] " "Logic cell \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|remap_decoy_le3a\[1\]\"" {  } { { "db/altpll_t0j3.tdf" "remap_decoy_le3a\[1\]" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 59 18 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933556576 ""} { "Info" "ISCL_SCL_CELL_NAME" "ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|remap_decoy_le3a\[2\] " "Logic cell \"ddr3controller:ddr3controller_1\|ddr3controller_0002:ddr3controller_inst\|ddr3controller_pll0:pll0\|altpll:upll_memphy\|altpll_t0j3:auto_generated\|remap_decoy_le3a\[2\]\"" {  } { { "db/altpll_t0j3.tdf" "remap_decoy_le3a\[2\]" { Text "/home/mhu/projects/fpga/deca-ddr3-test/quartus/db/altpll_t0j3.tdf" 59 18 0 } }  } 0 17048 "Logic cell \"%1!s!\"" 0 0 "Design Software" 0 -1 1613933556576 ""}  } {  } 0 17016 "Found the following redundant logic cells in design" 0 0 "Analysis & Synthesis" 0 -1 1613933556576 ""}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/home/mhu/projects/fpga/deca-ddr3-test/quartus/output_files/deca-ddr3-test.map.smsg " "Generated suppressed messages file /home/mhu/projects/fpga/deca-ddr3-test/quartus/output_files/deca-ddr3-test.map.smsg" {  } {  } 0 144001 "Generated suppressed messages file %1!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933556782 ""}
{ "Info" "IBPM_HARD_BLOCK_PARTITION_CREATED" "hard_block:auto_generated_inst " "Generating hard_block partition \"hard_block:auto_generated_inst\"" { { "Info" "IBPM_HARD_BLOCK_PARTITION_NODE" "7 0 1 0 6 " "Adding 7 node(s), including 0 DDIO, 1 PLL, 0 transceiver and 6 LCELL" {  } {  } 0 16011 "Adding %1!d! node(s), including %2!d! DDIO, %3!d! PLL, %4!d! transceiver and %5!d! LCELL" 0 0 "Design Software" 0 -1 1613933557726 ""}  } {  } 0 16010 "Generating hard_block partition \"%1!s!\"" 0 0 "Analysis & Synthesis" 0 -1 1613933557726 ""}
{ "Info" "ICUT_CUT_TM_SUMMARY" "7050 " "Implemented 7050 device resources after synthesis - the final resource count might be different" { { "Info" "ICUT_CUT_TM_IPINS" "3 " "Implemented 3 input pins" {  } {  } 0 21058 "Implemented %1!d! input pins" 0 0 "Design Software" 0 -1 1613933558231 ""} { "Info" "ICUT_CUT_TM_OPINS" "35 " "Implemented 35 output pins" {  } {  } 0 21059 "Implemented %1!d! output pins" 0 0 "Design Software" 0 -1 1613933558231 ""} { "Info" "ICUT_CUT_TM_BIDIRS" "22 " "Implemented 22 bidirectional pins" {  } {  } 0 21060 "Implemented %1!d! bidirectional pins" 0 0 "Design Software" 0 -1 1613933558231 ""} { "Info" "ICUT_CUT_TM_LCELLS" "6758 " "Implemented 6758 logic cells" {  } {  } 0 21061 "Implemented %1!d! logic cells" 0 0 "Design Software" 0 -1 1613933558231 ""} { "Info" "ICUT_CUT_TM_RAMS" "144 " "Implemented 144 RAM segments" {  } {  } 0 21064 "Implemented %1!d! RAM segments" 0 0 "Design Software" 0 -1 1613933558231 ""} { "Info" "ICUT_CUT_TM_PLLS" "1 " "Implemented 1 PLLs" {  } {  } 0 21065 "Implemented %1!d! PLLs" 0 0 "Design Software" 0 -1 1613933558231 ""}  } {  } 0 21057 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0 "Analysis & Synthesis" 0 -1 1613933558231 ""}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 67 s Quartus Prime " "Quartus Prime Analysis & Synthesis was successful. 0 errors, 67 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "1204 " "Peak virtual memory: 1204 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "Design Software" 0 -1 1613933558322 ""} { "Info" "IQEXE_END_BANNER_TIME" "Sun Feb 21 19:52:38 2021 " "Processing ended: Sun Feb 21 19:52:38 2021" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "Design Software" 0 -1 1613933558322 ""} { "Info" "IQEXE_ELAPSED_TIME" "00:00:33 " "Elapsed time: 00:00:33" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "Design Software" 0 -1 1613933558322 ""} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:43 " "Total CPU time (on all processors): 00:00:43" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "Design Software" 0 -1 1613933558322 ""}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "Analysis & Synthesis" 0 -1 1613933558322 ""}
