-- ddr3controller_c0.vhd

-- This file was auto-generated from alt_mem_if_nextgen_ddr3_controller_hw.tcl.  If you edit it your changes
-- will probably be lost.
-- 
-- Generated using ACDS version 18.1 625

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity ddr3controller_c0 is
	port (
		afi_reset_n         : in  std_logic                     := '0';             --    afi_reset.reset_n
		afi_clk             : in  std_logic                     := '0';             --      afi_clk.clk
		afi_half_clk        : in  std_logic                     := '0';             -- afi_half_clk.clk
		local_init_done     : out std_logic;                                        --       status.local_init_done
		local_cal_success   : out std_logic;                                        --             .local_cal_success
		local_cal_fail      : out std_logic;                                        --             .local_cal_fail
		afi_addr            : out std_logic_vector(29 downto 0);                    --          afi.afi_addr
		afi_ba              : out std_logic_vector(5 downto 0);                     --             .afi_ba
		afi_ras_n           : out std_logic_vector(1 downto 0);                     --             .afi_ras_n
		afi_we_n            : out std_logic_vector(1 downto 0);                     --             .afi_we_n
		afi_cas_n           : out std_logic_vector(1 downto 0);                     --             .afi_cas_n
		afi_odt             : out std_logic_vector(1 downto 0);                     --             .afi_odt
		afi_cke             : out std_logic_vector(1 downto 0);                     --             .afi_cke
		afi_cs_n            : out std_logic_vector(1 downto 0);                     --             .afi_cs_n
		afi_dqs_burst       : out std_logic_vector(3 downto 0);                     --             .afi_dqs_burst
		afi_wdata_valid     : out std_logic_vector(3 downto 0);                     --             .afi_wdata_valid
		afi_wdata           : out std_logic_vector(63 downto 0);                    --             .afi_wdata
		afi_dm              : out std_logic_vector(7 downto 0);                     --             .afi_dm
		afi_rdata           : in  std_logic_vector(63 downto 0) := (others => '0'); --             .afi_rdata
		afi_rst_n           : out std_logic_vector(1 downto 0);                     --             .afi_rst_n
		afi_mem_clk_disable : out std_logic_vector(0 downto 0);                     --             .afi_mem_clk_disable
		afi_init_req        : out std_logic;                                        --             .afi_init_req
		afi_cal_req         : out std_logic;                                        --             .afi_cal_req
		afi_rdata_en        : out std_logic_vector(1 downto 0);                     --             .afi_rdata_en
		afi_rdata_en_full   : out std_logic_vector(1 downto 0);                     --             .afi_rdata_en_full
		afi_rdata_valid     : in  std_logic_vector(1 downto 0)  := (others => '0'); --             .afi_rdata_valid
		afi_cal_success     : in  std_logic                     := '0';             --             .afi_cal_success
		afi_cal_fail        : in  std_logic                     := '0';             --             .afi_cal_fail
		afi_wlat            : in  std_logic_vector(5 downto 0)  := (others => '0'); --             .afi_wlat
		afi_rlat            : in  std_logic_vector(5 downto 0)  := (others => '0'); --             .afi_rlat
		avl_ready           : out std_logic;                                        --          avl.waitrequest_n
		avl_burstbegin      : in  std_logic                     := '0';             --             .beginbursttransfer
		avl_addr            : in  std_logic_vector(25 downto 0) := (others => '0'); --             .address
		avl_rdata_valid     : out std_logic;                                        --             .readdatavalid
		avl_rdata           : out std_logic_vector(63 downto 0);                    --             .readdata
		avl_wdata           : in  std_logic_vector(63 downto 0) := (others => '0'); --             .writedata
		avl_be              : in  std_logic_vector(7 downto 0)  := (others => '0'); --             .byteenable
		avl_read_req        : in  std_logic                     := '0';             --             .read
		avl_write_req       : in  std_logic                     := '0';             --             .write
		avl_size            : in  std_logic_vector(2 downto 0)  := (others => '0')  --             .burstcount
	);
end entity ddr3controller_c0;

architecture rtl of ddr3controller_c0 is
	component alt_mem_if_nextgen_ddr3_controller_core is
		generic (
			MEM_IF_ADDR_WIDTH                : integer := 0;
			MEM_IF_ROW_ADDR_WIDTH            : integer := 0;
			MEM_IF_COL_ADDR_WIDTH            : integer := 0;
			MEM_IF_DM_WIDTH                  : integer := 0;
			MEM_IF_DQS_WIDTH                 : integer := 0;
			MEM_IF_CS_WIDTH                  : integer := 0;
			MEM_IF_CHIP_BITS                 : integer := -1;
			MEM_IF_BANKADDR_WIDTH            : integer := 0;
			MEM_IF_DQ_WIDTH                  : integer := 0;
			MEM_IF_CLK_EN_WIDTH              : integer := 0;
			MEM_IF_CLK_PAIR_COUNT            : integer := 1;
			MEM_TRC                          : integer := 0;
			MEM_TRAS                         : integer := 0;
			MEM_TRCD                         : integer := 0;
			MEM_TRP                          : integer := 0;
			MEM_TREFI                        : integer := 0;
			MEM_TRFC                         : integer := 0;
			MEM_TWR                          : integer := 0;
			MEM_TFAW                         : integer := 0;
			MEM_TRRD                         : integer := 0;
			MEM_TRTP                         : integer := 0;
			MEM_IF_ODT_WIDTH                 : integer := 0;
			MEM_WTCL_INT                     : integer := 6;
			MEM_IF_RD_TO_WR_TURNAROUND_OCT   : integer := 0;
			MEM_IF_WR_TO_RD_TURNAROUND_OCT   : integer := 3;
			CTL_RD_TO_PCH_EXTRA_CLK          : integer := 0;
			CTL_RD_TO_RD_EXTRA_CLK           : integer := 0;
			CTL_WR_TO_WR_EXTRA_CLK           : integer := 0;
			CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK : integer := 0;
			CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK : integer := 0;
			MEM_TCL                          : integer := 7;
			MEM_TMRD_CK                      : integer := 3;
			MEM_TWTR                         : integer := 2;
			CSR_ADDR_WIDTH                   : integer := 8;
			CSR_DATA_WIDTH                   : integer := 32;
			CSR_BE_WIDTH                     : integer := 4;
			CTL_CS_WIDTH                     : integer := 0;
			AVL_ADDR_WIDTH                   : integer := 0;
			AVL_BE_WIDTH                     : integer := 0;
			AVL_DATA_WIDTH                   : integer := 0;
			AVL_SIZE_WIDTH                   : integer := 0;
			DWIDTH_RATIO                     : integer := 4;
			CTL_ODT_ENABLED                  : boolean := false;
			CTL_OUTPUT_REGD                  : boolean := false;
			CTL_ECC_MULTIPLES_16_24_40_72    : integer := 0;
			CTL_REGDIMM_ENABLED              : boolean := false;
			CTL_TBP_NUM                      : integer := 4;
			CTL_USR_REFRESH                  : integer := 0;
			CFG_TYPE                         : integer := 0;
			CFG_INTERFACE_WIDTH              : integer := 0;
			CFG_BURST_LENGTH                 : integer := 0;
			CFG_ADDR_ORDER                   : integer := 0;
			CFG_PDN_EXIT_CYCLES              : integer := 0;
			CFG_POWER_SAVING_EXIT_CYCLES     : integer := 0;
			CFG_MEM_CLK_ENTRY_CYCLES         : integer := 0;
			CFG_SELF_RFSH_EXIT_CYCLES        : integer := 0;
			CFG_PORT_WIDTH_WRITE_ODT_CHIP    : integer := 0;
			CFG_PORT_WIDTH_READ_ODT_CHIP     : integer := 0;
			CFG_WRITE_ODT_CHIP               : integer := 0;
			CFG_READ_ODT_CHIP                : integer := 0;
			LOCAL_CS_WIDTH                   : integer := 0;
			CFG_CLR_INTR                     : integer := 0;
			CFG_ENABLE_NO_DM                 : integer := 0;
			MEM_ADD_LAT                      : integer := 0;
			CTL_ENABLE_BURST_INTERRUPT_INT   : boolean := false;
			CTL_ENABLE_BURST_TERMINATE_INT   : boolean := false;
			CFG_ERRCMD_FIFO_REG              : integer := 0;
			CFG_ECC_DECODER_REG              : integer := 0;
			CTL_ENABLE_WDATA_PATH_LATENCY    : boolean := false;
			CFG_STARVE_LIMIT                 : integer := 0;
			MEM_AUTO_PD_CYCLES               : integer := 0;
			CONTINUE_AFTER_CAL_FAIL          : boolean := false;
			MAX10_CFG                        : boolean := false;
			CFG_REORDER_DATA                 : boolean := true;
			CTL_CSR_ENABLED                  : boolean := false;
			CTL_ECC_ENABLED                  : boolean := false;
			CTL_ECC_AUTO_CORRECTION_ENABLED  : boolean := false;
			ENABLE_BURST_MERGE               : boolean := false;
			LOCAL_ID_WIDTH                   : integer := 8;
			RDBUFFER_ADDR_WIDTH              : integer := 6;
			WRBUFFER_ADDR_WIDTH              : integer := 6;
			MAX_PENDING_WR_CMD               : integer := 16;
			MAX_PENDING_RD_CMD               : integer := 32;
			CFG_DATA_REORDERING_TYPE         : string  := "INTER_BANK";
			USE_DQS_TRACKING                 : boolean := false;
			USE_SHADOW_REGS                  : boolean := false;
			AFI_RATE_RATIO                   : integer := 0;
			AFI_ADDR_WIDTH                   : integer := 0;
			AFI_BANKADDR_WIDTH               : integer := 0;
			AFI_CONTROL_WIDTH                : integer := 0;
			AFI_CS_WIDTH                     : integer := 0;
			AFI_CLK_EN_WIDTH                 : integer := 0;
			AFI_DM_WIDTH                     : integer := 0;
			AFI_DQ_WIDTH                     : integer := 0;
			AFI_ODT_WIDTH                    : integer := 0;
			AFI_WRITE_DQS_WIDTH              : integer := 0;
			AFI_RLAT_WIDTH                   : integer := 0;
			AFI_WLAT_WIDTH                   : integer := 0;
			AFI_RRANK_WIDTH                  : integer := 0;
			AFI_WRANK_WIDTH                  : integer := 0
		);
		port (
			afi_reset_n             : in  std_logic                     := 'X';             -- reset_n
			afi_half_clk            : in  std_logic                     := 'X';             -- clk
			afi_clk                 : in  std_logic                     := 'X';             -- clk
			local_init_done         : out std_logic;                                        -- local_init_done
			local_cal_success       : out std_logic;                                        -- local_cal_success
			local_cal_fail          : out std_logic;                                        -- local_cal_fail
			itf_cmd_ready           : out std_logic;                                        -- itf_cmd_ready
			itf_cmd_valid           : in  std_logic                     := 'X';             -- itf_cmd_valid
			itf_cmd                 : in  std_logic                     := 'X';             -- itf_cmd
			itf_cmd_address         : in  std_logic_vector(25 downto 0) := (others => 'X'); -- itf_cmd_address
			itf_cmd_burstlen        : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- itf_cmd_burstlen
			itf_cmd_id              : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- itf_cmd_id
			itf_cmd_priority        : in  std_logic                     := 'X';             -- itf_cmd_priority
			itf_cmd_autopercharge   : in  std_logic                     := 'X';             -- itf_cmd_autopercharge
			itf_cmd_multicast       : in  std_logic                     := 'X';             -- itf_cmd_multicast
			itf_wr_data_ready       : out std_logic;                                        -- itf_wr_data_ready
			itf_wr_data_valid       : in  std_logic                     := 'X';             -- itf_wr_data_valid
			itf_wr_data             : in  std_logic_vector(63 downto 0) := (others => 'X'); -- itf_wr_data
			itf_wr_data_byte_en     : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- itf_wr_data_byte_en
			itf_wr_data_begin       : in  std_logic                     := 'X';             -- itf_wr_data_begin
			itf_wr_data_last        : in  std_logic                     := 'X';             -- itf_wr_data_last
			itf_wr_data_id          : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- itf_wr_data_id
			itf_rd_data_ready       : in  std_logic                     := 'X';             -- itf_rd_data_ready
			itf_rd_data_valid       : out std_logic;                                        -- itf_rd_data_valid
			itf_rd_data             : out std_logic_vector(63 downto 0);                    -- itf_rd_data
			itf_rd_data_error       : out std_logic;                                        -- itf_rd_data_error
			itf_rd_data_begin       : out std_logic;                                        -- itf_rd_data_begin
			itf_rd_data_last        : out std_logic;                                        -- itf_rd_data_last
			itf_rd_data_id          : out std_logic_vector(7 downto 0);                     -- itf_rd_data_id
			afi_addr                : out std_logic_vector(29 downto 0);                    -- afi_addr
			afi_ba                  : out std_logic_vector(5 downto 0);                     -- afi_ba
			afi_ras_n               : out std_logic_vector(1 downto 0);                     -- afi_ras_n
			afi_we_n                : out std_logic_vector(1 downto 0);                     -- afi_we_n
			afi_cas_n               : out std_logic_vector(1 downto 0);                     -- afi_cas_n
			afi_odt                 : out std_logic_vector(1 downto 0);                     -- afi_odt
			afi_cke                 : out std_logic_vector(1 downto 0);                     -- afi_cke
			afi_cs_n                : out std_logic_vector(1 downto 0);                     -- afi_cs_n
			afi_dqs_burst           : out std_logic_vector(3 downto 0);                     -- afi_dqs_burst
			afi_wdata_valid         : out std_logic_vector(3 downto 0);                     -- afi_wdata_valid
			afi_wdata               : out std_logic_vector(63 downto 0);                    -- afi_wdata
			afi_dm                  : out std_logic_vector(7 downto 0);                     -- afi_dm
			afi_rdata               : in  std_logic_vector(63 downto 0) := (others => 'X'); -- afi_rdata
			afi_rst_n               : out std_logic_vector(1 downto 0);                     -- afi_rst_n
			afi_mem_clk_disable     : out std_logic_vector(0 downto 0);                     -- afi_mem_clk_disable
			afi_init_req            : out std_logic;                                        -- afi_init_req
			afi_cal_req             : out std_logic;                                        -- afi_cal_req
			afi_rdata_en            : out std_logic_vector(1 downto 0);                     -- afi_rdata_en
			afi_rdata_en_full       : out std_logic_vector(1 downto 0);                     -- afi_rdata_en_full
			afi_rdata_valid         : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_valid
			afi_cal_success         : in  std_logic                     := 'X';             -- afi_cal_success
			afi_cal_fail            : in  std_logic                     := 'X';             -- afi_cal_fail
			afi_wlat                : in  std_logic_vector(5 downto 0)  := (others => 'X'); -- afi_wlat
			afi_rlat                : in  std_logic_vector(5 downto 0)  := (others => 'X'); -- afi_rlat
			csr_write_req           : in  std_logic                     := 'X';             -- write
			csr_read_req            : in  std_logic                     := 'X';             -- read
			csr_waitrequest         : out std_logic;                                        -- waitrequest
			csr_addr                : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- address
			csr_be                  : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- byteenable
			csr_wdata               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			csr_rdata               : out std_logic_vector(31 downto 0);                    -- readdata
			csr_rdata_valid         : out std_logic;                                        -- readdatavalid
			afi_seq_busy            : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- afi_seq_busy
			afi_ctl_refresh_done    : out std_logic_vector(0 downto 0);                     -- afi_ctl_refresh_done
			afi_ctl_long_idle       : out std_logic_vector(0 downto 0);                     -- afi_ctl_long_idle
			afi_rrank               : out std_logic_vector(3 downto 0);                     -- afi_rrank
			afi_wrank               : out std_logic_vector(3 downto 0);                     -- afi_wrank
			local_multicast         : in  std_logic                     := 'X';             -- local_multicast
			local_refresh_req       : in  std_logic                     := 'X';             -- local_refresh_req
			local_refresh_chip      : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- local_refresh_chip
			local_refresh_ack       : out std_logic;                                        -- local_refresh_ack
			local_self_rfsh_req     : in  std_logic                     := 'X';             -- local_self_rfsh_req
			local_self_rfsh_chip    : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- local_self_rfsh_chip
			local_self_rfsh_ack     : out std_logic;                                        -- local_self_rfsh_ack
			local_deep_powerdn_req  : in  std_logic                     := 'X';             -- local_deep_powerdn_req
			local_deep_powerdn_chip : in  std_logic_vector(0 downto 0)  := (others => 'X'); -- local_deep_powerdn_chip
			local_deep_powerdn_ack  : out std_logic;                                        -- local_deep_powerdn_ack
			local_powerdn_ack       : out std_logic;                                        -- local_powerdn_ack
			local_priority          : in  std_logic                     := 'X';             -- local_priority
			local_zqcal_req         : in  std_logic                     := 'X';             -- local_zqcal_req
			local_zqcal_chip        : in  std_logic_vector(0 downto 0)  := (others => 'X')  -- local_zqcal_chip
		);
	end component alt_mem_if_nextgen_ddr3_controller_core;

	component alt_mem_ddrx_mm_st_converter is
		generic (
			AVL_SIZE_WIDTH   : integer := 3;
			AVL_ADDR_WIDTH   : integer := 25;
			AVL_DATA_WIDTH   : integer := 32;
			LOCAL_ID_WIDTH   : integer := 8;
			CFG_DWIDTH_RATIO : integer := 4
		);
		port (
			ctl_clk               : in  std_logic                     := 'X';             -- clk
			ctl_reset_n           : in  std_logic                     := 'X';             -- reset_n
			ctl_half_clk          : in  std_logic                     := 'X';             -- clk
			ctl_half_clk_reset_n  : in  std_logic                     := 'X';             -- reset_n
			avl_ready             : out std_logic;                                        -- waitrequest_n
			avl_burstbegin        : in  std_logic                     := 'X';             -- beginbursttransfer
			avl_addr              : in  std_logic_vector(25 downto 0) := (others => 'X'); -- address
			avl_rdata_valid       : out std_logic;                                        -- readdatavalid
			avl_rdata             : out std_logic_vector(63 downto 0);                    -- readdata
			avl_wdata             : in  std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
			avl_be                : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- byteenable
			avl_read_req          : in  std_logic                     := 'X';             -- read
			avl_write_req         : in  std_logic                     := 'X';             -- write
			avl_size              : in  std_logic_vector(2 downto 0)  := (others => 'X'); -- burstcount
			itf_cmd_ready         : in  std_logic                     := 'X';             -- itf_cmd_ready
			itf_cmd_valid         : out std_logic;                                        -- itf_cmd_valid
			itf_cmd               : out std_logic;                                        -- itf_cmd
			itf_cmd_address       : out std_logic_vector(25 downto 0);                    -- itf_cmd_address
			itf_cmd_burstlen      : out std_logic_vector(2 downto 0);                     -- itf_cmd_burstlen
			itf_cmd_id            : out std_logic_vector(7 downto 0);                     -- itf_cmd_id
			itf_cmd_priority      : out std_logic;                                        -- itf_cmd_priority
			itf_cmd_autopercharge : out std_logic;                                        -- itf_cmd_autopercharge
			itf_cmd_multicast     : out std_logic;                                        -- itf_cmd_multicast
			itf_wr_data_ready     : in  std_logic                     := 'X';             -- itf_wr_data_ready
			itf_wr_data_valid     : out std_logic;                                        -- itf_wr_data_valid
			itf_wr_data           : out std_logic_vector(63 downto 0);                    -- itf_wr_data
			itf_wr_data_byte_en   : out std_logic_vector(7 downto 0);                     -- itf_wr_data_byte_en
			itf_wr_data_begin     : out std_logic;                                        -- itf_wr_data_begin
			itf_wr_data_last      : out std_logic;                                        -- itf_wr_data_last
			itf_wr_data_id        : out std_logic_vector(7 downto 0);                     -- itf_wr_data_id
			itf_rd_data_ready     : out std_logic;                                        -- itf_rd_data_ready
			itf_rd_data_valid     : in  std_logic                     := 'X';             -- itf_rd_data_valid
			itf_rd_data           : in  std_logic_vector(63 downto 0) := (others => 'X'); -- itf_rd_data
			itf_rd_data_error     : in  std_logic                     := 'X';             -- itf_rd_data_error
			itf_rd_data_begin     : in  std_logic                     := 'X';             -- itf_rd_data_begin
			itf_rd_data_last      : in  std_logic                     := 'X';             -- itf_rd_data_last
			itf_rd_data_id        : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- itf_rd_data_id
			local_multicast       : in  std_logic                     := 'X';             -- local_multicast
			local_autopch_req     : in  std_logic                     := 'X';             -- local_autopch_req
			local_priority        : in  std_logic                     := 'X'              -- local_priority
		);
	end component alt_mem_ddrx_mm_st_converter;

	signal a0_native_st_itf_wr_data_begin     : std_logic;                     -- a0:itf_wr_data_begin -> ng0:itf_wr_data_begin
	signal ng0_native_st_itf_rd_data_last     : std_logic;                     -- ng0:itf_rd_data_last -> a0:itf_rd_data_last
	signal a0_native_st_itf_cmd_autopercharge : std_logic;                     -- a0:itf_cmd_autopercharge -> ng0:itf_cmd_autopercharge
	signal ng0_native_st_itf_rd_data_error    : std_logic;                     -- ng0:itf_rd_data_error -> a0:itf_rd_data_error
	signal a0_native_st_itf_cmd_priority      : std_logic;                     -- a0:itf_cmd_priority -> ng0:itf_cmd_priority
	signal a0_native_st_itf_wr_data_byte_en   : std_logic_vector(7 downto 0);  -- a0:itf_wr_data_byte_en -> ng0:itf_wr_data_byte_en
	signal ng0_native_st_itf_rd_data_id       : std_logic_vector(7 downto 0);  -- ng0:itf_rd_data_id -> a0:itf_rd_data_id
	signal a0_native_st_itf_wr_data           : std_logic_vector(63 downto 0); -- a0:itf_wr_data -> ng0:itf_wr_data
	signal a0_native_st_itf_wr_data_valid     : std_logic;                     -- a0:itf_wr_data_valid -> ng0:itf_wr_data_valid
	signal a0_native_st_itf_cmd_id            : std_logic_vector(7 downto 0);  -- a0:itf_cmd_id -> ng0:itf_cmd_id
	signal ng0_native_st_itf_rd_data          : std_logic_vector(63 downto 0); -- ng0:itf_rd_data -> a0:itf_rd_data
	signal ng0_native_st_itf_cmd_ready        : std_logic;                     -- ng0:itf_cmd_ready -> a0:itf_cmd_ready
	signal ng0_native_st_itf_rd_data_begin    : std_logic;                     -- ng0:itf_rd_data_begin -> a0:itf_rd_data_begin
	signal a0_native_st_itf_cmd_multicast     : std_logic;                     -- a0:itf_cmd_multicast -> ng0:itf_cmd_multicast
	signal a0_native_st_itf_wr_data_last      : std_logic;                     -- a0:itf_wr_data_last -> ng0:itf_wr_data_last
	signal ng0_native_st_itf_rd_data_valid    : std_logic;                     -- ng0:itf_rd_data_valid -> a0:itf_rd_data_valid
	signal a0_native_st_itf_cmd_valid         : std_logic;                     -- a0:itf_cmd_valid -> ng0:itf_cmd_valid
	signal ng0_native_st_itf_wr_data_ready    : std_logic;                     -- ng0:itf_wr_data_ready -> a0:itf_wr_data_ready
	signal a0_native_st_itf_rd_data_ready     : std_logic;                     -- a0:itf_rd_data_ready -> ng0:itf_rd_data_ready
	signal a0_native_st_itf_cmd_burstlen      : std_logic_vector(2 downto 0);  -- a0:itf_cmd_burstlen -> ng0:itf_cmd_burstlen
	signal a0_native_st_itf_cmd               : std_logic;                     -- a0:itf_cmd -> ng0:itf_cmd
	signal a0_native_st_itf_cmd_address       : std_logic_vector(25 downto 0); -- a0:itf_cmd_address -> ng0:itf_cmd_address
	signal a0_native_st_itf_wr_data_id        : std_logic_vector(7 downto 0);  -- a0:itf_wr_data_id -> ng0:itf_wr_data_id

begin

	ng0 : component alt_mem_if_nextgen_ddr3_controller_core
		generic map (
			MEM_IF_ADDR_WIDTH                => 15,
			MEM_IF_ROW_ADDR_WIDTH            => 15,
			MEM_IF_COL_ADDR_WIDTH            => 10,
			MEM_IF_DM_WIDTH                  => 2,
			MEM_IF_DQS_WIDTH                 => 2,
			MEM_IF_CS_WIDTH                  => 1,
			MEM_IF_CHIP_BITS                 => 1,
			MEM_IF_BANKADDR_WIDTH            => 3,
			MEM_IF_DQ_WIDTH                  => 16,
			MEM_IF_CLK_EN_WIDTH              => 1,
			MEM_IF_CLK_PAIR_COUNT            => 1,
			MEM_TRC                          => 15,
			MEM_TRAS                         => 11,
			MEM_TRCD                         => 5,
			MEM_TRP                          => 5,
			MEM_TREFI                        => 2341,
			MEM_TRFC                         => 79,
			MEM_TWR                          => 5,
			MEM_TFAW                         => 14,
			MEM_TRRD                         => 3,
			MEM_TRTP                         => 3,
			MEM_IF_ODT_WIDTH                 => 1,
			MEM_WTCL_INT                     => 6,
			MEM_IF_RD_TO_WR_TURNAROUND_OCT   => 2,
			MEM_IF_WR_TO_RD_TURNAROUND_OCT   => 3,
			CTL_RD_TO_PCH_EXTRA_CLK          => 0,
			CTL_RD_TO_RD_EXTRA_CLK           => 0,
			CTL_WR_TO_WR_EXTRA_CLK           => 0,
			CTL_RD_TO_RD_DIFF_CHIP_EXTRA_CLK => 1,
			CTL_WR_TO_WR_DIFF_CHIP_EXTRA_CLK => 1,
			MEM_TCL                          => 7,
			MEM_TMRD_CK                      => 4,
			MEM_TWTR                         => 6,
			CSR_ADDR_WIDTH                   => 8,
			CSR_DATA_WIDTH                   => 32,
			CSR_BE_WIDTH                     => 4,
			CTL_CS_WIDTH                     => 1,
			AVL_ADDR_WIDTH                   => 26,
			AVL_BE_WIDTH                     => 8,
			AVL_DATA_WIDTH                   => 64,
			AVL_SIZE_WIDTH                   => 3,
			DWIDTH_RATIO                     => 4,
			CTL_ODT_ENABLED                  => true,
			CTL_OUTPUT_REGD                  => false,
			CTL_ECC_MULTIPLES_16_24_40_72    => 1,
			CTL_REGDIMM_ENABLED              => false,
			CTL_TBP_NUM                      => 4,
			CTL_USR_REFRESH                  => 0,
			CFG_TYPE                         => 2,
			CFG_INTERFACE_WIDTH              => 16,
			CFG_BURST_LENGTH                 => 8,
			CFG_ADDR_ORDER                   => 0,
			CFG_PDN_EXIT_CYCLES              => 10,
			CFG_POWER_SAVING_EXIT_CYCLES     => 5,
			CFG_MEM_CLK_ENTRY_CYCLES         => 20,
			CFG_SELF_RFSH_EXIT_CYCLES        => 512,
			CFG_PORT_WIDTH_WRITE_ODT_CHIP    => 1,
			CFG_PORT_WIDTH_READ_ODT_CHIP     => 1,
			CFG_WRITE_ODT_CHIP               => 1,
			CFG_READ_ODT_CHIP                => 0,
			LOCAL_CS_WIDTH                   => 0,
			CFG_CLR_INTR                     => 0,
			CFG_ENABLE_NO_DM                 => 0,
			MEM_ADD_LAT                      => 0,
			CTL_ENABLE_BURST_INTERRUPT_INT   => false,
			CTL_ENABLE_BURST_TERMINATE_INT   => false,
			CFG_ERRCMD_FIFO_REG              => 0,
			CFG_ECC_DECODER_REG              => 0,
			CTL_ENABLE_WDATA_PATH_LATENCY    => false,
			CFG_STARVE_LIMIT                 => 10,
			MEM_AUTO_PD_CYCLES               => 0,
			CONTINUE_AFTER_CAL_FAIL          => false,
			MAX10_CFG                        => true,
			CFG_REORDER_DATA                 => true,
			CTL_CSR_ENABLED                  => false,
			CTL_ECC_ENABLED                  => false,
			CTL_ECC_AUTO_CORRECTION_ENABLED  => false,
			ENABLE_BURST_MERGE               => false,
			LOCAL_ID_WIDTH                   => 8,
			RDBUFFER_ADDR_WIDTH              => 7,
			WRBUFFER_ADDR_WIDTH              => 6,
			MAX_PENDING_WR_CMD               => 16,
			MAX_PENDING_RD_CMD               => 32,
			CFG_DATA_REORDERING_TYPE         => "INTER_BANK",
			USE_DQS_TRACKING                 => false,
			USE_SHADOW_REGS                  => false,
			AFI_RATE_RATIO                   => 2,
			AFI_ADDR_WIDTH                   => 30,
			AFI_BANKADDR_WIDTH               => 6,
			AFI_CONTROL_WIDTH                => 2,
			AFI_CS_WIDTH                     => 2,
			AFI_CLK_EN_WIDTH                 => 2,
			AFI_DM_WIDTH                     => 8,
			AFI_DQ_WIDTH                     => 64,
			AFI_ODT_WIDTH                    => 2,
			AFI_WRITE_DQS_WIDTH              => 4,
			AFI_RLAT_WIDTH                   => 6,
			AFI_WLAT_WIDTH                   => 6,
			AFI_RRANK_WIDTH                  => 4,
			AFI_WRANK_WIDTH                  => 4
		)
		port map (
			afi_reset_n             => afi_reset_n,                        --    afi_reset.reset_n
			afi_half_clk            => afi_half_clk,                       -- afi_half_clk.clk
			afi_clk                 => afi_clk,                            --      afi_clk.clk
			local_init_done         => local_init_done,                    --       status.local_init_done
			local_cal_success       => local_cal_success,                  --             .local_cal_success
			local_cal_fail          => local_cal_fail,                     --             .local_cal_fail
			itf_cmd_ready           => ng0_native_st_itf_cmd_ready,        --    native_st.itf_cmd_ready
			itf_cmd_valid           => a0_native_st_itf_cmd_valid,         --             .itf_cmd_valid
			itf_cmd                 => a0_native_st_itf_cmd,               --             .itf_cmd
			itf_cmd_address         => a0_native_st_itf_cmd_address,       --             .itf_cmd_address
			itf_cmd_burstlen        => a0_native_st_itf_cmd_burstlen,      --             .itf_cmd_burstlen
			itf_cmd_id              => a0_native_st_itf_cmd_id,            --             .itf_cmd_id
			itf_cmd_priority        => a0_native_st_itf_cmd_priority,      --             .itf_cmd_priority
			itf_cmd_autopercharge   => a0_native_st_itf_cmd_autopercharge, --             .itf_cmd_autopercharge
			itf_cmd_multicast       => a0_native_st_itf_cmd_multicast,     --             .itf_cmd_multicast
			itf_wr_data_ready       => ng0_native_st_itf_wr_data_ready,    --             .itf_wr_data_ready
			itf_wr_data_valid       => a0_native_st_itf_wr_data_valid,     --             .itf_wr_data_valid
			itf_wr_data             => a0_native_st_itf_wr_data,           --             .itf_wr_data
			itf_wr_data_byte_en     => a0_native_st_itf_wr_data_byte_en,   --             .itf_wr_data_byte_en
			itf_wr_data_begin       => a0_native_st_itf_wr_data_begin,     --             .itf_wr_data_begin
			itf_wr_data_last        => a0_native_st_itf_wr_data_last,      --             .itf_wr_data_last
			itf_wr_data_id          => a0_native_st_itf_wr_data_id,        --             .itf_wr_data_id
			itf_rd_data_ready       => a0_native_st_itf_rd_data_ready,     --             .itf_rd_data_ready
			itf_rd_data_valid       => ng0_native_st_itf_rd_data_valid,    --             .itf_rd_data_valid
			itf_rd_data             => ng0_native_st_itf_rd_data,          --             .itf_rd_data
			itf_rd_data_error       => ng0_native_st_itf_rd_data_error,    --             .itf_rd_data_error
			itf_rd_data_begin       => ng0_native_st_itf_rd_data_begin,    --             .itf_rd_data_begin
			itf_rd_data_last        => ng0_native_st_itf_rd_data_last,     --             .itf_rd_data_last
			itf_rd_data_id          => ng0_native_st_itf_rd_data_id,       --             .itf_rd_data_id
			afi_addr                => afi_addr,                           --          afi.afi_addr
			afi_ba                  => afi_ba,                             --             .afi_ba
			afi_ras_n               => afi_ras_n,                          --             .afi_ras_n
			afi_we_n                => afi_we_n,                           --             .afi_we_n
			afi_cas_n               => afi_cas_n,                          --             .afi_cas_n
			afi_odt                 => afi_odt,                            --             .afi_odt
			afi_cke                 => afi_cke,                            --             .afi_cke
			afi_cs_n                => afi_cs_n,                           --             .afi_cs_n
			afi_dqs_burst           => afi_dqs_burst,                      --             .afi_dqs_burst
			afi_wdata_valid         => afi_wdata_valid,                    --             .afi_wdata_valid
			afi_wdata               => afi_wdata,                          --             .afi_wdata
			afi_dm                  => afi_dm,                             --             .afi_dm
			afi_rdata               => afi_rdata,                          --             .afi_rdata
			afi_rst_n               => afi_rst_n,                          --             .afi_rst_n
			afi_mem_clk_disable     => afi_mem_clk_disable,                --             .afi_mem_clk_disable
			afi_init_req            => afi_init_req,                       --             .afi_init_req
			afi_cal_req             => afi_cal_req,                        --             .afi_cal_req
			afi_rdata_en            => afi_rdata_en,                       --             .afi_rdata_en
			afi_rdata_en_full       => afi_rdata_en_full,                  --             .afi_rdata_en_full
			afi_rdata_valid         => afi_rdata_valid,                    --             .afi_rdata_valid
			afi_cal_success         => afi_cal_success,                    --             .afi_cal_success
			afi_cal_fail            => afi_cal_fail,                       --             .afi_cal_fail
			afi_wlat                => afi_wlat,                           --             .afi_wlat
			afi_rlat                => afi_rlat,                           --             .afi_rlat
			csr_write_req           => '0',                                --  (terminated)
			csr_read_req            => '0',                                --  (terminated)
			csr_waitrequest         => open,                               --  (terminated)
			csr_addr                => "00000000",                         --  (terminated)
			csr_be                  => "0000",                             --  (terminated)
			csr_wdata               => "00000000000000000000000000000000", --  (terminated)
			csr_rdata               => open,                               --  (terminated)
			csr_rdata_valid         => open,                               --  (terminated)
			afi_seq_busy            => "0",                                --  (terminated)
			afi_ctl_refresh_done    => open,                               --  (terminated)
			afi_ctl_long_idle       => open,                               --  (terminated)
			afi_rrank               => open,                               --  (terminated)
			afi_wrank               => open,                               --  (terminated)
			local_multicast         => '0',                                --  (terminated)
			local_refresh_req       => '0',                                --  (terminated)
			local_refresh_chip      => "0",                                --  (terminated)
			local_refresh_ack       => open,                               --  (terminated)
			local_self_rfsh_req     => '0',                                --  (terminated)
			local_self_rfsh_chip    => "0",                                --  (terminated)
			local_self_rfsh_ack     => open,                               --  (terminated)
			local_deep_powerdn_req  => '0',                                --  (terminated)
			local_deep_powerdn_chip => "0",                                --  (terminated)
			local_deep_powerdn_ack  => open,                               --  (terminated)
			local_powerdn_ack       => open,                               --  (terminated)
			local_priority          => '0',                                --  (terminated)
			local_zqcal_req         => '0',                                --  (terminated)
			local_zqcal_chip        => "0"                                 --  (terminated)
		);

	a0 : component alt_mem_ddrx_mm_st_converter
		generic map (
			AVL_SIZE_WIDTH   => 3,
			AVL_ADDR_WIDTH   => 26,
			AVL_DATA_WIDTH   => 64,
			LOCAL_ID_WIDTH   => 8,
			CFG_DWIDTH_RATIO => 4
		)
		port map (
			ctl_clk               => afi_clk,                            --        afi_clk.clk
			ctl_reset_n           => afi_reset_n,                        --      afi_reset.reset_n
			ctl_half_clk          => afi_half_clk,                       --   afi_half_clk.clk
			ctl_half_clk_reset_n  => afi_reset_n,                        -- afi_half_reset.reset_n
			avl_ready             => avl_ready,                          --            avl.waitrequest_n
			avl_burstbegin        => avl_burstbegin,                     --               .beginbursttransfer
			avl_addr              => avl_addr,                           --               .address
			avl_rdata_valid       => avl_rdata_valid,                    --               .readdatavalid
			avl_rdata             => avl_rdata,                          --               .readdata
			avl_wdata             => avl_wdata,                          --               .writedata
			avl_be                => avl_be,                             --               .byteenable
			avl_read_req          => avl_read_req,                       --               .read
			avl_write_req         => avl_write_req,                      --               .write
			avl_size              => avl_size,                           --               .burstcount
			itf_cmd_ready         => ng0_native_st_itf_cmd_ready,        --      native_st.itf_cmd_ready
			itf_cmd_valid         => a0_native_st_itf_cmd_valid,         --               .itf_cmd_valid
			itf_cmd               => a0_native_st_itf_cmd,               --               .itf_cmd
			itf_cmd_address       => a0_native_st_itf_cmd_address,       --               .itf_cmd_address
			itf_cmd_burstlen      => a0_native_st_itf_cmd_burstlen,      --               .itf_cmd_burstlen
			itf_cmd_id            => a0_native_st_itf_cmd_id,            --               .itf_cmd_id
			itf_cmd_priority      => a0_native_st_itf_cmd_priority,      --               .itf_cmd_priority
			itf_cmd_autopercharge => a0_native_st_itf_cmd_autopercharge, --               .itf_cmd_autopercharge
			itf_cmd_multicast     => a0_native_st_itf_cmd_multicast,     --               .itf_cmd_multicast
			itf_wr_data_ready     => ng0_native_st_itf_wr_data_ready,    --               .itf_wr_data_ready
			itf_wr_data_valid     => a0_native_st_itf_wr_data_valid,     --               .itf_wr_data_valid
			itf_wr_data           => a0_native_st_itf_wr_data,           --               .itf_wr_data
			itf_wr_data_byte_en   => a0_native_st_itf_wr_data_byte_en,   --               .itf_wr_data_byte_en
			itf_wr_data_begin     => a0_native_st_itf_wr_data_begin,     --               .itf_wr_data_begin
			itf_wr_data_last      => a0_native_st_itf_wr_data_last,      --               .itf_wr_data_last
			itf_wr_data_id        => a0_native_st_itf_wr_data_id,        --               .itf_wr_data_id
			itf_rd_data_ready     => a0_native_st_itf_rd_data_ready,     --               .itf_rd_data_ready
			itf_rd_data_valid     => ng0_native_st_itf_rd_data_valid,    --               .itf_rd_data_valid
			itf_rd_data           => ng0_native_st_itf_rd_data,          --               .itf_rd_data
			itf_rd_data_error     => ng0_native_st_itf_rd_data_error,    --               .itf_rd_data_error
			itf_rd_data_begin     => ng0_native_st_itf_rd_data_begin,    --               .itf_rd_data_begin
			itf_rd_data_last      => ng0_native_st_itf_rd_data_last,     --               .itf_rd_data_last
			itf_rd_data_id        => ng0_native_st_itf_rd_data_id,       --               .itf_rd_data_id
			local_multicast       => '0',                                --    (terminated)
			local_autopch_req     => '0',                                --    (terminated)
			local_priority        => '0'                                 --    (terminated)
		);

end architecture rtl; -- of ddr3controller_c0
