-- ddr3controller_s0.vhd

-- This file was auto-generated from qsys_sequencer_110_hw.tcl.  If you edit it your changes
-- will probably be lost.
-- 
-- Generated using ACDS version 18.1 625

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity ddr3controller_s0 is
	port (
		avl_clk                     : in  std_logic                     := '0';             --          avl_clk.clk
		avl_reset_n                 : in  std_logic                     := '0';             --    sequencer_rst.reset
		pd_reset_n                  : out std_logic;                                        --   phase_detector.pd_reset_n
		pd_ack                      : out std_logic;                                        --                 .pd_ack
		pd_up                       : in  std_logic                     := '0';             --                 .pd_up
		pd_down                     : in  std_logic                     := '0';             --                 .pd_down
		phasecounterselect          : out std_logic_vector(2 downto 0);                     --     pll_reconfig.phasecounterselect
		phasestep                   : out std_logic;                                        --                 .phasestep
		phaseupdown                 : out std_logic;                                        --                 .phaseupdown
		scanclk                     : out std_logic;                                        --                 .scanclk
		phasedone                   : in  std_logic                     := '0';             --                 .phasedone
		phy_clk                     : in  std_logic                     := '0';             --              phy.phy_clk
		phy_reset_n                 : in  std_logic                     := '0';             --                 .phy_reset_n
		phy_read_latency_counter    : out std_logic_vector(4 downto 0);                     --                 .phy_read_latency_counter
		phy_afi_wlat                : out std_logic_vector(5 downto 0);                     --                 .phy_afi_wlat
		phy_afi_rlat                : out std_logic_vector(5 downto 0);                     --                 .phy_afi_rlat
		phy_read_increment_vfifo_fr : out std_logic_vector(1 downto 0);                     --                 .phy_read_increment_vfifo_fr
		phy_read_increment_vfifo_hr : out std_logic_vector(1 downto 0);                     --                 .phy_read_increment_vfifo_hr
		phy_read_increment_vfifo_qr : out std_logic_vector(1 downto 0);                     --                 .phy_read_increment_vfifo_qr
		phy_reset_mem_stable        : out std_logic;                                        --                 .phy_reset_mem_stable
		phy_cal_success             : out std_logic;                                        --                 .phy_cal_success
		phy_cal_fail                : out std_logic;                                        --                 .phy_cal_fail
		phy_cal_debug_info          : out std_logic_vector(31 downto 0);                    --                 .phy_cal_debug_info
		phy_read_fifo_reset         : out std_logic_vector(1 downto 0);                     --                 .phy_read_fifo_reset
		phy_vfifo_rd_en_override    : out std_logic_vector(1 downto 0);                     --                 .phy_vfifo_rd_en_override
		phy_read_fifo_q             : in  std_logic_vector(63 downto 0) := (others => '0'); --                 .phy_read_fifo_q
		phy_write_fr_cycle_shifts   : out std_logic_vector(3 downto 0);                     --                 .phy_write_fr_cycle_shifts
		phy_mux_sel                 : out std_logic;                                        --          mux_sel.mux_sel
		calib_skip_steps            : in  std_logic_vector(7 downto 0)  := (others => '0'); --            calib.calib_skip_steps
		afi_clk                     : in  std_logic                     := '0';             --          afi_clk.clk
		afi_reset_n                 : in  std_logic                     := '0';             --        afi_reset.reset_n
		afi_addr                    : out std_logic_vector(29 downto 0);                    --              afi.afi_addr
		afi_ba                      : out std_logic_vector(5 downto 0);                     --                 .afi_ba
		afi_cs_n                    : out std_logic_vector(1 downto 0);                     --                 .afi_cs_n
		afi_cke                     : out std_logic_vector(1 downto 0);                     --                 .afi_cke
		afi_odt                     : out std_logic_vector(1 downto 0);                     --                 .afi_odt
		afi_ras_n                   : out std_logic_vector(1 downto 0);                     --                 .afi_ras_n
		afi_cas_n                   : out std_logic_vector(1 downto 0);                     --                 .afi_cas_n
		afi_we_n                    : out std_logic_vector(1 downto 0);                     --                 .afi_we_n
		afi_dqs_burst               : out std_logic_vector(3 downto 0);                     --                 .afi_dqs_burst
		afi_rst_n                   : out std_logic_vector(1 downto 0);                     --                 .afi_rst_n
		afi_wdata                   : out std_logic_vector(63 downto 0);                    --                 .afi_wdata
		afi_wdata_valid             : out std_logic_vector(3 downto 0);                     --                 .afi_wdata_valid
		afi_dm                      : out std_logic_vector(7 downto 0);                     --                 .afi_dm
		afi_rdata_en                : out std_logic_vector(1 downto 0);                     --                 .afi_rdata_en
		afi_rdata_en_full           : out std_logic_vector(1 downto 0);                     --                 .afi_rdata_en_full
		afi_rdata                   : in  std_logic_vector(63 downto 0) := (others => '0'); --                 .afi_rdata
		afi_rdata_valid             : in  std_logic_vector(1 downto 0)  := (others => '0'); --                 .afi_rdata_valid
		afi_init_req                : in  std_logic                     := '0';             -- afi_init_cal_req.afi_init_req
		afi_cal_req                 : in  std_logic                     := '0'              --                 .afi_cal_req
	);
end entity ddr3controller_s0;

architecture rtl of ddr3controller_s0 is
	component altera_mem_if_sequencer_rst is
		generic (
			DEPTH            : integer := 8;
			CLKEN_LAGS_RESET : integer := 0
		);
		port (
			clk       : in  std_logic := 'X'; -- clk
			rst       : in  std_logic := 'X'; -- reset
			reset_out : out std_logic;        -- reset
			clken_out : out std_logic         -- clken
		);
	end component altera_mem_if_sequencer_rst;

	component sequencer_m10 is
		generic (
			AVL_DATA_WIDTH       : integer := 32;
			AVL_ADDR_WIDTH       : integer := 20;
			READ_VALID_FIFO_SIZE : integer := 4;
			HPS_PROTOCOL         : string  := "DDR3";
			PHY_MGR_BASE         : integer := 0;
			RW_MGR_BASE          : integer := 0;
			PLL_MGR_BASE         : integer := 0;
			MEM_DQ_WIDTH         : integer := 8
		);
		port (
			clk         : in  std_logic                     := 'X';             -- clk
			reset_n     : in  std_logic                     := 'X';             -- reset_n
			address     : out std_logic_vector(19 downto 0);                    -- address
			write       : out std_logic;                                        -- write
			writedata   : out std_logic_vector(31 downto 0);                    -- writedata
			read        : out std_logic;                                        -- read
			readdata    : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			waitrequest : in  std_logic                     := 'X';             -- waitrequest
			pd_reset_n  : out std_logic;                                        -- pd_reset_n
			pd_ack      : out std_logic;                                        -- pd_ack
			pd_up       : in  std_logic                     := 'X';             -- pd_up
			pd_down     : in  std_logic                     := 'X'              -- pd_down
		);
	end component sequencer_m10;

	component sequencer_pll_mgr is
		generic (
			AVL_DATA_WIDTH : integer := 32;
			AVL_ADDR_WIDTH : integer := 1
		);
		port (
			avl_clk            : in  std_logic                     := 'X';             -- clk
			avl_reset_n        : in  std_logic                     := 'X';             -- reset_n
			avl_address        : in  std_logic_vector(12 downto 0) := (others => 'X'); -- address
			avl_write          : in  std_logic                     := 'X';             -- write
			avl_writedata      : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			avl_read           : in  std_logic                     := 'X';             -- read
			avl_readdata       : out std_logic_vector(31 downto 0);                    -- readdata
			avl_waitrequest    : out std_logic;                                        -- waitrequest
			phasecounterselect : out std_logic_vector(2 downto 0);                     -- phasecounterselect
			phasestep          : out std_logic;                                        -- phasestep
			phaseupdown        : out std_logic;                                        -- phaseupdown
			scanclk            : out std_logic;                                        -- scanclk
			phasedone          : in  std_logic                     := 'X';             -- phasedone
			afi_init_req       : in  std_logic                     := 'X';             -- afi_init_req
			afi_cal_req        : in  std_logic                     := 'X'              -- afi_cal_req
		);
	end component sequencer_pll_mgr;

	component sequencer_phy_mgr is
		generic (
			AVL_DATA_WIDTH                    : integer := 32;
			AVL_ADDR_WIDTH                    : integer := 13;
			MAX_LATENCY_COUNT_WIDTH           : integer := 5;
			MEM_IF_READ_DQS_WIDTH             : integer := 1;
			MEM_IF_WRITE_DQS_WIDTH            : integer := 1;
			AFI_DQ_WIDTH                      : integer := 64;
			AFI_DEBUG_INFO_WIDTH              : integer := 32;
			AFI_MAX_WRITE_LATENCY_COUNT_WIDTH : integer := 5;
			AFI_MAX_READ_LATENCY_COUNT_WIDTH  : integer := 5;
			CALIB_VFIFO_OFFSET                : integer := 14;
			CALIB_LFIFO_OFFSET                : integer := 5;
			CALIB_REG_WIDTH                   : integer := 8;
			READ_VALID_FIFO_SIZE              : integer := 16;
			MEM_T_WL                          : integer := 5;
			MEM_T_RL                          : integer := 7;
			CTL_REGDIMM_ENABLED               : boolean := false;
			NUM_WRITE_FR_CYCLE_SHIFTS         : integer := 0;
			VFIFO_CONTROL_WIDTH_PER_DQS       : integer := 1;
			DEVICE_FAMILY                     : string  := ""
		);
		port (
			avl_clk                     : in  std_logic                     := 'X';             -- clk
			avl_reset_n                 : in  std_logic                     := 'X';             -- reset_n
			avl_address                 : in  std_logic_vector(12 downto 0) := (others => 'X'); -- address
			avl_write                   : in  std_logic                     := 'X';             -- write
			avl_writedata               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			avl_read                    : in  std_logic                     := 'X';             -- read
			avl_readdata                : out std_logic_vector(31 downto 0);                    -- readdata
			avl_waitrequest             : out std_logic;                                        -- waitrequest
			phy_clk                     : in  std_logic                     := 'X';             -- phy_clk
			phy_reset_n                 : in  std_logic                     := 'X';             -- phy_reset_n
			phy_read_latency_counter    : out std_logic_vector(4 downto 0);                     -- phy_read_latency_counter
			phy_afi_wlat                : out std_logic_vector(5 downto 0);                     -- phy_afi_wlat
			phy_afi_rlat                : out std_logic_vector(5 downto 0);                     -- phy_afi_rlat
			phy_read_increment_vfifo_fr : out std_logic_vector(1 downto 0);                     -- phy_read_increment_vfifo_fr
			phy_read_increment_vfifo_hr : out std_logic_vector(1 downto 0);                     -- phy_read_increment_vfifo_hr
			phy_read_increment_vfifo_qr : out std_logic_vector(1 downto 0);                     -- phy_read_increment_vfifo_qr
			phy_reset_mem_stable        : out std_logic;                                        -- phy_reset_mem_stable
			phy_cal_success             : out std_logic;                                        -- phy_cal_success
			phy_cal_fail                : out std_logic;                                        -- phy_cal_fail
			phy_cal_debug_info          : out std_logic_vector(31 downto 0);                    -- phy_cal_debug_info
			phy_read_fifo_reset         : out std_logic_vector(1 downto 0);                     -- phy_read_fifo_reset
			phy_vfifo_rd_en_override    : out std_logic_vector(1 downto 0);                     -- phy_vfifo_rd_en_override
			phy_read_fifo_q             : in  std_logic_vector(63 downto 0) := (others => 'X'); -- phy_read_fifo_q
			phy_write_fr_cycle_shifts   : out std_logic_vector(3 downto 0);                     -- phy_write_fr_cycle_shifts
			calib_skip_steps            : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- calib_skip_steps
			phy_mux_sel                 : out std_logic                                         -- mux_sel
		);
	end component sequencer_phy_mgr;

	component rw_manager_ddr3 is
		generic (
			RATE                                 : string                       := "Half";
			AVL_DATA_WIDTH                       : integer                      := 32;
			AVL_ADDR_WIDTH                       : integer                      := 13;
			MEM_ADDRESS_WIDTH                    : integer                      := 1;
			MEM_CONTROL_WIDTH                    : integer                      := 1;
			MEM_DQ_WIDTH                         : integer                      := 1;
			MEM_DM_WIDTH                         : integer                      := 1;
			MEM_NUMBER_OF_RANKS                  : integer                      := 1;
			MEM_CLK_EN_WIDTH                     : integer                      := 1;
			MEM_BANK_WIDTH                       : integer                      := 1;
			MEM_ODT_WIDTH                        : integer                      := 1;
			MEM_CHIP_SELECT_WIDTH                : integer                      := 1;
			MEM_READ_DQS_WIDTH                   : integer                      := 1;
			MEM_WRITE_DQS_WIDTH                  : integer                      := 1;
			AFI_RATIO                            : integer                      := 2;
			AC_BUS_WIDTH                         : integer                      := 27;
			HCX_COMPAT_MODE                      : boolean                      := false;
			DEVICE_FAMILY                        : string                       := "STRATIXIII";
			AC_ROM_INIT_FILE_NAME                : string                       := "AC_ROM.hex";
			INST_ROM_INIT_FILE_NAME              : string                       := "inst_ROM.hex";
			DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT : integer                      := 0;
			DEBUG_WRITE_TO_READ_RATIO            : integer                      := 0;
			MAX_DI_BUFFER_WORDS_LOG_2            : integer                      := 2;
			AP_MODE_EN                           : std_logic_vector(1 downto 0) := "00";
			AVL_CLK_PS                           : integer                      := 1000;
			AFI_CLK_PS                           : integer                      := 1000;
			ENABLE_NON_DES_CAL                   : boolean                      := true;
			TREFI                                : integer                      := 35100;
			REFRESH_INTERVAL                     : integer                      := 28000;
			TRFC                                 : integer                      := 350
		);
		port (
			avl_clk           : in  std_logic                     := 'X';             -- clk
			avl_reset_n       : in  std_logic                     := 'X';             -- reset_n
			avl_address       : in  std_logic_vector(12 downto 0) := (others => 'X'); -- address
			avl_write         : in  std_logic                     := 'X';             -- write
			avl_writedata     : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			avl_read          : in  std_logic                     := 'X';             -- read
			avl_readdata      : out std_logic_vector(31 downto 0);                    -- readdata
			avl_waitrequest   : out std_logic;                                        -- waitrequest
			afi_clk           : in  std_logic                     := 'X';             -- clk
			afi_reset_n       : in  std_logic                     := 'X';             -- reset_n
			afi_addr          : out std_logic_vector(29 downto 0);                    -- afi_addr
			afi_ba            : out std_logic_vector(5 downto 0);                     -- afi_ba
			afi_cs_n          : out std_logic_vector(1 downto 0);                     -- afi_cs_n
			afi_cke           : out std_logic_vector(1 downto 0);                     -- afi_cke
			afi_odt           : out std_logic_vector(1 downto 0);                     -- afi_odt
			afi_ras_n         : out std_logic_vector(1 downto 0);                     -- afi_ras_n
			afi_cas_n         : out std_logic_vector(1 downto 0);                     -- afi_cas_n
			afi_we_n          : out std_logic_vector(1 downto 0);                     -- afi_we_n
			afi_dqs_burst     : out std_logic_vector(3 downto 0);                     -- afi_dqs_burst
			afi_rst_n         : out std_logic_vector(1 downto 0);                     -- afi_rst_n
			afi_wdata         : out std_logic_vector(63 downto 0);                    -- afi_wdata
			afi_wdata_valid   : out std_logic_vector(3 downto 0);                     -- afi_wdata_valid
			afi_dm            : out std_logic_vector(7 downto 0);                     -- afi_dm
			afi_rdata_en      : out std_logic_vector(1 downto 0);                     -- afi_rdata_en
			afi_rdata_en_full : out std_logic_vector(1 downto 0);                     -- afi_rdata_en_full
			afi_rdata         : in  std_logic_vector(63 downto 0) := (others => 'X'); -- afi_rdata
			afi_rdata_valid   : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_valid
			csr_clk           : in  std_logic                     := 'X';             -- csr_clk
			csr_ena           : in  std_logic                     := 'X';             -- csr_ena
			csr_dout_phy      : in  std_logic                     := 'X';             -- csr_dout_phy
			csr_dout          : out std_logic;                                        -- csr_dout
			afi_rrank         : out std_logic_vector(3 downto 0);                     -- afi_rrank
			afi_wrank         : out std_logic_vector(3 downto 0)                      -- afi_wrank
		);
	end component rw_manager_ddr3;

	component ddr3controller_s0_mm_interconnect_0 is
		port (
			avl_clk_out_clk_clk                                          : in  std_logic                     := 'X';             -- clk
			cpu_inst_reset_n_reset_bridge_in_reset_reset                 : in  std_logic                     := 'X';             -- reset
			sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset : in  std_logic                     := 'X';             -- reset
			cpu_inst_data_master_address                                 : in  std_logic_vector(19 downto 0) := (others => 'X'); -- address
			cpu_inst_data_master_waitrequest                             : out std_logic;                                        -- waitrequest
			cpu_inst_data_master_read                                    : in  std_logic                     := 'X';             -- read
			cpu_inst_data_master_readdata                                : out std_logic_vector(31 downto 0);                    -- readdata
			cpu_inst_data_master_write                                   : in  std_logic                     := 'X';             -- write
			cpu_inst_data_master_writedata                               : in  std_logic_vector(31 downto 0) := (others => 'X'); -- writedata
			sequencer_phy_mgr_inst_avl_address                           : out std_logic_vector(12 downto 0);                    -- address
			sequencer_phy_mgr_inst_avl_write                             : out std_logic;                                        -- write
			sequencer_phy_mgr_inst_avl_read                              : out std_logic;                                        -- read
			sequencer_phy_mgr_inst_avl_readdata                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			sequencer_phy_mgr_inst_avl_writedata                         : out std_logic_vector(31 downto 0);                    -- writedata
			sequencer_phy_mgr_inst_avl_waitrequest                       : in  std_logic                     := 'X';             -- waitrequest
			sequencer_pll_mgr_inst_avl_address                           : out std_logic_vector(12 downto 0);                    -- address
			sequencer_pll_mgr_inst_avl_write                             : out std_logic;                                        -- write
			sequencer_pll_mgr_inst_avl_read                              : out std_logic;                                        -- read
			sequencer_pll_mgr_inst_avl_readdata                          : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			sequencer_pll_mgr_inst_avl_writedata                         : out std_logic_vector(31 downto 0);                    -- writedata
			sequencer_pll_mgr_inst_avl_waitrequest                       : in  std_logic                     := 'X';             -- waitrequest
			sequencer_rw_mgr_inst_avl_address                            : out std_logic_vector(12 downto 0);                    -- address
			sequencer_rw_mgr_inst_avl_write                              : out std_logic;                                        -- write
			sequencer_rw_mgr_inst_avl_read                               : out std_logic;                                        -- read
			sequencer_rw_mgr_inst_avl_readdata                           : in  std_logic_vector(31 downto 0) := (others => 'X'); -- readdata
			sequencer_rw_mgr_inst_avl_writedata                          : out std_logic_vector(31 downto 0);                    -- writedata
			sequencer_rw_mgr_inst_avl_waitrequest                        : in  std_logic                     := 'X'              -- waitrequest
		);
	end component ddr3controller_s0_mm_interconnect_0;

	signal sequencer_rst_reset_out_reset                            : std_logic;                     -- sequencer_rst:reset_out -> [mm_interconnect_0:cpu_inst_reset_n_reset_bridge_in_reset_reset, mm_interconnect_0:sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset, sequencer_rst_reset_out_reset:in]
	signal cpu_inst_data_master_readdata                            : std_logic_vector(31 downto 0); -- mm_interconnect_0:cpu_inst_data_master_readdata -> cpu_inst:readdata
	signal cpu_inst_data_master_waitrequest                         : std_logic;                     -- mm_interconnect_0:cpu_inst_data_master_waitrequest -> cpu_inst:waitrequest
	signal cpu_inst_data_master_address                             : std_logic_vector(19 downto 0); -- cpu_inst:address -> mm_interconnect_0:cpu_inst_data_master_address
	signal cpu_inst_data_master_read                                : std_logic;                     -- cpu_inst:read -> mm_interconnect_0:cpu_inst_data_master_read
	signal cpu_inst_data_master_write                               : std_logic;                     -- cpu_inst:write -> mm_interconnect_0:cpu_inst_data_master_write
	signal cpu_inst_data_master_writedata                           : std_logic_vector(31 downto 0); -- cpu_inst:writedata -> mm_interconnect_0:cpu_inst_data_master_writedata
	signal mm_interconnect_0_sequencer_phy_mgr_inst_avl_readdata    : std_logic_vector(31 downto 0); -- sequencer_phy_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_phy_mgr_inst_avl_readdata
	signal mm_interconnect_0_sequencer_phy_mgr_inst_avl_waitrequest : std_logic;                     -- sequencer_phy_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_phy_mgr_inst_avl_waitrequest
	signal mm_interconnect_0_sequencer_phy_mgr_inst_avl_address     : std_logic_vector(12 downto 0); -- mm_interconnect_0:sequencer_phy_mgr_inst_avl_address -> sequencer_phy_mgr_inst:avl_address
	signal mm_interconnect_0_sequencer_phy_mgr_inst_avl_read        : std_logic;                     -- mm_interconnect_0:sequencer_phy_mgr_inst_avl_read -> sequencer_phy_mgr_inst:avl_read
	signal mm_interconnect_0_sequencer_phy_mgr_inst_avl_write       : std_logic;                     -- mm_interconnect_0:sequencer_phy_mgr_inst_avl_write -> sequencer_phy_mgr_inst:avl_write
	signal mm_interconnect_0_sequencer_phy_mgr_inst_avl_writedata   : std_logic_vector(31 downto 0); -- mm_interconnect_0:sequencer_phy_mgr_inst_avl_writedata -> sequencer_phy_mgr_inst:avl_writedata
	signal mm_interconnect_0_sequencer_rw_mgr_inst_avl_readdata     : std_logic_vector(31 downto 0); -- sequencer_rw_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_rw_mgr_inst_avl_readdata
	signal mm_interconnect_0_sequencer_rw_mgr_inst_avl_waitrequest  : std_logic;                     -- sequencer_rw_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_rw_mgr_inst_avl_waitrequest
	signal mm_interconnect_0_sequencer_rw_mgr_inst_avl_address      : std_logic_vector(12 downto 0); -- mm_interconnect_0:sequencer_rw_mgr_inst_avl_address -> sequencer_rw_mgr_inst:avl_address
	signal mm_interconnect_0_sequencer_rw_mgr_inst_avl_read         : std_logic;                     -- mm_interconnect_0:sequencer_rw_mgr_inst_avl_read -> sequencer_rw_mgr_inst:avl_read
	signal mm_interconnect_0_sequencer_rw_mgr_inst_avl_write        : std_logic;                     -- mm_interconnect_0:sequencer_rw_mgr_inst_avl_write -> sequencer_rw_mgr_inst:avl_write
	signal mm_interconnect_0_sequencer_rw_mgr_inst_avl_writedata    : std_logic_vector(31 downto 0); -- mm_interconnect_0:sequencer_rw_mgr_inst_avl_writedata -> sequencer_rw_mgr_inst:avl_writedata
	signal mm_interconnect_0_sequencer_pll_mgr_inst_avl_readdata    : std_logic_vector(31 downto 0); -- sequencer_pll_mgr_inst:avl_readdata -> mm_interconnect_0:sequencer_pll_mgr_inst_avl_readdata
	signal mm_interconnect_0_sequencer_pll_mgr_inst_avl_waitrequest : std_logic;                     -- sequencer_pll_mgr_inst:avl_waitrequest -> mm_interconnect_0:sequencer_pll_mgr_inst_avl_waitrequest
	signal mm_interconnect_0_sequencer_pll_mgr_inst_avl_address     : std_logic_vector(12 downto 0); -- mm_interconnect_0:sequencer_pll_mgr_inst_avl_address -> sequencer_pll_mgr_inst:avl_address
	signal mm_interconnect_0_sequencer_pll_mgr_inst_avl_read        : std_logic;                     -- mm_interconnect_0:sequencer_pll_mgr_inst_avl_read -> sequencer_pll_mgr_inst:avl_read
	signal mm_interconnect_0_sequencer_pll_mgr_inst_avl_write       : std_logic;                     -- mm_interconnect_0:sequencer_pll_mgr_inst_avl_write -> sequencer_pll_mgr_inst:avl_write
	signal mm_interconnect_0_sequencer_pll_mgr_inst_avl_writedata   : std_logic_vector(31 downto 0); -- mm_interconnect_0:sequencer_pll_mgr_inst_avl_writedata -> sequencer_pll_mgr_inst:avl_writedata
	signal sequencer_rst_reset_out_reset_ports_inv                  : std_logic;                     -- sequencer_rst_reset_out_reset:inv -> [cpu_inst:reset_n, sequencer_phy_mgr_inst:avl_reset_n, sequencer_pll_mgr_inst:avl_reset_n, sequencer_rw_mgr_inst:avl_reset_n]

begin

	sequencer_rst : component altera_mem_if_sequencer_rst
		generic map (
			DEPTH            => 10,
			CLKEN_LAGS_RESET => 0
		)
		port map (
			clk       => avl_clk,                       --       clk.clk
			rst       => avl_reset_n,                   --       rst.reset
			reset_out => sequencer_rst_reset_out_reset, -- reset_out.reset
			clken_out => open                           -- clken_out.clken
		);

	cpu_inst : component sequencer_m10
		generic map (
			AVL_DATA_WIDTH       => 32,
			AVL_ADDR_WIDTH       => 20,
			READ_VALID_FIFO_SIZE => 16,
			HPS_PROTOCOL         => "DDR3",
			PHY_MGR_BASE         => 294912,
			RW_MGR_BASE          => 327680,
			PLL_MGR_BASE         => 360448,
			MEM_DQ_WIDTH         => 16
		)
		port map (
			clk         => avl_clk,                                 --            clk.clk
			reset_n     => sequencer_rst_reset_out_reset_ports_inv, --        reset_n.reset_n
			address     => cpu_inst_data_master_address,            --    data_master.address
			write       => cpu_inst_data_master_write,              --               .write
			writedata   => cpu_inst_data_master_writedata,          --               .writedata
			read        => cpu_inst_data_master_read,               --               .read
			readdata    => cpu_inst_data_master_readdata,           --               .readdata
			waitrequest => cpu_inst_data_master_waitrequest,        --               .waitrequest
			pd_reset_n  => pd_reset_n,                              -- phase_detector.pd_reset_n
			pd_ack      => pd_ack,                                  --               .pd_ack
			pd_up       => pd_up,                                   --               .pd_up
			pd_down     => pd_down                                  --               .pd_down
		);

	sequencer_pll_mgr_inst : component sequencer_pll_mgr
		generic map (
			AVL_DATA_WIDTH => 32,
			AVL_ADDR_WIDTH => 13
		)
		port map (
			avl_clk            => avl_clk,                                                  --          avl_clk.clk
			avl_reset_n        => sequencer_rst_reset_out_reset_ports_inv,                  --        avl_reset.reset_n
			avl_address        => mm_interconnect_0_sequencer_pll_mgr_inst_avl_address,     --              avl.address
			avl_write          => mm_interconnect_0_sequencer_pll_mgr_inst_avl_write,       --                 .write
			avl_writedata      => mm_interconnect_0_sequencer_pll_mgr_inst_avl_writedata,   --                 .writedata
			avl_read           => mm_interconnect_0_sequencer_pll_mgr_inst_avl_read,        --                 .read
			avl_readdata       => mm_interconnect_0_sequencer_pll_mgr_inst_avl_readdata,    --                 .readdata
			avl_waitrequest    => mm_interconnect_0_sequencer_pll_mgr_inst_avl_waitrequest, --                 .waitrequest
			phasecounterselect => phasecounterselect,                                       --     pll_reconfig.phasecounterselect
			phasestep          => phasestep,                                                --                 .phasestep
			phaseupdown        => phaseupdown,                                              --                 .phaseupdown
			scanclk            => scanclk,                                                  --                 .scanclk
			phasedone          => phasedone,                                                --                 .phasedone
			afi_init_req       => afi_init_req,                                             -- afi_init_cal_req.afi_init_req
			afi_cal_req        => afi_cal_req                                               --                 .afi_cal_req
		);

	sequencer_phy_mgr_inst : component sequencer_phy_mgr
		generic map (
			AVL_DATA_WIDTH                    => 32,
			AVL_ADDR_WIDTH                    => 13,
			MAX_LATENCY_COUNT_WIDTH           => 5,
			MEM_IF_READ_DQS_WIDTH             => 2,
			MEM_IF_WRITE_DQS_WIDTH            => 2,
			AFI_DQ_WIDTH                      => 64,
			AFI_DEBUG_INFO_WIDTH              => 32,
			AFI_MAX_WRITE_LATENCY_COUNT_WIDTH => 6,
			AFI_MAX_READ_LATENCY_COUNT_WIDTH  => 6,
			CALIB_VFIFO_OFFSET                => 14,
			CALIB_LFIFO_OFFSET                => 5,
			CALIB_REG_WIDTH                   => 8,
			READ_VALID_FIFO_SIZE              => 16,
			MEM_T_WL                          => 6,
			MEM_T_RL                          => 7,
			CTL_REGDIMM_ENABLED               => false,
			NUM_WRITE_FR_CYCLE_SHIFTS         => 0,
			VFIFO_CONTROL_WIDTH_PER_DQS       => 1,
			DEVICE_FAMILY                     => "MAX10"
		)
		port map (
			avl_clk                     => avl_clk,                                                  --   avl_clk.clk
			avl_reset_n                 => sequencer_rst_reset_out_reset_ports_inv,                  -- avl_reset.reset_n
			avl_address                 => mm_interconnect_0_sequencer_phy_mgr_inst_avl_address,     --       avl.address
			avl_write                   => mm_interconnect_0_sequencer_phy_mgr_inst_avl_write,       --          .write
			avl_writedata               => mm_interconnect_0_sequencer_phy_mgr_inst_avl_writedata,   --          .writedata
			avl_read                    => mm_interconnect_0_sequencer_phy_mgr_inst_avl_read,        --          .read
			avl_readdata                => mm_interconnect_0_sequencer_phy_mgr_inst_avl_readdata,    --          .readdata
			avl_waitrequest             => mm_interconnect_0_sequencer_phy_mgr_inst_avl_waitrequest, --          .waitrequest
			phy_clk                     => phy_clk,                                                  --       phy.phy_clk
			phy_reset_n                 => phy_reset_n,                                              --          .phy_reset_n
			phy_read_latency_counter    => phy_read_latency_counter,                                 --          .phy_read_latency_counter
			phy_afi_wlat                => phy_afi_wlat,                                             --          .phy_afi_wlat
			phy_afi_rlat                => phy_afi_rlat,                                             --          .phy_afi_rlat
			phy_read_increment_vfifo_fr => phy_read_increment_vfifo_fr,                              --          .phy_read_increment_vfifo_fr
			phy_read_increment_vfifo_hr => phy_read_increment_vfifo_hr,                              --          .phy_read_increment_vfifo_hr
			phy_read_increment_vfifo_qr => phy_read_increment_vfifo_qr,                              --          .phy_read_increment_vfifo_qr
			phy_reset_mem_stable        => phy_reset_mem_stable,                                     --          .phy_reset_mem_stable
			phy_cal_success             => phy_cal_success,                                          --          .phy_cal_success
			phy_cal_fail                => phy_cal_fail,                                             --          .phy_cal_fail
			phy_cal_debug_info          => phy_cal_debug_info,                                       --          .phy_cal_debug_info
			phy_read_fifo_reset         => phy_read_fifo_reset,                                      --          .phy_read_fifo_reset
			phy_vfifo_rd_en_override    => phy_vfifo_rd_en_override,                                 --          .phy_vfifo_rd_en_override
			phy_read_fifo_q             => phy_read_fifo_q,                                          --          .phy_read_fifo_q
			phy_write_fr_cycle_shifts   => phy_write_fr_cycle_shifts,                                --          .phy_write_fr_cycle_shifts
			calib_skip_steps            => calib_skip_steps,                                         --     calib.calib_skip_steps
			phy_mux_sel                 => phy_mux_sel                                               --   mux_sel.mux_sel
		);

	sequencer_rw_mgr_inst : component rw_manager_ddr3
		generic map (
			RATE                                 => "Half",
			AVL_DATA_WIDTH                       => 32,
			AVL_ADDR_WIDTH                       => 13,
			MEM_ADDRESS_WIDTH                    => 15,
			MEM_CONTROL_WIDTH                    => 1,
			MEM_DQ_WIDTH                         => 16,
			MEM_DM_WIDTH                         => 2,
			MEM_NUMBER_OF_RANKS                  => 1,
			MEM_CLK_EN_WIDTH                     => 1,
			MEM_BANK_WIDTH                       => 3,
			MEM_ODT_WIDTH                        => 1,
			MEM_CHIP_SELECT_WIDTH                => 1,
			MEM_READ_DQS_WIDTH                   => 2,
			MEM_WRITE_DQS_WIDTH                  => 2,
			AFI_RATIO                            => 2,
			AC_BUS_WIDTH                         => 27,
			HCX_COMPAT_MODE                      => false,
			DEVICE_FAMILY                        => "MAX10",
			AC_ROM_INIT_FILE_NAME                => "ddr3controller_s0_AC_ROM.hex",
			INST_ROM_INIT_FILE_NAME              => "ddr3controller_s0_inst_ROM.hex",
			DEBUG_WRITE_TO_READ_RATIO_2_EXPONENT => 0,
			DEBUG_WRITE_TO_READ_RATIO            => 1,
			MAX_DI_BUFFER_WORDS_LOG_2            => 2,
			AP_MODE_EN                           => "00",
			AVL_CLK_PS                           => 6667,
			AFI_CLK_PS                           => 6667,
			ENABLE_NON_DES_CAL                   => false,
			TREFI                                => 35100,
			REFRESH_INTERVAL                     => 15000,
			TRFC                                 => 350
		)
		port map (
			avl_clk           => avl_clk,                                                 --   avl_clk.clk
			avl_reset_n       => sequencer_rst_reset_out_reset_ports_inv,                 -- avl_reset.reset_n
			avl_address       => mm_interconnect_0_sequencer_rw_mgr_inst_avl_address,     --       avl.address
			avl_write         => mm_interconnect_0_sequencer_rw_mgr_inst_avl_write,       --          .write
			avl_writedata     => mm_interconnect_0_sequencer_rw_mgr_inst_avl_writedata,   --          .writedata
			avl_read          => mm_interconnect_0_sequencer_rw_mgr_inst_avl_read,        --          .read
			avl_readdata      => mm_interconnect_0_sequencer_rw_mgr_inst_avl_readdata,    --          .readdata
			avl_waitrequest   => mm_interconnect_0_sequencer_rw_mgr_inst_avl_waitrequest, --          .waitrequest
			afi_clk           => afi_clk,                                                 --   afi_clk.clk
			afi_reset_n       => afi_reset_n,                                             -- afi_reset.reset_n
			afi_addr          => afi_addr,                                                --       afi.afi_addr
			afi_ba            => afi_ba,                                                  --          .afi_ba
			afi_cs_n          => afi_cs_n,                                                --          .afi_cs_n
			afi_cke           => afi_cke,                                                 --          .afi_cke
			afi_odt           => afi_odt,                                                 --          .afi_odt
			afi_ras_n         => afi_ras_n,                                               --          .afi_ras_n
			afi_cas_n         => afi_cas_n,                                               --          .afi_cas_n
			afi_we_n          => afi_we_n,                                                --          .afi_we_n
			afi_dqs_burst     => afi_dqs_burst,                                           --          .afi_dqs_burst
			afi_rst_n         => afi_rst_n,                                               --          .afi_rst_n
			afi_wdata         => afi_wdata,                                               --          .afi_wdata
			afi_wdata_valid   => afi_wdata_valid,                                         --          .afi_wdata_valid
			afi_dm            => afi_dm,                                                  --          .afi_dm
			afi_rdata_en      => afi_rdata_en,                                            --          .afi_rdata_en
			afi_rdata_en_full => afi_rdata_en_full,                                       --          .afi_rdata_en_full
			afi_rdata         => afi_rdata,                                               --          .afi_rdata
			afi_rdata_valid   => afi_rdata_valid,                                         --          .afi_rdata_valid
			csr_clk           => open,                                                    --       csr.csr_clk
			csr_ena           => open,                                                    --          .csr_ena
			csr_dout_phy      => open,                                                    --          .csr_dout_phy
			csr_dout          => open,                                                    --          .csr_dout
			afi_rrank         => open,                                                    -- (terminated)
			afi_wrank         => open                                                     -- (terminated)
		);

	mm_interconnect_0 : component ddr3controller_s0_mm_interconnect_0
		port map (
			avl_clk_out_clk_clk                                          => avl_clk,                                                  --                                        avl_clk_out_clk.clk
			cpu_inst_reset_n_reset_bridge_in_reset_reset                 => sequencer_rst_reset_out_reset,                            --                 cpu_inst_reset_n_reset_bridge_in_reset.reset
			sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset_reset => sequencer_rst_reset_out_reset,                            -- sequencer_phy_mgr_inst_avl_reset_reset_bridge_in_reset.reset
			cpu_inst_data_master_address                                 => cpu_inst_data_master_address,                             --                                   cpu_inst_data_master.address
			cpu_inst_data_master_waitrequest                             => cpu_inst_data_master_waitrequest,                         --                                                       .waitrequest
			cpu_inst_data_master_read                                    => cpu_inst_data_master_read,                                --                                                       .read
			cpu_inst_data_master_readdata                                => cpu_inst_data_master_readdata,                            --                                                       .readdata
			cpu_inst_data_master_write                                   => cpu_inst_data_master_write,                               --                                                       .write
			cpu_inst_data_master_writedata                               => cpu_inst_data_master_writedata,                           --                                                       .writedata
			sequencer_phy_mgr_inst_avl_address                           => mm_interconnect_0_sequencer_phy_mgr_inst_avl_address,     --                             sequencer_phy_mgr_inst_avl.address
			sequencer_phy_mgr_inst_avl_write                             => mm_interconnect_0_sequencer_phy_mgr_inst_avl_write,       --                                                       .write
			sequencer_phy_mgr_inst_avl_read                              => mm_interconnect_0_sequencer_phy_mgr_inst_avl_read,        --                                                       .read
			sequencer_phy_mgr_inst_avl_readdata                          => mm_interconnect_0_sequencer_phy_mgr_inst_avl_readdata,    --                                                       .readdata
			sequencer_phy_mgr_inst_avl_writedata                         => mm_interconnect_0_sequencer_phy_mgr_inst_avl_writedata,   --                                                       .writedata
			sequencer_phy_mgr_inst_avl_waitrequest                       => mm_interconnect_0_sequencer_phy_mgr_inst_avl_waitrequest, --                                                       .waitrequest
			sequencer_pll_mgr_inst_avl_address                           => mm_interconnect_0_sequencer_pll_mgr_inst_avl_address,     --                             sequencer_pll_mgr_inst_avl.address
			sequencer_pll_mgr_inst_avl_write                             => mm_interconnect_0_sequencer_pll_mgr_inst_avl_write,       --                                                       .write
			sequencer_pll_mgr_inst_avl_read                              => mm_interconnect_0_sequencer_pll_mgr_inst_avl_read,        --                                                       .read
			sequencer_pll_mgr_inst_avl_readdata                          => mm_interconnect_0_sequencer_pll_mgr_inst_avl_readdata,    --                                                       .readdata
			sequencer_pll_mgr_inst_avl_writedata                         => mm_interconnect_0_sequencer_pll_mgr_inst_avl_writedata,   --                                                       .writedata
			sequencer_pll_mgr_inst_avl_waitrequest                       => mm_interconnect_0_sequencer_pll_mgr_inst_avl_waitrequest, --                                                       .waitrequest
			sequencer_rw_mgr_inst_avl_address                            => mm_interconnect_0_sequencer_rw_mgr_inst_avl_address,      --                              sequencer_rw_mgr_inst_avl.address
			sequencer_rw_mgr_inst_avl_write                              => mm_interconnect_0_sequencer_rw_mgr_inst_avl_write,        --                                                       .write
			sequencer_rw_mgr_inst_avl_read                               => mm_interconnect_0_sequencer_rw_mgr_inst_avl_read,         --                                                       .read
			sequencer_rw_mgr_inst_avl_readdata                           => mm_interconnect_0_sequencer_rw_mgr_inst_avl_readdata,     --                                                       .readdata
			sequencer_rw_mgr_inst_avl_writedata                          => mm_interconnect_0_sequencer_rw_mgr_inst_avl_writedata,    --                                                       .writedata
			sequencer_rw_mgr_inst_avl_waitrequest                        => mm_interconnect_0_sequencer_rw_mgr_inst_avl_waitrequest   --                                                       .waitrequest
		);

	sequencer_rst_reset_out_reset_ports_inv <= not sequencer_rst_reset_out_reset;

end architecture rtl; -- of ddr3controller_s0
