--altsyncram ADDRESS_ACLR_A="NONE" ADDRESS_ACLR_B="NONE" ADDRESS_REG_B="CLOCK0" CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" CYCLONEII_M4K_COMPATIBILITY="ON" DEVICE_FAMILY="MAX 10" INDATA_ACLR_A="NONE" LOW_POWER_MODE="AUTO" NUMWORDS_A=128 NUMWORDS_B=128 OPERATION_MODE="DUAL_PORT" OUTDATA_ACLR_B="NONE" OUTDATA_REG_B="UNREGISTERED" POWER_UP_UNINITIALIZED="FALSE" READ_DURING_WRITE_MODE_MIXED_PORTS="DONT_CARE" WIDTH_A=65 WIDTH_B=65 WIDTH_BYTEENA_A=1 WIDTHAD_A=7 WIDTHAD_B=7 WRCONTROL_ACLR_A="NONE" address_a address_b clock0 data_a q_b wren_a CARRY_CHAIN="MANUAL" CARRY_CHAIN_LENGTH=48
--VERSION_BEGIN 18.1 cbx_altera_syncram_nd_impl 2018:09:12:13:04:09:SJ cbx_altsyncram 2018:09:12:13:04:09:SJ cbx_cycloneii 2018:09:12:13:04:09:SJ cbx_lpm_add_sub 2018:09:12:13:04:09:SJ cbx_lpm_compare 2018:09:12:13:04:09:SJ cbx_lpm_decode 2018:09:12:13:04:09:SJ cbx_lpm_mux 2018:09:12:13:04:09:SJ cbx_mgl 2018:09:12:14:15:07:SJ cbx_nadder 2018:09:12:13:04:09:SJ cbx_stratix 2018:09:12:13:04:09:SJ cbx_stratixii 2018:09:12:13:04:09:SJ cbx_stratixiii 2018:09:12:13:04:09:SJ cbx_stratixv 2018:09:12:13:04:09:SJ cbx_util_mgl 2018:09:12:13:04:09:SJ  VERSION_END


-- Copyright (C) 2018  Intel Corporation. All rights reserved.
--  Your use of Intel Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Intel Program License 
--  Subscription Agreement, the Intel Quartus Prime License Agreement,
--  the Intel FPGA IP License Agreement, or other applicable license
--  agreement, including, without limitation, that your use is for
--  the sole purpose of programming logic devices manufactured by
--  Intel and sold by Intel or its authorized distributors.  Please
--  refer to the applicable agreement for further details.


FUNCTION fiftyfivenm_ram_block (clk0, clk1, clr0, clr1, ena0, ena1, ena2, ena3, portaaddr[PORT_A_ADDRESS_WIDTH-1..0], portaaddrstall, portabyteenamasks[PORT_A_BYTE_ENABLE_MASK_WIDTH-1..0], portadatain[PORT_A_DATA_WIDTH-1..0], portare, portawe, portbaddr[PORT_B_ADDRESS_WIDTH-1..0], portbaddrstall, portbbyteenamasks[PORT_B_BYTE_ENABLE_MASK_WIDTH-1..0], portbdatain[PORT_B_DATA_WIDTH-1..0], portbre, portbwe)
WITH ( CLK0_CORE_CLOCK_ENABLE, CLK0_INPUT_CLOCK_ENABLE, CLK0_OUTPUT_CLOCK_ENABLE, CLK1_CORE_CLOCK_ENABLE, CLK1_INPUT_CLOCK_ENABLE, CLK1_OUTPUT_CLOCK_ENABLE, CONNECTIVITY_CHECKING, DATA_INTERLEAVE_OFFSET_IN_BITS, DATA_INTERLEAVE_WIDTH_IN_BITS, DONT_POWER_OPTIMIZE, INIT_FILE, INIT_FILE_LAYOUT, init_file_restructured, LOGICAL_RAM_NAME, mem_init0, mem_init1, mem_init2, mem_init3, mem_init4, MIXED_PORT_FEED_THROUGH_MODE, OPERATION_MODE, PORT_A_ADDRESS_CLEAR, PORT_A_ADDRESS_WIDTH = 1, PORT_A_BYTE_ENABLE_MASK_WIDTH = 1, PORT_A_BYTE_SIZE, PORT_A_DATA_OUT_CLEAR, PORT_A_DATA_OUT_CLOCK, PORT_A_DATA_WIDTH = 1, PORT_A_FIRST_ADDRESS, PORT_A_FIRST_BIT_NUMBER, PORT_A_LAST_ADDRESS, PORT_A_LOGICAL_RAM_DEPTH, PORT_A_LOGICAL_RAM_WIDTH, PORT_A_READ_DURING_WRITE_MODE, PORT_B_ADDRESS_CLEAR, PORT_B_ADDRESS_CLOCK, PORT_B_ADDRESS_WIDTH = 1, PORT_B_BYTE_ENABLE_CLOCK, PORT_B_BYTE_ENABLE_MASK_WIDTH = 1, PORT_B_BYTE_SIZE, PORT_B_DATA_IN_CLOCK, PORT_B_DATA_OUT_CLEAR, PORT_B_DATA_OUT_CLOCK, PORT_B_DATA_WIDTH = 1, PORT_B_FIRST_ADDRESS, PORT_B_FIRST_BIT_NUMBER, PORT_B_LAST_ADDRESS, PORT_B_LOGICAL_RAM_DEPTH, PORT_B_LOGICAL_RAM_WIDTH, PORT_B_READ_DURING_WRITE_MODE, PORT_B_READ_ENABLE_CLOCK, PORT_B_WRITE_ENABLE_CLOCK, POWER_UP_UNINITIALIZED, RAM_BLOCK_TYPE, SAFE_WRITE, WIDTH_ECCSTATUS)
RETURNS ( portadataout[PORT_A_DATA_WIDTH-1..0], portbdataout[PORT_B_DATA_WIDTH-1..0]);

--synthesis_resources = M9K 2 
OPTIONS ALTERA_INTERNAL_OPTION = "OPTIMIZE_POWER_DURING_SYNTHESIS=NORMAL_COMPILATION";

SUBDESIGN altsyncram_14l1
( 
	address_a[6..0]	:	input;
	address_b[6..0]	:	input;
	clock0	:	input;
	data_a[64..0]	:	input;
	q_b[64..0]	:	output;
	wren_a	:	input;
) 
VARIABLE 
	ram_block1a0 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 0,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 0,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a1 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 1,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 1,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a2 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 2,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 2,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a3 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 3,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 3,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a4 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 4,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 4,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a5 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 5,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 5,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a6 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 6,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 6,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a7 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 7,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 7,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a8 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 8,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 8,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a9 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 9,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 9,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a10 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 10,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 10,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a11 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 11,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 11,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a12 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 12,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 12,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a13 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 13,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 13,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a14 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 14,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 14,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a15 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 15,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 15,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a16 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 16,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 16,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a17 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 17,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 17,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a18 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 18,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 18,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a19 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 19,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 19,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a20 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 20,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 20,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a21 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 21,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 21,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a22 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 22,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 22,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a23 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 23,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 23,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a24 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 24,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 24,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a25 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 25,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 25,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a26 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 26,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 26,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a27 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 27,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 27,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a28 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 28,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 28,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a29 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 29,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 29,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a30 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 30,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 30,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a31 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 31,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 31,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a32 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 32,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 32,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a33 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 33,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 33,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a34 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 34,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 34,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a35 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 35,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 35,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a36 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 36,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 36,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a37 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 37,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 37,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a38 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 38,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 38,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a39 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 39,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 39,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a40 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 40,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 40,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a41 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 41,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 41,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a42 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 42,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 42,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a43 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 43,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 43,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a44 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 44,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 44,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a45 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 45,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 45,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a46 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 46,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 46,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a47 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 47,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 47,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a48 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 48,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 48,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a49 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 49,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 49,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a50 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 50,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 50,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a51 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 51,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 51,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a52 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 52,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 52,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a53 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 53,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 53,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a54 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 54,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 54,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a55 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 55,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 55,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a56 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 56,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 56,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a57 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 57,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 57,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a58 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 58,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 58,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a59 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 59,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 59,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a60 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 60,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 60,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a61 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 61,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 61,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a62 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 62,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 62,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a63 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 63,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 63,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	ram_block1a64 : fiftyfivenm_ram_block
		WITH (
			CLK0_CORE_CLOCK_ENABLE = "ena0",
			CLK0_INPUT_CLOCK_ENABLE = "none",
			CLK1_CORE_CLOCK_ENABLE = "none",
			CLK1_INPUT_CLOCK_ENABLE = "none",
			CONNECTIVITY_CHECKING = "OFF",
			LOGICAL_RAM_NAME = "ALTSYNCRAM",
			MIXED_PORT_FEED_THROUGH_MODE = "dont_care",
			OPERATION_MODE = "dual_port",
			PORT_A_ADDRESS_WIDTH = 7,
			PORT_A_DATA_WIDTH = 1,
			PORT_A_FIRST_ADDRESS = 0,
			PORT_A_FIRST_BIT_NUMBER = 64,
			PORT_A_LAST_ADDRESS = 127,
			PORT_A_LOGICAL_RAM_DEPTH = 128,
			PORT_A_LOGICAL_RAM_WIDTH = 65,
			PORT_B_ADDRESS_CLEAR = "none",
			PORT_B_ADDRESS_CLOCK = "clock1",
			PORT_B_ADDRESS_WIDTH = 7,
			PORT_B_DATA_OUT_CLEAR = "none",
			PORT_B_DATA_WIDTH = 1,
			PORT_B_FIRST_ADDRESS = 0,
			PORT_B_FIRST_BIT_NUMBER = 64,
			PORT_B_LAST_ADDRESS = 127,
			PORT_B_LOGICAL_RAM_DEPTH = 128,
			PORT_B_LOGICAL_RAM_WIDTH = 65,
			PORT_B_READ_ENABLE_CLOCK = "clock1",
			POWER_UP_UNINITIALIZED = "false",
			RAM_BLOCK_TYPE = "AUTO"
		);
	address_a_wire[6..0]	: WIRE;
	address_b_wire[6..0]	: WIRE;

BEGIN 
	ram_block1a[64..0].clk0 = clock0;
	ram_block1a[64..0].clk1 = clock0;
	ram_block1a[64..0].ena0 = wren_a;
	ram_block1a[64..0].portaaddr[] = ( address_a_wire[6..0]);
	ram_block1a[0].portadatain[] = ( data_a[0..0]);
	ram_block1a[1].portadatain[] = ( data_a[1..1]);
	ram_block1a[2].portadatain[] = ( data_a[2..2]);
	ram_block1a[3].portadatain[] = ( data_a[3..3]);
	ram_block1a[4].portadatain[] = ( data_a[4..4]);
	ram_block1a[5].portadatain[] = ( data_a[5..5]);
	ram_block1a[6].portadatain[] = ( data_a[6..6]);
	ram_block1a[7].portadatain[] = ( data_a[7..7]);
	ram_block1a[8].portadatain[] = ( data_a[8..8]);
	ram_block1a[9].portadatain[] = ( data_a[9..9]);
	ram_block1a[10].portadatain[] = ( data_a[10..10]);
	ram_block1a[11].portadatain[] = ( data_a[11..11]);
	ram_block1a[12].portadatain[] = ( data_a[12..12]);
	ram_block1a[13].portadatain[] = ( data_a[13..13]);
	ram_block1a[14].portadatain[] = ( data_a[14..14]);
	ram_block1a[15].portadatain[] = ( data_a[15..15]);
	ram_block1a[16].portadatain[] = ( data_a[16..16]);
	ram_block1a[17].portadatain[] = ( data_a[17..17]);
	ram_block1a[18].portadatain[] = ( data_a[18..18]);
	ram_block1a[19].portadatain[] = ( data_a[19..19]);
	ram_block1a[20].portadatain[] = ( data_a[20..20]);
	ram_block1a[21].portadatain[] = ( data_a[21..21]);
	ram_block1a[22].portadatain[] = ( data_a[22..22]);
	ram_block1a[23].portadatain[] = ( data_a[23..23]);
	ram_block1a[24].portadatain[] = ( data_a[24..24]);
	ram_block1a[25].portadatain[] = ( data_a[25..25]);
	ram_block1a[26].portadatain[] = ( data_a[26..26]);
	ram_block1a[27].portadatain[] = ( data_a[27..27]);
	ram_block1a[28].portadatain[] = ( data_a[28..28]);
	ram_block1a[29].portadatain[] = ( data_a[29..29]);
	ram_block1a[30].portadatain[] = ( data_a[30..30]);
	ram_block1a[31].portadatain[] = ( data_a[31..31]);
	ram_block1a[32].portadatain[] = ( data_a[32..32]);
	ram_block1a[33].portadatain[] = ( data_a[33..33]);
	ram_block1a[34].portadatain[] = ( data_a[34..34]);
	ram_block1a[35].portadatain[] = ( data_a[35..35]);
	ram_block1a[36].portadatain[] = ( data_a[36..36]);
	ram_block1a[37].portadatain[] = ( data_a[37..37]);
	ram_block1a[38].portadatain[] = ( data_a[38..38]);
	ram_block1a[39].portadatain[] = ( data_a[39..39]);
	ram_block1a[40].portadatain[] = ( data_a[40..40]);
	ram_block1a[41].portadatain[] = ( data_a[41..41]);
	ram_block1a[42].portadatain[] = ( data_a[42..42]);
	ram_block1a[43].portadatain[] = ( data_a[43..43]);
	ram_block1a[44].portadatain[] = ( data_a[44..44]);
	ram_block1a[45].portadatain[] = ( data_a[45..45]);
	ram_block1a[46].portadatain[] = ( data_a[46..46]);
	ram_block1a[47].portadatain[] = ( data_a[47..47]);
	ram_block1a[48].portadatain[] = ( data_a[48..48]);
	ram_block1a[49].portadatain[] = ( data_a[49..49]);
	ram_block1a[50].portadatain[] = ( data_a[50..50]);
	ram_block1a[51].portadatain[] = ( data_a[51..51]);
	ram_block1a[52].portadatain[] = ( data_a[52..52]);
	ram_block1a[53].portadatain[] = ( data_a[53..53]);
	ram_block1a[54].portadatain[] = ( data_a[54..54]);
	ram_block1a[55].portadatain[] = ( data_a[55..55]);
	ram_block1a[56].portadatain[] = ( data_a[56..56]);
	ram_block1a[57].portadatain[] = ( data_a[57..57]);
	ram_block1a[58].portadatain[] = ( data_a[58..58]);
	ram_block1a[59].portadatain[] = ( data_a[59..59]);
	ram_block1a[60].portadatain[] = ( data_a[60..60]);
	ram_block1a[61].portadatain[] = ( data_a[61..61]);
	ram_block1a[62].portadatain[] = ( data_a[62..62]);
	ram_block1a[63].portadatain[] = ( data_a[63..63]);
	ram_block1a[64].portadatain[] = ( data_a[64..64]);
	ram_block1a[64..0].portawe = wren_a;
	ram_block1a[64..0].portbaddr[] = ( address_b_wire[6..0]);
	ram_block1a[64..0].portbre = B"11111111111111111111111111111111111111111111111111111111111111111";
	address_a_wire[] = address_a[];
	address_b_wire[] = address_b[];
	q_b[] = ( ram_block1a[64..0].portbdataout[0..0]);
END;
--VALID FILE
