library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity bench is

end entity bench;

architecture sim of bench is

  signal clk50 : std_logic;
  signal rst   : std_logic;

begin  -- architecture sim

  clkgen : process is
  begin
    clk50 <= '0';
    wait for 20 ns;
    clk50 <= '1';
    wait for 20 ns;
  end process clkgen;

  rstgen : process is
  begin
    rst <= '0';
    wait for 30 ns;
    rst <= '1';
    wait;
  end process rstgen :



end architecture sim;
