# system info ddr3controller_example on 2021.02.20.21:29:02
system_info:
name,value
DEVICE,
DEVICE_FAMILY,MAX 10
GENERATION_ID,
#
#
# Files generated for ddr3controller_example on 2021.02.20.21:29:02
files:
filepath,kind,attributes,module,is_top
ddr3controller_example/ddr3controller_example.v,VERILOG,,ddr3controller_example,true
ddr3controller_example/submodules/ddr3controller_example_if0.v,VERILOG,,ddr3controller_example_if0,false
ddr3controller_example/submodules/ddr3controller_example_d0.v,VERILOG,,ddr3controller_example_d0,false
ddr3controller_example/submodules/ddr3controller_example_mm_interconnect_0.v,VERILOG,,ddr3controller_example_mm_interconnect_0,false
ddr3controller_example/submodules/altera_reset_controller.v,VERILOG,,altera_reset_controller,false
ddr3controller_example/submodules/altera_reset_synchronizer.v,VERILOG,,altera_reset_controller,false
ddr3controller_example/submodules/altera_reset_controller.sdc,SDC,,altera_reset_controller,false
ddr3controller_example/submodules/ddr3controller_example_if0_pll0.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_pll0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_clock_pair_generator.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_read_valid_selector.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_addr_cmd_datapath.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_reset_m10.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_memphy_m10.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_dqdqs_pads_m10.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_reset_sync.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_fr_cycle_shifter.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_read_datapath_m10.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_write_datapath_m10.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_simple_ddio_out_m10.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/max10emif_dcfifo.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_iss_probe.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_addr_cmd_pads_m10.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_flop_mem.v,VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/altera_gpio_lite.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0.ppf,OTHER,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0.sdc,SDC,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_timing.tcl,OTHER,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_report_timing.tcl,OTHER,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_report_timing_core.tcl,OTHER,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_pin_map.tcl,OTHER,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_pin_assignments.tcl,OTHER,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/ddr3controller_example_if0_p0_parameters.tcl,OTHER,,ddr3controller_example_if0_p0,false
ddr3controller_example/submodules/afi_mux_ddr3_ddrx.v,VERILOG,,afi_mux_ddr3_ddrx,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_software/sequencer_m10.c,OTHER,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_software/sequencer_m10.h,OTHER,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_software/sequencer_defines.h,OTHER,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_make_qsys_seq.tcl,OTHER,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_mm_interconnect_0_avalon_st_adapter_error_adapter_0.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_mm_interconnect_0_avalon_st_adapter.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_mm_interconnect_0_rsp_mux.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_mm_interconnect_0_rsp_demux.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/altera_merlin_arbitrator.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_mm_interconnect_0_cmd_mux.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_mm_interconnect_0_cmd_demux.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_mm_interconnect_0_router_001.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_mm_interconnect_0_router.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/altera_avalon_sc_fifo.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/altera_merlin_burst_uncompressor.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/altera_merlin_slave_agent.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/altera_merlin_master_agent.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_mm_interconnect_0.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_write_decoder.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_read_datapath.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_ram_csr.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_ram.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_pattern_fifo.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_lfsr12.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_lfsr36.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_lfsr72.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_jumplogic.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_inst_ROM_reg.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_generic.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_dm_decoder.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_di_buffer_wrap.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_di_buffer.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_datamux.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_data_decoder.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_data_broadcast.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_core.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_bitcheck.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_ac_ROM_reg.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_ddr3.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/sequencer_phy_mgr.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/sequencer_pll_mgr.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/sequencer_m10.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/altera_mem_if_sequencer_rst.sv,SYSTEM_VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_AC_ROM.hex,HEX,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_s0_inst_ROM.hex,HEX,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_m10_ac_ROM.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/rw_manager_m10_inst_ROM.v,VERILOG,,ddr3controller_example_if0_s0,false
ddr3controller_example/submodules/ddr3controller_example_if0_c0.v,VERILOG,,ddr3controller_example_if0_c0,false
ddr3controller_example/submodules/driver_definitions.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/burst_boundary_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/lfsr.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/lfsr_wrapper.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/rand_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/rand_burstcount_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/rand_num_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/rand_seq_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/reset_sync.v,VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/scfifo_wrapper.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/seq_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/template_addr_gen.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/template_stage.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/driver_csr.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/avalon_traffic_gen_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/block_rw_stage_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/driver_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/driver_fsm_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/read_compare_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/single_rw_stage_avl_use_be_avl_use_burstbegin.sv,SYSTEM_VERILOG,,driver_avl_use_be_avl_use_burstbegin,false
ddr3controller_example/submodules/altera_merlin_master_translator.sv,SYSTEM_VERILOG,,altera_merlin_master_translator,false
ddr3controller_example/submodules/altera_merlin_slave_translator.sv,SYSTEM_VERILOG,,altera_merlin_slave_translator,false
ddr3controller_example/submodules/alt_mem_ddrx_addr_cmd.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_addr_cmd_wrap.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_ddr2_odt_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_ddr3_odt_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_lpddr2_addr_cmd.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_odt_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_rdwr_data_tmg.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_arbiter.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_burst_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_cmd_gen.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_csr.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_buffer.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_buffer_manager.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_burst_tracking.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_dataid_manager.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_fifo.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_list.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_rdata_path.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_wdata_path.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_define.iv,VERILOG_INCLUDE,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_ecc_decoder.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_ecc_decoder_32_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_ecc_decoder_64_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_ecc_encoder.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_ecc_encoder_32_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_ecc_encoder_64_syn.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_ecc_encoder_decoder_wrapper.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_axi_st_converter.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_input_if.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_rank_timer.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_sideband.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_tbp.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_timing_param.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_controller.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_controller_st_top.v,VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_if_nextgen_ddr3_controller_core.sv,SYSTEM_VERILOG,,alt_mem_if_nextgen_ddr3_controller_core,false
ddr3controller_example/submodules/alt_mem_ddrx_mm_st_converter.v,VERILOG,,alt_mem_ddrx_mm_st_converter,false
#
# Map from instance-path to kind of module
instances:
instancePath,module
ddr3controller_example.if0,ddr3controller_example_if0
ddr3controller_example.if0.pll0,ddr3controller_example_if0_pll0
ddr3controller_example.if0.p0,ddr3controller_example_if0_p0
ddr3controller_example.if0.m0,afi_mux_ddr3_ddrx
ddr3controller_example.if0.s0,ddr3controller_example_if0_s0
ddr3controller_example.if0.c0,ddr3controller_example_if0_c0
ddr3controller_example.if0.c0.ng0,alt_mem_if_nextgen_ddr3_controller_core
ddr3controller_example.if0.c0.a0,alt_mem_ddrx_mm_st_converter
ddr3controller_example.d0,ddr3controller_example_d0
ddr3controller_example.d0.traffic_generator_0,driver_avl_use_be_avl_use_burstbegin
ddr3controller_example.mm_interconnect_0,ddr3controller_example_mm_interconnect_0
ddr3controller_example.mm_interconnect_0.d0_avl_translator,altera_merlin_master_translator
ddr3controller_example.mm_interconnect_0.if0_avl_translator,altera_merlin_slave_translator
ddr3controller_example.rst_controller,altera_reset_controller
ddr3controller_example.rst_controller_001,altera_reset_controller
