-- ddr3controller_0002.vhd

-- This file was auto-generated from alt_mem_if_ddr3_emif_hw.tcl.  If you edit it your changes
-- will probably be lost.
-- 
-- Generated using ACDS version 18.1 625

library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity ddr3controller_0002 is
	port (
		pll_ref_clk        : in    std_logic                     := '0';             --      pll_ref_clk.clk
		global_reset_n     : in    std_logic                     := '0';             --     global_reset.reset_n
		soft_reset_n       : in    std_logic                     := '0';             --       soft_reset.reset_n
		afi_clk            : out   std_logic;                                        --          afi_clk.clk
		afi_half_clk       : out   std_logic;                                        --     afi_half_clk.clk
		afi_reset_n        : out   std_logic;                                        --        afi_reset.reset_n
		afi_reset_export_n : out   std_logic;                                        -- afi_reset_export.reset_n
		mem_a              : out   std_logic_vector(14 downto 0);                    --           memory.mem_a
		mem_ba             : out   std_logic_vector(2 downto 0);                     --                 .mem_ba
		mem_ck             : inout std_logic_vector(0 downto 0)  := (others => '0'); --                 .mem_ck
		mem_ck_n           : inout std_logic_vector(0 downto 0)  := (others => '0'); --                 .mem_ck_n
		mem_cke            : out   std_logic_vector(0 downto 0);                     --                 .mem_cke
		mem_cs_n           : out   std_logic_vector(0 downto 0);                     --                 .mem_cs_n
		mem_dm             : out   std_logic_vector(1 downto 0);                     --                 .mem_dm
		mem_ras_n          : out   std_logic_vector(0 downto 0);                     --                 .mem_ras_n
		mem_cas_n          : out   std_logic_vector(0 downto 0);                     --                 .mem_cas_n
		mem_we_n           : out   std_logic_vector(0 downto 0);                     --                 .mem_we_n
		mem_reset_n        : out   std_logic;                                        --                 .mem_reset_n
		mem_dq             : inout std_logic_vector(15 downto 0) := (others => '0'); --                 .mem_dq
		mem_dqs            : inout std_logic_vector(1 downto 0)  := (others => '0'); --                 .mem_dqs
		mem_dqs_n          : inout std_logic_vector(1 downto 0)  := (others => '0'); --                 .mem_dqs_n
		mem_odt            : out   std_logic_vector(0 downto 0);                     --                 .mem_odt
		avl_ready          : out   std_logic;                                        --              avl.waitrequest_n
		avl_burstbegin     : in    std_logic                     := '0';             --                 .beginbursttransfer
		avl_addr           : in    std_logic_vector(25 downto 0) := (others => '0'); --                 .address
		avl_rdata_valid    : out   std_logic;                                        --                 .readdatavalid
		avl_rdata          : out   std_logic_vector(63 downto 0);                    --                 .readdata
		avl_wdata          : in    std_logic_vector(63 downto 0) := (others => '0'); --                 .writedata
		avl_be             : in    std_logic_vector(7 downto 0)  := (others => '0'); --                 .byteenable
		avl_read_req       : in    std_logic                     := '0';             --                 .read
		avl_write_req      : in    std_logic                     := '0';             --                 .write
		avl_size           : in    std_logic_vector(2 downto 0)  := (others => '0'); --                 .burstcount
		local_init_done    : out   std_logic;                                        --           status.local_init_done
		local_cal_success  : out   std_logic;                                        --                 .local_cal_success
		local_cal_fail     : out   std_logic;                                        --                 .local_cal_fail
		pll_mem_clk        : out   std_logic;                                        --      pll_sharing.pll_mem_clk
		pll_write_clk      : out   std_logic;                                        --                 .pll_write_clk
		pll_locked         : out   std_logic;                                        --                 .pll_locked
		pll_capture0_clk   : out   std_logic;                                        --                 .pll_capture0_clk
		pll_capture1_clk   : out   std_logic                                         --                 .pll_capture1_clk
	);
end entity ddr3controller_0002;

architecture rtl of ddr3controller_0002 is
	component ddr3controller_pll0 is
		port (
			global_reset_n     : in  std_logic                    := 'X';             -- reset_n
			afi_clk            : out std_logic;                                       -- clk
			afi_half_clk       : out std_logic;                                       -- clk
			pll_ref_clk        : in  std_logic                    := 'X';             -- clk
			pll_mem_clk        : out std_logic;                                       -- pll_mem_clk
			pll_write_clk      : out std_logic;                                       -- pll_write_clk
			pll_locked         : out std_logic;                                       -- pll_locked
			pll_capture0_clk   : out std_logic;                                       -- pll_capture0_clk
			pll_capture1_clk   : out std_logic;                                       -- pll_capture1_clk
			phasecounterselect : in  std_logic_vector(2 downto 0) := (others => 'X'); -- phasecounterselect
			phasestep          : in  std_logic                    := 'X';             -- phasestep
			phaseupdown        : in  std_logic                    := 'X';             -- phaseupdown
			scanclk            : in  std_logic                    := 'X';             -- scanclk
			phasedone          : out std_logic                                        -- phasedone
		);
	end component ddr3controller_pll0;

	component ddr3controller_p0 is
		port (
			global_reset_n              : in    std_logic                     := 'X';             -- reset_n
			soft_reset_n                : in    std_logic                     := 'X';             -- reset_n
			afi_reset_n                 : out   std_logic;                                        -- reset_n
			afi_reset_export_n          : out   std_logic;                                        -- reset_n
			afi_clk                     : in    std_logic                     := 'X';             -- clk
			afi_half_clk                : in    std_logic                     := 'X';             -- clk
			avl_clk                     : out   std_logic;                                        -- clk
			avl_reset_n                 : out   std_logic;                                        -- reset_n
			afi_addr                    : in    std_logic_vector(29 downto 0) := (others => 'X'); -- afi_addr
			afi_ba                      : in    std_logic_vector(5 downto 0)  := (others => 'X'); -- afi_ba
			afi_ras_n                   : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_ras_n
			afi_we_n                    : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_we_n
			afi_cas_n                   : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_cas_n
			afi_odt                     : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_odt
			afi_cke                     : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_cke
			afi_cs_n                    : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_cs_n
			afi_dqs_burst               : in    std_logic_vector(3 downto 0)  := (others => 'X'); -- afi_dqs_burst
			afi_wdata_valid             : in    std_logic_vector(3 downto 0)  := (others => 'X'); -- afi_wdata_valid
			afi_wdata                   : in    std_logic_vector(63 downto 0) := (others => 'X'); -- afi_wdata
			afi_dm                      : in    std_logic_vector(7 downto 0)  := (others => 'X'); -- afi_dm
			afi_rdata                   : out   std_logic_vector(63 downto 0);                    -- afi_rdata
			afi_rst_n                   : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rst_n
			afi_rdata_en                : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_en
			afi_rdata_en_full           : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_en_full
			afi_rdata_valid             : out   std_logic_vector(1 downto 0);                     -- afi_rdata_valid
			afi_cal_success             : out   std_logic;                                        -- afi_cal_success
			afi_cal_fail                : out   std_logic;                                        -- afi_cal_fail
			afi_wlat                    : out   std_logic_vector(5 downto 0);                     -- afi_wlat
			afi_rlat                    : out   std_logic_vector(5 downto 0);                     -- afi_rlat
			phy_clk                     : out   std_logic;                                        -- phy_clk
			phy_reset_n                 : out   std_logic;                                        -- phy_reset_n
			phy_read_latency_counter    : in    std_logic_vector(4 downto 0)  := (others => 'X'); -- phy_read_latency_counter
			phy_afi_wlat                : in    std_logic_vector(5 downto 0)  := (others => 'X'); -- phy_afi_wlat
			phy_afi_rlat                : in    std_logic_vector(5 downto 0)  := (others => 'X'); -- phy_afi_rlat
			phy_read_increment_vfifo_fr : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- phy_read_increment_vfifo_fr
			phy_read_increment_vfifo_hr : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- phy_read_increment_vfifo_hr
			phy_read_increment_vfifo_qr : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- phy_read_increment_vfifo_qr
			phy_reset_mem_stable        : in    std_logic                     := 'X';             -- phy_reset_mem_stable
			phy_cal_success             : in    std_logic                     := 'X';             -- phy_cal_success
			phy_cal_fail                : in    std_logic                     := 'X';             -- phy_cal_fail
			phy_cal_debug_info          : in    std_logic_vector(31 downto 0) := (others => 'X'); -- phy_cal_debug_info
			phy_read_fifo_reset         : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- phy_read_fifo_reset
			phy_vfifo_rd_en_override    : in    std_logic_vector(1 downto 0)  := (others => 'X'); -- phy_vfifo_rd_en_override
			phy_read_fifo_q             : out   std_logic_vector(63 downto 0);                    -- phy_read_fifo_q
			phy_write_fr_cycle_shifts   : in    std_logic_vector(3 downto 0)  := (others => 'X'); -- phy_write_fr_cycle_shifts
			calib_skip_steps            : out   std_logic_vector(7 downto 0);                     -- calib_skip_steps
			pd_reset_n                  : in    std_logic                     := 'X';             -- pd_reset_n
			pd_ack                      : in    std_logic                     := 'X';             -- pd_ack
			pd_up                       : out   std_logic;                                        -- pd_up
			pd_down                     : out   std_logic;                                        -- pd_down
			afi_mem_clk_disable         : in    std_logic_vector(0 downto 0)  := (others => 'X'); -- afi_mem_clk_disable
			pll_mem_clk                 : in    std_logic                     := 'X';             -- pll_mem_clk
			pll_write_clk               : in    std_logic                     := 'X';             -- pll_write_clk
			pll_locked                  : in    std_logic                     := 'X';             -- pll_locked
			pll_capture0_clk            : in    std_logic                     := 'X';             -- pll_capture0_clk
			pll_capture1_clk            : in    std_logic                     := 'X';             -- pll_capture1_clk
			mem_a                       : out   std_logic_vector(14 downto 0);                    -- mem_a
			mem_ba                      : out   std_logic_vector(2 downto 0);                     -- mem_ba
			mem_ck                      : inout std_logic_vector(0 downto 0)  := (others => 'X'); -- mem_ck
			mem_ck_n                    : inout std_logic_vector(0 downto 0)  := (others => 'X'); -- mem_ck_n
			mem_cke                     : out   std_logic_vector(0 downto 0);                     -- mem_cke
			mem_cs_n                    : out   std_logic_vector(0 downto 0);                     -- mem_cs_n
			mem_dm                      : out   std_logic_vector(1 downto 0);                     -- mem_dm
			mem_ras_n                   : out   std_logic_vector(0 downto 0);                     -- mem_ras_n
			mem_cas_n                   : out   std_logic_vector(0 downto 0);                     -- mem_cas_n
			mem_we_n                    : out   std_logic_vector(0 downto 0);                     -- mem_we_n
			mem_reset_n                 : out   std_logic;                                        -- mem_reset_n
			mem_dq                      : inout std_logic_vector(15 downto 0) := (others => 'X'); -- mem_dq
			mem_dqs                     : inout std_logic_vector(1 downto 0)  := (others => 'X'); -- mem_dqs
			mem_dqs_n                   : inout std_logic_vector(1 downto 0)  := (others => 'X'); -- mem_dqs_n
			mem_odt                     : out   std_logic_vector(0 downto 0);                     -- mem_odt
			csr_soft_reset_req          : in    std_logic                     := 'X'              -- reset
		);
	end component ddr3controller_p0;

	component afi_mux_ddr3_ddrx is
		generic (
			AFI_RATE_RATIO            : integer := 0;
			AFI_ADDR_WIDTH            : integer := 0;
			AFI_BANKADDR_WIDTH        : integer := 0;
			AFI_CONTROL_WIDTH         : integer := 0;
			AFI_CS_WIDTH              : integer := 0;
			AFI_CLK_EN_WIDTH          : integer := 0;
			AFI_DM_WIDTH              : integer := 0;
			AFI_DQ_WIDTH              : integer := 0;
			AFI_ODT_WIDTH             : integer := 0;
			AFI_WRITE_DQS_WIDTH       : integer := 0;
			AFI_RLAT_WIDTH            : integer := 0;
			AFI_WLAT_WIDTH            : integer := 0;
			AFI_RRANK_WIDTH           : integer := 0;
			AFI_WRANK_WIDTH           : integer := 0;
			MRS_MIRROR_PING_PONG_ATSO : boolean := false
		);
		port (
			clk                   : in  std_logic                     := 'X';             -- clk
			afi_addr              : in  std_logic_vector(29 downto 0) := (others => 'X'); -- afi_addr
			afi_ba                : in  std_logic_vector(5 downto 0)  := (others => 'X'); -- afi_ba
			afi_ras_n             : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_ras_n
			afi_we_n              : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_we_n
			afi_cas_n             : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_cas_n
			afi_odt               : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_odt
			afi_cke               : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_cke
			afi_cs_n              : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_cs_n
			afi_dqs_burst         : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- afi_dqs_burst
			afi_wdata_valid       : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- afi_wdata_valid
			afi_wdata             : in  std_logic_vector(63 downto 0) := (others => 'X'); -- afi_wdata
			afi_dm                : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- afi_dm
			afi_rdata             : out std_logic_vector(63 downto 0);                    -- afi_rdata
			afi_rst_n             : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rst_n
			afi_rdata_en          : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_en
			afi_rdata_en_full     : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_en_full
			afi_rdata_valid       : out std_logic_vector(1 downto 0);                     -- afi_rdata_valid
			afi_cal_success       : out std_logic;                                        -- afi_cal_success
			afi_cal_fail          : out std_logic;                                        -- afi_cal_fail
			afi_wlat              : out std_logic_vector(5 downto 0);                     -- afi_wlat
			afi_rlat              : out std_logic_vector(5 downto 0);                     -- afi_rlat
			phy_mux_addr          : out std_logic_vector(29 downto 0);                    -- afi_addr
			phy_mux_ba            : out std_logic_vector(5 downto 0);                     -- afi_ba
			phy_mux_ras_n         : out std_logic_vector(1 downto 0);                     -- afi_ras_n
			phy_mux_we_n          : out std_logic_vector(1 downto 0);                     -- afi_we_n
			phy_mux_cas_n         : out std_logic_vector(1 downto 0);                     -- afi_cas_n
			phy_mux_odt           : out std_logic_vector(1 downto 0);                     -- afi_odt
			phy_mux_cke           : out std_logic_vector(1 downto 0);                     -- afi_cke
			phy_mux_cs_n          : out std_logic_vector(1 downto 0);                     -- afi_cs_n
			phy_mux_dqs_burst     : out std_logic_vector(3 downto 0);                     -- afi_dqs_burst
			phy_mux_wdata_valid   : out std_logic_vector(3 downto 0);                     -- afi_wdata_valid
			phy_mux_wdata         : out std_logic_vector(63 downto 0);                    -- afi_wdata
			phy_mux_dm            : out std_logic_vector(7 downto 0);                     -- afi_dm
			phy_mux_rdata         : in  std_logic_vector(63 downto 0) := (others => 'X'); -- afi_rdata
			phy_mux_rst_n         : out std_logic_vector(1 downto 0);                     -- afi_rst_n
			phy_mux_rdata_en      : out std_logic_vector(1 downto 0);                     -- afi_rdata_en
			phy_mux_rdata_en_full : out std_logic_vector(1 downto 0);                     -- afi_rdata_en_full
			phy_mux_rdata_valid   : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_valid
			phy_mux_cal_success   : in  std_logic                     := 'X';             -- afi_cal_success
			phy_mux_cal_fail      : in  std_logic                     := 'X';             -- afi_cal_fail
			phy_mux_wlat          : in  std_logic_vector(5 downto 0)  := (others => 'X'); -- afi_wlat
			phy_mux_rlat          : in  std_logic_vector(5 downto 0)  := (others => 'X'); -- afi_rlat
			seq_mux_addr          : in  std_logic_vector(29 downto 0) := (others => 'X'); -- afi_addr
			seq_mux_ba            : in  std_logic_vector(5 downto 0)  := (others => 'X'); -- afi_ba
			seq_mux_ras_n         : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_ras_n
			seq_mux_we_n          : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_we_n
			seq_mux_cas_n         : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_cas_n
			seq_mux_odt           : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_odt
			seq_mux_cke           : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_cke
			seq_mux_cs_n          : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_cs_n
			seq_mux_dqs_burst     : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- afi_dqs_burst
			seq_mux_wdata_valid   : in  std_logic_vector(3 downto 0)  := (others => 'X'); -- afi_wdata_valid
			seq_mux_wdata         : in  std_logic_vector(63 downto 0) := (others => 'X'); -- afi_wdata
			seq_mux_dm            : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- afi_dm
			seq_mux_rdata         : out std_logic_vector(63 downto 0);                    -- afi_rdata
			seq_mux_rst_n         : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rst_n
			seq_mux_rdata_en      : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_en
			seq_mux_rdata_en_full : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_en_full
			seq_mux_rdata_valid   : out std_logic_vector(1 downto 0);                     -- afi_rdata_valid
			mux_sel               : in  std_logic                     := 'X'              -- mux_sel
		);
	end component afi_mux_ddr3_ddrx;

	component ddr3controller_s0 is
		port (
			avl_clk                     : in  std_logic                     := 'X';             -- clk
			avl_reset_n                 : in  std_logic                     := 'X';             -- reset_n
			phasecounterselect          : out std_logic_vector(2 downto 0);                     -- phasecounterselect
			phasestep                   : out std_logic;                                        -- phasestep
			phaseupdown                 : out std_logic;                                        -- phaseupdown
			scanclk                     : out std_logic;                                        -- scanclk
			phasedone                   : in  std_logic                     := 'X';             -- phasedone
			afi_init_req                : in  std_logic                     := 'X';             -- afi_init_req
			afi_cal_req                 : in  std_logic                     := 'X';             -- afi_cal_req
			pd_reset_n                  : out std_logic;                                        -- pd_reset_n
			pd_ack                      : out std_logic;                                        -- pd_ack
			pd_up                       : in  std_logic                     := 'X';             -- pd_up
			pd_down                     : in  std_logic                     := 'X';             -- pd_down
			phy_clk                     : in  std_logic                     := 'X';             -- phy_clk
			phy_reset_n                 : in  std_logic                     := 'X';             -- phy_reset_n
			phy_read_latency_counter    : out std_logic_vector(4 downto 0);                     -- phy_read_latency_counter
			phy_afi_wlat                : out std_logic_vector(5 downto 0);                     -- phy_afi_wlat
			phy_afi_rlat                : out std_logic_vector(5 downto 0);                     -- phy_afi_rlat
			phy_read_increment_vfifo_fr : out std_logic_vector(1 downto 0);                     -- phy_read_increment_vfifo_fr
			phy_read_increment_vfifo_hr : out std_logic_vector(1 downto 0);                     -- phy_read_increment_vfifo_hr
			phy_read_increment_vfifo_qr : out std_logic_vector(1 downto 0);                     -- phy_read_increment_vfifo_qr
			phy_reset_mem_stable        : out std_logic;                                        -- phy_reset_mem_stable
			phy_cal_success             : out std_logic;                                        -- phy_cal_success
			phy_cal_fail                : out std_logic;                                        -- phy_cal_fail
			phy_cal_debug_info          : out std_logic_vector(31 downto 0);                    -- phy_cal_debug_info
			phy_read_fifo_reset         : out std_logic_vector(1 downto 0);                     -- phy_read_fifo_reset
			phy_vfifo_rd_en_override    : out std_logic_vector(1 downto 0);                     -- phy_vfifo_rd_en_override
			phy_read_fifo_q             : in  std_logic_vector(63 downto 0) := (others => 'X'); -- phy_read_fifo_q
			phy_write_fr_cycle_shifts   : out std_logic_vector(3 downto 0);                     -- phy_write_fr_cycle_shifts
			calib_skip_steps            : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- calib_skip_steps
			phy_mux_sel                 : out std_logic;                                        -- mux_sel
			afi_clk                     : in  std_logic                     := 'X';             -- clk
			afi_reset_n                 : in  std_logic                     := 'X';             -- reset_n
			afi_addr                    : out std_logic_vector(29 downto 0);                    -- afi_addr
			afi_ba                      : out std_logic_vector(5 downto 0);                     -- afi_ba
			afi_ras_n                   : out std_logic_vector(1 downto 0);                     -- afi_ras_n
			afi_we_n                    : out std_logic_vector(1 downto 0);                     -- afi_we_n
			afi_cas_n                   : out std_logic_vector(1 downto 0);                     -- afi_cas_n
			afi_odt                     : out std_logic_vector(1 downto 0);                     -- afi_odt
			afi_cke                     : out std_logic_vector(1 downto 0);                     -- afi_cke
			afi_cs_n                    : out std_logic_vector(1 downto 0);                     -- afi_cs_n
			afi_dqs_burst               : out std_logic_vector(3 downto 0);                     -- afi_dqs_burst
			afi_wdata_valid             : out std_logic_vector(3 downto 0);                     -- afi_wdata_valid
			afi_wdata                   : out std_logic_vector(63 downto 0);                    -- afi_wdata
			afi_dm                      : out std_logic_vector(7 downto 0);                     -- afi_dm
			afi_rdata                   : in  std_logic_vector(63 downto 0) := (others => 'X'); -- afi_rdata
			afi_rst_n                   : out std_logic_vector(1 downto 0);                     -- afi_rst_n
			afi_rdata_en                : out std_logic_vector(1 downto 0);                     -- afi_rdata_en
			afi_rdata_en_full           : out std_logic_vector(1 downto 0);                     -- afi_rdata_en_full
			afi_rdata_valid             : in  std_logic_vector(1 downto 0)  := (others => 'X')  -- afi_rdata_valid
		);
	end component ddr3controller_s0;

	component ddr3controller_c0 is
		port (
			afi_reset_n         : in  std_logic                     := 'X';             -- reset_n
			afi_clk             : in  std_logic                     := 'X';             -- clk
			afi_half_clk        : in  std_logic                     := 'X';             -- clk
			local_init_done     : out std_logic;                                        -- local_init_done
			local_cal_success   : out std_logic;                                        -- local_cal_success
			local_cal_fail      : out std_logic;                                        -- local_cal_fail
			afi_addr            : out std_logic_vector(29 downto 0);                    -- afi_addr
			afi_ba              : out std_logic_vector(5 downto 0);                     -- afi_ba
			afi_ras_n           : out std_logic_vector(1 downto 0);                     -- afi_ras_n
			afi_we_n            : out std_logic_vector(1 downto 0);                     -- afi_we_n
			afi_cas_n           : out std_logic_vector(1 downto 0);                     -- afi_cas_n
			afi_odt             : out std_logic_vector(1 downto 0);                     -- afi_odt
			afi_cke             : out std_logic_vector(1 downto 0);                     -- afi_cke
			afi_cs_n            : out std_logic_vector(1 downto 0);                     -- afi_cs_n
			afi_dqs_burst       : out std_logic_vector(3 downto 0);                     -- afi_dqs_burst
			afi_wdata_valid     : out std_logic_vector(3 downto 0);                     -- afi_wdata_valid
			afi_wdata           : out std_logic_vector(63 downto 0);                    -- afi_wdata
			afi_dm              : out std_logic_vector(7 downto 0);                     -- afi_dm
			afi_rdata           : in  std_logic_vector(63 downto 0) := (others => 'X'); -- afi_rdata
			afi_rst_n           : out std_logic_vector(1 downto 0);                     -- afi_rst_n
			afi_mem_clk_disable : out std_logic_vector(0 downto 0);                     -- afi_mem_clk_disable
			afi_init_req        : out std_logic;                                        -- afi_init_req
			afi_cal_req         : out std_logic;                                        -- afi_cal_req
			afi_rdata_en        : out std_logic_vector(1 downto 0);                     -- afi_rdata_en
			afi_rdata_en_full   : out std_logic_vector(1 downto 0);                     -- afi_rdata_en_full
			afi_rdata_valid     : in  std_logic_vector(1 downto 0)  := (others => 'X'); -- afi_rdata_valid
			afi_cal_success     : in  std_logic                     := 'X';             -- afi_cal_success
			afi_cal_fail        : in  std_logic                     := 'X';             -- afi_cal_fail
			afi_wlat            : in  std_logic_vector(5 downto 0)  := (others => 'X'); -- afi_wlat
			afi_rlat            : in  std_logic_vector(5 downto 0)  := (others => 'X'); -- afi_rlat
			avl_ready           : out std_logic;                                        -- waitrequest_n
			avl_burstbegin      : in  std_logic                     := 'X';             -- beginbursttransfer
			avl_addr            : in  std_logic_vector(25 downto 0) := (others => 'X'); -- address
			avl_rdata_valid     : out std_logic;                                        -- readdatavalid
			avl_rdata           : out std_logic_vector(63 downto 0);                    -- readdata
			avl_wdata           : in  std_logic_vector(63 downto 0) := (others => 'X'); -- writedata
			avl_be              : in  std_logic_vector(7 downto 0)  := (others => 'X'); -- byteenable
			avl_read_req        : in  std_logic                     := 'X';             -- read
			avl_write_req       : in  std_logic                     := 'X';             -- write
			avl_size            : in  std_logic_vector(2 downto 0)  := (others => 'X')  -- burstcount
		);
	end component ddr3controller_c0;

	signal pll0_afi_clk_clk                   : std_logic;                     -- pll0:afi_clk -> [afi_clk, c0:afi_clk, m0:clk, p0:afi_clk, s0:afi_clk]
	signal pll0_afi_half_clk_clk              : std_logic;                     -- pll0:afi_half_clk -> [afi_half_clk, c0:afi_half_clk, p0:afi_half_clk]
	signal p0_afi_reset_reset                 : std_logic;                     -- p0:afi_reset_n -> [afi_reset_n, c0:afi_reset_n, s0:afi_reset_n]
	signal m0_phy_mux_afi_rdata_en_full       : std_logic_vector(1 downto 0);  -- m0:phy_mux_rdata_en_full -> p0:afi_rdata_en_full
	signal p0_afi_afi_rlat                    : std_logic_vector(5 downto 0);  -- p0:afi_rlat -> m0:phy_mux_rlat
	signal p0_afi_afi_cal_success             : std_logic;                     -- p0:afi_cal_success -> m0:phy_mux_cal_success
	signal m0_phy_mux_afi_wdata_valid         : std_logic_vector(3 downto 0);  -- m0:phy_mux_wdata_valid -> p0:afi_wdata_valid
	signal p0_afi_afi_rdata                   : std_logic_vector(63 downto 0); -- p0:afi_rdata -> m0:phy_mux_rdata
	signal m0_phy_mux_afi_wdata               : std_logic_vector(63 downto 0); -- m0:phy_mux_wdata -> p0:afi_wdata
	signal m0_phy_mux_afi_rst_n               : std_logic_vector(1 downto 0);  -- m0:phy_mux_rst_n -> p0:afi_rst_n
	signal m0_phy_mux_afi_dqs_burst           : std_logic_vector(3 downto 0);  -- m0:phy_mux_dqs_burst -> p0:afi_dqs_burst
	signal m0_phy_mux_afi_addr                : std_logic_vector(29 downto 0); -- m0:phy_mux_addr -> p0:afi_addr
	signal m0_phy_mux_afi_ba                  : std_logic_vector(5 downto 0);  -- m0:phy_mux_ba -> p0:afi_ba
	signal p0_afi_afi_wlat                    : std_logic_vector(5 downto 0);  -- p0:afi_wlat -> m0:phy_mux_wlat
	signal m0_phy_mux_afi_dm                  : std_logic_vector(7 downto 0);  -- m0:phy_mux_dm -> p0:afi_dm
	signal p0_afi_afi_cal_fail                : std_logic;                     -- p0:afi_cal_fail -> m0:phy_mux_cal_fail
	signal p0_afi_afi_rdata_valid             : std_logic_vector(1 downto 0);  -- p0:afi_rdata_valid -> m0:phy_mux_rdata_valid
	signal m0_phy_mux_afi_we_n                : std_logic_vector(1 downto 0);  -- m0:phy_mux_we_n -> p0:afi_we_n
	signal m0_phy_mux_afi_cas_n               : std_logic_vector(1 downto 0);  -- m0:phy_mux_cas_n -> p0:afi_cas_n
	signal m0_phy_mux_afi_cs_n                : std_logic_vector(1 downto 0);  -- m0:phy_mux_cs_n -> p0:afi_cs_n
	signal m0_phy_mux_afi_rdata_en            : std_logic_vector(1 downto 0);  -- m0:phy_mux_rdata_en -> p0:afi_rdata_en
	signal m0_phy_mux_afi_odt                 : std_logic_vector(1 downto 0);  -- m0:phy_mux_odt -> p0:afi_odt
	signal m0_phy_mux_afi_ras_n               : std_logic_vector(1 downto 0);  -- m0:phy_mux_ras_n -> p0:afi_ras_n
	signal m0_phy_mux_afi_cke                 : std_logic_vector(1 downto 0);  -- m0:phy_mux_cke -> p0:afi_cke
	signal m0_afi_afi_rlat                    : std_logic_vector(5 downto 0);  -- m0:afi_rlat -> c0:afi_rlat
	signal m0_afi_afi_cal_success             : std_logic;                     -- m0:afi_cal_success -> c0:afi_cal_success
	signal m0_afi_afi_rdata                   : std_logic_vector(63 downto 0); -- m0:afi_rdata -> c0:afi_rdata
	signal m0_afi_afi_wlat                    : std_logic_vector(5 downto 0);  -- m0:afi_wlat -> c0:afi_wlat
	signal m0_afi_afi_cal_fail                : std_logic;                     -- m0:afi_cal_fail -> c0:afi_cal_fail
	signal m0_afi_afi_rdata_valid             : std_logic_vector(1 downto 0);  -- m0:afi_rdata_valid -> c0:afi_rdata_valid
	signal p0_avl_clk_clk                     : std_logic;                     -- p0:avl_clk -> s0:avl_clk
	signal p0_avl_reset_reset                 : std_logic;                     -- p0:avl_reset_n -> s0:avl_reset_n
	signal s0_pll_reconfig_scanclk            : std_logic;                     -- s0:scanclk -> pll0:scanclk
	signal s0_pll_reconfig_phaseupdown        : std_logic;                     -- s0:phaseupdown -> pll0:phaseupdown
	signal s0_pll_reconfig_phasecounterselect : std_logic_vector(2 downto 0);  -- s0:phasecounterselect -> pll0:phasecounterselect
	signal s0_pll_reconfig_phasestep          : std_logic;                     -- s0:phasestep -> pll0:phasestep
	signal pll0_pll_reconfig_phasedone        : std_logic;                     -- pll0:phasedone -> s0:phasedone
	signal s0_phase_detector_pd_ack           : std_logic;                     -- s0:pd_ack -> p0:pd_ack
	signal s0_phase_detector_pd_reset_n       : std_logic;                     -- s0:pd_reset_n -> p0:pd_reset_n
	signal p0_phase_detector_pd_down          : std_logic;                     -- p0:pd_down -> s0:pd_down
	signal p0_phase_detector_pd_up            : std_logic;                     -- p0:pd_up -> s0:pd_up
	signal s0_afi_afi_rdata_en_full           : std_logic_vector(1 downto 0);  -- s0:afi_rdata_en_full -> m0:seq_mux_rdata_en_full
	signal s0_afi_afi_wdata_valid             : std_logic_vector(3 downto 0);  -- s0:afi_wdata_valid -> m0:seq_mux_wdata_valid
	signal m0_seq_mux_afi_rdata               : std_logic_vector(63 downto 0); -- m0:seq_mux_rdata -> s0:afi_rdata
	signal s0_afi_afi_wdata                   : std_logic_vector(63 downto 0); -- s0:afi_wdata -> m0:seq_mux_wdata
	signal s0_afi_afi_rst_n                   : std_logic_vector(1 downto 0);  -- s0:afi_rst_n -> m0:seq_mux_rst_n
	signal s0_afi_afi_dqs_burst               : std_logic_vector(3 downto 0);  -- s0:afi_dqs_burst -> m0:seq_mux_dqs_burst
	signal s0_afi_afi_addr                    : std_logic_vector(29 downto 0); -- s0:afi_addr -> m0:seq_mux_addr
	signal s0_afi_afi_ba                      : std_logic_vector(5 downto 0);  -- s0:afi_ba -> m0:seq_mux_ba
	signal s0_afi_afi_dm                      : std_logic_vector(7 downto 0);  -- s0:afi_dm -> m0:seq_mux_dm
	signal m0_seq_mux_afi_rdata_valid         : std_logic_vector(1 downto 0);  -- m0:seq_mux_rdata_valid -> s0:afi_rdata_valid
	signal s0_afi_afi_we_n                    : std_logic_vector(1 downto 0);  -- s0:afi_we_n -> m0:seq_mux_we_n
	signal s0_afi_afi_cas_n                   : std_logic_vector(1 downto 0);  -- s0:afi_cas_n -> m0:seq_mux_cas_n
	signal s0_afi_afi_cs_n                    : std_logic_vector(1 downto 0);  -- s0:afi_cs_n -> m0:seq_mux_cs_n
	signal s0_afi_afi_rdata_en                : std_logic_vector(1 downto 0);  -- s0:afi_rdata_en -> m0:seq_mux_rdata_en
	signal s0_afi_afi_odt                     : std_logic_vector(1 downto 0);  -- s0:afi_odt -> m0:seq_mux_odt
	signal s0_afi_afi_ras_n                   : std_logic_vector(1 downto 0);  -- s0:afi_ras_n -> m0:seq_mux_ras_n
	signal s0_afi_afi_cke                     : std_logic_vector(1 downto 0);  -- s0:afi_cke -> m0:seq_mux_cke
	signal s0_mux_sel_mux_sel                 : std_logic;                     -- s0:phy_mux_sel -> m0:mux_sel
	signal s0_phy_phy_afi_rlat                : std_logic_vector(5 downto 0);  -- s0:phy_afi_rlat -> p0:phy_afi_rlat
	signal p0_phy_phy_clk                     : std_logic;                     -- p0:phy_clk -> s0:phy_clk
	signal s0_phy_phy_read_latency_counter    : std_logic_vector(4 downto 0);  -- s0:phy_read_latency_counter -> p0:phy_read_latency_counter
	signal s0_phy_phy_afi_wlat                : std_logic_vector(5 downto 0);  -- s0:phy_afi_wlat -> p0:phy_afi_wlat
	signal s0_phy_phy_reset_mem_stable        : std_logic;                     -- s0:phy_reset_mem_stable -> p0:phy_reset_mem_stable
	signal s0_phy_phy_read_increment_vfifo_qr : std_logic_vector(1 downto 0);  -- s0:phy_read_increment_vfifo_qr -> p0:phy_read_increment_vfifo_qr
	signal s0_phy_phy_vfifo_rd_en_override    : std_logic_vector(1 downto 0);  -- s0:phy_vfifo_rd_en_override -> p0:phy_vfifo_rd_en_override
	signal s0_phy_phy_read_fifo_reset         : std_logic_vector(1 downto 0);  -- s0:phy_read_fifo_reset -> p0:phy_read_fifo_reset
	signal s0_phy_phy_write_fr_cycle_shifts   : std_logic_vector(3 downto 0);  -- s0:phy_write_fr_cycle_shifts -> p0:phy_write_fr_cycle_shifts
	signal s0_phy_phy_cal_fail                : std_logic;                     -- s0:phy_cal_fail -> p0:phy_cal_fail
	signal s0_phy_phy_cal_success             : std_logic;                     -- s0:phy_cal_success -> p0:phy_cal_success
	signal p0_phy_phy_reset_n                 : std_logic;                     -- p0:phy_reset_n -> s0:phy_reset_n
	signal s0_phy_phy_cal_debug_info          : std_logic_vector(31 downto 0); -- s0:phy_cal_debug_info -> p0:phy_cal_debug_info
	signal s0_phy_phy_read_increment_vfifo_hr : std_logic_vector(1 downto 0);  -- s0:phy_read_increment_vfifo_hr -> p0:phy_read_increment_vfifo_hr
	signal s0_phy_phy_read_increment_vfifo_fr : std_logic_vector(1 downto 0);  -- s0:phy_read_increment_vfifo_fr -> p0:phy_read_increment_vfifo_fr
	signal p0_phy_phy_read_fifo_q             : std_logic_vector(63 downto 0); -- p0:phy_read_fifo_q -> s0:phy_read_fifo_q
	signal p0_calib_calib_skip_steps          : std_logic_vector(7 downto 0);  -- p0:calib_skip_steps -> s0:calib_skip_steps
	signal c0_afi_afi_rdata_en_full           : std_logic_vector(1 downto 0);  -- c0:afi_rdata_en_full -> m0:afi_rdata_en_full
	signal c0_afi_afi_wdata_valid             : std_logic_vector(3 downto 0);  -- c0:afi_wdata_valid -> m0:afi_wdata_valid
	signal c0_afi_afi_wdata                   : std_logic_vector(63 downto 0); -- c0:afi_wdata -> m0:afi_wdata
	signal c0_afi_afi_rst_n                   : std_logic_vector(1 downto 0);  -- c0:afi_rst_n -> m0:afi_rst_n
	signal c0_afi_afi_cal_req                 : std_logic;                     -- c0:afi_cal_req -> s0:afi_cal_req
	signal c0_afi_afi_dqs_burst               : std_logic_vector(3 downto 0);  -- c0:afi_dqs_burst -> m0:afi_dqs_burst
	signal c0_afi_afi_addr                    : std_logic_vector(29 downto 0); -- c0:afi_addr -> m0:afi_addr
	signal c0_afi_afi_ba                      : std_logic_vector(5 downto 0);  -- c0:afi_ba -> m0:afi_ba
	signal c0_afi_afi_dm                      : std_logic_vector(7 downto 0);  -- c0:afi_dm -> m0:afi_dm
	signal c0_afi_afi_mem_clk_disable         : std_logic_vector(0 downto 0);  -- c0:afi_mem_clk_disable -> p0:afi_mem_clk_disable
	signal c0_afi_afi_init_req                : std_logic;                     -- c0:afi_init_req -> s0:afi_init_req
	signal c0_afi_afi_we_n                    : std_logic_vector(1 downto 0);  -- c0:afi_we_n -> m0:afi_we_n
	signal c0_afi_afi_cas_n                   : std_logic_vector(1 downto 0);  -- c0:afi_cas_n -> m0:afi_cas_n
	signal c0_afi_afi_cs_n                    : std_logic_vector(1 downto 0);  -- c0:afi_cs_n -> m0:afi_cs_n
	signal c0_afi_afi_rdata_en                : std_logic_vector(1 downto 0);  -- c0:afi_rdata_en -> m0:afi_rdata_en
	signal c0_afi_afi_odt                     : std_logic_vector(1 downto 0);  -- c0:afi_odt -> m0:afi_odt
	signal c0_afi_afi_ras_n                   : std_logic_vector(1 downto 0);  -- c0:afi_ras_n -> m0:afi_ras_n
	signal c0_afi_afi_cke                     : std_logic_vector(1 downto 0);  -- c0:afi_cke -> m0:afi_cke
	signal pll0_pll_sharing_pll_write_clk     : std_logic;                     -- pll0:pll_write_clk -> [pll_write_clk, p0:pll_write_clk]
	signal pll0_pll_sharing_pll_capture1_clk  : std_logic;                     -- pll0:pll_capture1_clk -> [pll_capture1_clk, p0:pll_capture1_clk]
	signal pll0_pll_sharing_pll_capture0_clk  : std_logic;                     -- pll0:pll_capture0_clk -> [pll_capture0_clk, p0:pll_capture0_clk]
	signal pll0_pll_sharing_pll_mem_clk       : std_logic;                     -- pll0:pll_mem_clk -> [pll_mem_clk, p0:pll_mem_clk]
	signal pll0_pll_sharing_pll_locked        : std_logic;                     -- pll0:pll_locked -> [pll_locked, p0:pll_locked]

begin

	pll0 : component ddr3controller_pll0
		port map (
			global_reset_n     => global_reset_n,                     -- global_reset.reset_n
			afi_clk            => pll0_afi_clk_clk,                   --      afi_clk.clk
			afi_half_clk       => pll0_afi_half_clk_clk,              -- afi_half_clk.clk
			pll_ref_clk        => pll_ref_clk,                        --  pll_ref_clk.clk
			pll_mem_clk        => pll0_pll_sharing_pll_mem_clk,       --  pll_sharing.pll_mem_clk
			pll_write_clk      => pll0_pll_sharing_pll_write_clk,     --             .pll_write_clk
			pll_locked         => pll0_pll_sharing_pll_locked,        --             .pll_locked
			pll_capture0_clk   => pll0_pll_sharing_pll_capture0_clk,  --             .pll_capture0_clk
			pll_capture1_clk   => pll0_pll_sharing_pll_capture1_clk,  --             .pll_capture1_clk
			phasecounterselect => s0_pll_reconfig_phasecounterselect, -- pll_reconfig.phasecounterselect
			phasestep          => s0_pll_reconfig_phasestep,          --             .phasestep
			phaseupdown        => s0_pll_reconfig_phaseupdown,        --             .phaseupdown
			scanclk            => s0_pll_reconfig_scanclk,            --             .scanclk
			phasedone          => pll0_pll_reconfig_phasedone         --             .phasedone
		);

	p0 : component ddr3controller_p0
		port map (
			global_reset_n              => global_reset_n,                     --        global_reset.reset_n
			soft_reset_n                => soft_reset_n,                       --          soft_reset.reset_n
			afi_reset_n                 => p0_afi_reset_reset,                 --           afi_reset.reset_n
			afi_reset_export_n          => afi_reset_export_n,                 --    afi_reset_export.reset_n
			afi_clk                     => pll0_afi_clk_clk,                   --             afi_clk.clk
			afi_half_clk                => pll0_afi_half_clk_clk,              --        afi_half_clk.clk
			avl_clk                     => p0_avl_clk_clk,                     --             avl_clk.clk
			avl_reset_n                 => p0_avl_reset_reset,                 --           avl_reset.reset_n
			afi_addr                    => m0_phy_mux_afi_addr,                --                 afi.afi_addr
			afi_ba                      => m0_phy_mux_afi_ba,                  --                    .afi_ba
			afi_ras_n                   => m0_phy_mux_afi_ras_n,               --                    .afi_ras_n
			afi_we_n                    => m0_phy_mux_afi_we_n,                --                    .afi_we_n
			afi_cas_n                   => m0_phy_mux_afi_cas_n,               --                    .afi_cas_n
			afi_odt                     => m0_phy_mux_afi_odt,                 --                    .afi_odt
			afi_cke                     => m0_phy_mux_afi_cke,                 --                    .afi_cke
			afi_cs_n                    => m0_phy_mux_afi_cs_n,                --                    .afi_cs_n
			afi_dqs_burst               => m0_phy_mux_afi_dqs_burst,           --                    .afi_dqs_burst
			afi_wdata_valid             => m0_phy_mux_afi_wdata_valid,         --                    .afi_wdata_valid
			afi_wdata                   => m0_phy_mux_afi_wdata,               --                    .afi_wdata
			afi_dm                      => m0_phy_mux_afi_dm,                  --                    .afi_dm
			afi_rdata                   => p0_afi_afi_rdata,                   --                    .afi_rdata
			afi_rst_n                   => m0_phy_mux_afi_rst_n,               --                    .afi_rst_n
			afi_rdata_en                => m0_phy_mux_afi_rdata_en,            --                    .afi_rdata_en
			afi_rdata_en_full           => m0_phy_mux_afi_rdata_en_full,       --                    .afi_rdata_en_full
			afi_rdata_valid             => p0_afi_afi_rdata_valid,             --                    .afi_rdata_valid
			afi_cal_success             => p0_afi_afi_cal_success,             --                    .afi_cal_success
			afi_cal_fail                => p0_afi_afi_cal_fail,                --                    .afi_cal_fail
			afi_wlat                    => p0_afi_afi_wlat,                    --                    .afi_wlat
			afi_rlat                    => p0_afi_afi_rlat,                    --                    .afi_rlat
			phy_clk                     => p0_phy_phy_clk,                     --                 phy.phy_clk
			phy_reset_n                 => p0_phy_phy_reset_n,                 --                    .phy_reset_n
			phy_read_latency_counter    => s0_phy_phy_read_latency_counter,    --                    .phy_read_latency_counter
			phy_afi_wlat                => s0_phy_phy_afi_wlat,                --                    .phy_afi_wlat
			phy_afi_rlat                => s0_phy_phy_afi_rlat,                --                    .phy_afi_rlat
			phy_read_increment_vfifo_fr => s0_phy_phy_read_increment_vfifo_fr, --                    .phy_read_increment_vfifo_fr
			phy_read_increment_vfifo_hr => s0_phy_phy_read_increment_vfifo_hr, --                    .phy_read_increment_vfifo_hr
			phy_read_increment_vfifo_qr => s0_phy_phy_read_increment_vfifo_qr, --                    .phy_read_increment_vfifo_qr
			phy_reset_mem_stable        => s0_phy_phy_reset_mem_stable,        --                    .phy_reset_mem_stable
			phy_cal_success             => s0_phy_phy_cal_success,             --                    .phy_cal_success
			phy_cal_fail                => s0_phy_phy_cal_fail,                --                    .phy_cal_fail
			phy_cal_debug_info          => s0_phy_phy_cal_debug_info,          --                    .phy_cal_debug_info
			phy_read_fifo_reset         => s0_phy_phy_read_fifo_reset,         --                    .phy_read_fifo_reset
			phy_vfifo_rd_en_override    => s0_phy_phy_vfifo_rd_en_override,    --                    .phy_vfifo_rd_en_override
			phy_read_fifo_q             => p0_phy_phy_read_fifo_q,             --                    .phy_read_fifo_q
			phy_write_fr_cycle_shifts   => s0_phy_phy_write_fr_cycle_shifts,   --                    .phy_write_fr_cycle_shifts
			calib_skip_steps            => p0_calib_calib_skip_steps,          --               calib.calib_skip_steps
			pd_reset_n                  => s0_phase_detector_pd_reset_n,       --      phase_detector.pd_reset_n
			pd_ack                      => s0_phase_detector_pd_ack,           --                    .pd_ack
			pd_up                       => p0_phase_detector_pd_up,            --                    .pd_up
			pd_down                     => p0_phase_detector_pd_down,          --                    .pd_down
			afi_mem_clk_disable         => c0_afi_afi_mem_clk_disable,         -- afi_mem_clk_disable.afi_mem_clk_disable
			pll_mem_clk                 => pll0_pll_sharing_pll_mem_clk,       --         pll_sharing.pll_mem_clk
			pll_write_clk               => pll0_pll_sharing_pll_write_clk,     --                    .pll_write_clk
			pll_locked                  => pll0_pll_sharing_pll_locked,        --                    .pll_locked
			pll_capture0_clk            => pll0_pll_sharing_pll_capture0_clk,  --                    .pll_capture0_clk
			pll_capture1_clk            => pll0_pll_sharing_pll_capture1_clk,  --                    .pll_capture1_clk
			mem_a                       => mem_a,                              --              memory.mem_a
			mem_ba                      => mem_ba,                             --                    .mem_ba
			mem_ck                      => mem_ck,                             --                    .mem_ck
			mem_ck_n                    => mem_ck_n,                           --                    .mem_ck_n
			mem_cke                     => mem_cke,                            --                    .mem_cke
			mem_cs_n                    => mem_cs_n,                           --                    .mem_cs_n
			mem_dm                      => mem_dm,                             --                    .mem_dm
			mem_ras_n                   => mem_ras_n,                          --                    .mem_ras_n
			mem_cas_n                   => mem_cas_n,                          --                    .mem_cas_n
			mem_we_n                    => mem_we_n,                           --                    .mem_we_n
			mem_reset_n                 => mem_reset_n,                        --                    .mem_reset_n
			mem_dq                      => mem_dq,                             --                    .mem_dq
			mem_dqs                     => mem_dqs,                            --                    .mem_dqs
			mem_dqs_n                   => mem_dqs_n,                          --                    .mem_dqs_n
			mem_odt                     => mem_odt,                            --                    .mem_odt
			csr_soft_reset_req          => '0'                                 --         (terminated)
		);

	m0 : component afi_mux_ddr3_ddrx
		generic map (
			AFI_RATE_RATIO            => 2,
			AFI_ADDR_WIDTH            => 30,
			AFI_BANKADDR_WIDTH        => 6,
			AFI_CONTROL_WIDTH         => 2,
			AFI_CS_WIDTH              => 2,
			AFI_CLK_EN_WIDTH          => 2,
			AFI_DM_WIDTH              => 8,
			AFI_DQ_WIDTH              => 64,
			AFI_ODT_WIDTH             => 2,
			AFI_WRITE_DQS_WIDTH       => 4,
			AFI_RLAT_WIDTH            => 6,
			AFI_WLAT_WIDTH            => 6,
			AFI_RRANK_WIDTH           => 4,
			AFI_WRANK_WIDTH           => 4,
			MRS_MIRROR_PING_PONG_ATSO => false
		)
		port map (
			clk                   => pll0_afi_clk_clk,             --     clk.clk
			afi_addr              => c0_afi_afi_addr,              --     afi.afi_addr
			afi_ba                => c0_afi_afi_ba,                --        .afi_ba
			afi_ras_n             => c0_afi_afi_ras_n,             --        .afi_ras_n
			afi_we_n              => c0_afi_afi_we_n,              --        .afi_we_n
			afi_cas_n             => c0_afi_afi_cas_n,             --        .afi_cas_n
			afi_odt               => c0_afi_afi_odt,               --        .afi_odt
			afi_cke               => c0_afi_afi_cke,               --        .afi_cke
			afi_cs_n              => c0_afi_afi_cs_n,              --        .afi_cs_n
			afi_dqs_burst         => c0_afi_afi_dqs_burst,         --        .afi_dqs_burst
			afi_wdata_valid       => c0_afi_afi_wdata_valid,       --        .afi_wdata_valid
			afi_wdata             => c0_afi_afi_wdata,             --        .afi_wdata
			afi_dm                => c0_afi_afi_dm,                --        .afi_dm
			afi_rdata             => m0_afi_afi_rdata,             --        .afi_rdata
			afi_rst_n             => c0_afi_afi_rst_n,             --        .afi_rst_n
			afi_rdata_en          => c0_afi_afi_rdata_en,          --        .afi_rdata_en
			afi_rdata_en_full     => c0_afi_afi_rdata_en_full,     --        .afi_rdata_en_full
			afi_rdata_valid       => m0_afi_afi_rdata_valid,       --        .afi_rdata_valid
			afi_cal_success       => m0_afi_afi_cal_success,       --        .afi_cal_success
			afi_cal_fail          => m0_afi_afi_cal_fail,          --        .afi_cal_fail
			afi_wlat              => m0_afi_afi_wlat,              --        .afi_wlat
			afi_rlat              => m0_afi_afi_rlat,              --        .afi_rlat
			phy_mux_addr          => m0_phy_mux_afi_addr,          -- phy_mux.afi_addr
			phy_mux_ba            => m0_phy_mux_afi_ba,            --        .afi_ba
			phy_mux_ras_n         => m0_phy_mux_afi_ras_n,         --        .afi_ras_n
			phy_mux_we_n          => m0_phy_mux_afi_we_n,          --        .afi_we_n
			phy_mux_cas_n         => m0_phy_mux_afi_cas_n,         --        .afi_cas_n
			phy_mux_odt           => m0_phy_mux_afi_odt,           --        .afi_odt
			phy_mux_cke           => m0_phy_mux_afi_cke,           --        .afi_cke
			phy_mux_cs_n          => m0_phy_mux_afi_cs_n,          --        .afi_cs_n
			phy_mux_dqs_burst     => m0_phy_mux_afi_dqs_burst,     --        .afi_dqs_burst
			phy_mux_wdata_valid   => m0_phy_mux_afi_wdata_valid,   --        .afi_wdata_valid
			phy_mux_wdata         => m0_phy_mux_afi_wdata,         --        .afi_wdata
			phy_mux_dm            => m0_phy_mux_afi_dm,            --        .afi_dm
			phy_mux_rdata         => p0_afi_afi_rdata,             --        .afi_rdata
			phy_mux_rst_n         => m0_phy_mux_afi_rst_n,         --        .afi_rst_n
			phy_mux_rdata_en      => m0_phy_mux_afi_rdata_en,      --        .afi_rdata_en
			phy_mux_rdata_en_full => m0_phy_mux_afi_rdata_en_full, --        .afi_rdata_en_full
			phy_mux_rdata_valid   => p0_afi_afi_rdata_valid,       --        .afi_rdata_valid
			phy_mux_cal_success   => p0_afi_afi_cal_success,       --        .afi_cal_success
			phy_mux_cal_fail      => p0_afi_afi_cal_fail,          --        .afi_cal_fail
			phy_mux_wlat          => p0_afi_afi_wlat,              --        .afi_wlat
			phy_mux_rlat          => p0_afi_afi_rlat,              --        .afi_rlat
			seq_mux_addr          => s0_afi_afi_addr,              -- seq_mux.afi_addr
			seq_mux_ba            => s0_afi_afi_ba,                --        .afi_ba
			seq_mux_ras_n         => s0_afi_afi_ras_n,             --        .afi_ras_n
			seq_mux_we_n          => s0_afi_afi_we_n,              --        .afi_we_n
			seq_mux_cas_n         => s0_afi_afi_cas_n,             --        .afi_cas_n
			seq_mux_odt           => s0_afi_afi_odt,               --        .afi_odt
			seq_mux_cke           => s0_afi_afi_cke,               --        .afi_cke
			seq_mux_cs_n          => s0_afi_afi_cs_n,              --        .afi_cs_n
			seq_mux_dqs_burst     => s0_afi_afi_dqs_burst,         --        .afi_dqs_burst
			seq_mux_wdata_valid   => s0_afi_afi_wdata_valid,       --        .afi_wdata_valid
			seq_mux_wdata         => s0_afi_afi_wdata,             --        .afi_wdata
			seq_mux_dm            => s0_afi_afi_dm,                --        .afi_dm
			seq_mux_rdata         => m0_seq_mux_afi_rdata,         --        .afi_rdata
			seq_mux_rst_n         => s0_afi_afi_rst_n,             --        .afi_rst_n
			seq_mux_rdata_en      => s0_afi_afi_rdata_en,          --        .afi_rdata_en
			seq_mux_rdata_en_full => s0_afi_afi_rdata_en_full,     --        .afi_rdata_en_full
			seq_mux_rdata_valid   => m0_seq_mux_afi_rdata_valid,   --        .afi_rdata_valid
			mux_sel               => s0_mux_sel_mux_sel            -- mux_sel.mux_sel
		);

	s0 : component ddr3controller_s0
		port map (
			avl_clk                     => p0_avl_clk_clk,                     --          avl_clk.clk
			avl_reset_n                 => p0_avl_reset_reset,                 --        avl_reset.reset_n
			phasecounterselect          => s0_pll_reconfig_phasecounterselect, --     pll_reconfig.phasecounterselect
			phasestep                   => s0_pll_reconfig_phasestep,          --                 .phasestep
			phaseupdown                 => s0_pll_reconfig_phaseupdown,        --                 .phaseupdown
			scanclk                     => s0_pll_reconfig_scanclk,            --                 .scanclk
			phasedone                   => pll0_pll_reconfig_phasedone,        --                 .phasedone
			afi_init_req                => c0_afi_afi_init_req,                -- afi_init_cal_req.afi_init_req
			afi_cal_req                 => c0_afi_afi_cal_req,                 --                 .afi_cal_req
			pd_reset_n                  => s0_phase_detector_pd_reset_n,       --   phase_detector.pd_reset_n
			pd_ack                      => s0_phase_detector_pd_ack,           --                 .pd_ack
			pd_up                       => p0_phase_detector_pd_up,            --                 .pd_up
			pd_down                     => p0_phase_detector_pd_down,          --                 .pd_down
			phy_clk                     => p0_phy_phy_clk,                     --              phy.phy_clk
			phy_reset_n                 => p0_phy_phy_reset_n,                 --                 .phy_reset_n
			phy_read_latency_counter    => s0_phy_phy_read_latency_counter,    --                 .phy_read_latency_counter
			phy_afi_wlat                => s0_phy_phy_afi_wlat,                --                 .phy_afi_wlat
			phy_afi_rlat                => s0_phy_phy_afi_rlat,                --                 .phy_afi_rlat
			phy_read_increment_vfifo_fr => s0_phy_phy_read_increment_vfifo_fr, --                 .phy_read_increment_vfifo_fr
			phy_read_increment_vfifo_hr => s0_phy_phy_read_increment_vfifo_hr, --                 .phy_read_increment_vfifo_hr
			phy_read_increment_vfifo_qr => s0_phy_phy_read_increment_vfifo_qr, --                 .phy_read_increment_vfifo_qr
			phy_reset_mem_stable        => s0_phy_phy_reset_mem_stable,        --                 .phy_reset_mem_stable
			phy_cal_success             => s0_phy_phy_cal_success,             --                 .phy_cal_success
			phy_cal_fail                => s0_phy_phy_cal_fail,                --                 .phy_cal_fail
			phy_cal_debug_info          => s0_phy_phy_cal_debug_info,          --                 .phy_cal_debug_info
			phy_read_fifo_reset         => s0_phy_phy_read_fifo_reset,         --                 .phy_read_fifo_reset
			phy_vfifo_rd_en_override    => s0_phy_phy_vfifo_rd_en_override,    --                 .phy_vfifo_rd_en_override
			phy_read_fifo_q             => p0_phy_phy_read_fifo_q,             --                 .phy_read_fifo_q
			phy_write_fr_cycle_shifts   => s0_phy_phy_write_fr_cycle_shifts,   --                 .phy_write_fr_cycle_shifts
			calib_skip_steps            => p0_calib_calib_skip_steps,          --            calib.calib_skip_steps
			phy_mux_sel                 => s0_mux_sel_mux_sel,                 --          mux_sel.mux_sel
			afi_clk                     => pll0_afi_clk_clk,                   --          afi_clk.clk
			afi_reset_n                 => p0_afi_reset_reset,                 --        afi_reset.reset_n
			afi_addr                    => s0_afi_afi_addr,                    --              afi.afi_addr
			afi_ba                      => s0_afi_afi_ba,                      --                 .afi_ba
			afi_ras_n                   => s0_afi_afi_ras_n,                   --                 .afi_ras_n
			afi_we_n                    => s0_afi_afi_we_n,                    --                 .afi_we_n
			afi_cas_n                   => s0_afi_afi_cas_n,                   --                 .afi_cas_n
			afi_odt                     => s0_afi_afi_odt,                     --                 .afi_odt
			afi_cke                     => s0_afi_afi_cke,                     --                 .afi_cke
			afi_cs_n                    => s0_afi_afi_cs_n,                    --                 .afi_cs_n
			afi_dqs_burst               => s0_afi_afi_dqs_burst,               --                 .afi_dqs_burst
			afi_wdata_valid             => s0_afi_afi_wdata_valid,             --                 .afi_wdata_valid
			afi_wdata                   => s0_afi_afi_wdata,                   --                 .afi_wdata
			afi_dm                      => s0_afi_afi_dm,                      --                 .afi_dm
			afi_rdata                   => m0_seq_mux_afi_rdata,               --                 .afi_rdata
			afi_rst_n                   => s0_afi_afi_rst_n,                   --                 .afi_rst_n
			afi_rdata_en                => s0_afi_afi_rdata_en,                --                 .afi_rdata_en
			afi_rdata_en_full           => s0_afi_afi_rdata_en_full,           --                 .afi_rdata_en_full
			afi_rdata_valid             => m0_seq_mux_afi_rdata_valid          --                 .afi_rdata_valid
		);

	c0 : component ddr3controller_c0
		port map (
			afi_reset_n         => p0_afi_reset_reset,         --    afi_reset.reset_n
			afi_clk             => pll0_afi_clk_clk,           --      afi_clk.clk
			afi_half_clk        => pll0_afi_half_clk_clk,      -- afi_half_clk.clk
			local_init_done     => local_init_done,            --       status.local_init_done
			local_cal_success   => local_cal_success,          --             .local_cal_success
			local_cal_fail      => local_cal_fail,             --             .local_cal_fail
			afi_addr            => c0_afi_afi_addr,            --          afi.afi_addr
			afi_ba              => c0_afi_afi_ba,              --             .afi_ba
			afi_ras_n           => c0_afi_afi_ras_n,           --             .afi_ras_n
			afi_we_n            => c0_afi_afi_we_n,            --             .afi_we_n
			afi_cas_n           => c0_afi_afi_cas_n,           --             .afi_cas_n
			afi_odt             => c0_afi_afi_odt,             --             .afi_odt
			afi_cke             => c0_afi_afi_cke,             --             .afi_cke
			afi_cs_n            => c0_afi_afi_cs_n,            --             .afi_cs_n
			afi_dqs_burst       => c0_afi_afi_dqs_burst,       --             .afi_dqs_burst
			afi_wdata_valid     => c0_afi_afi_wdata_valid,     --             .afi_wdata_valid
			afi_wdata           => c0_afi_afi_wdata,           --             .afi_wdata
			afi_dm              => c0_afi_afi_dm,              --             .afi_dm
			afi_rdata           => m0_afi_afi_rdata,           --             .afi_rdata
			afi_rst_n           => c0_afi_afi_rst_n,           --             .afi_rst_n
			afi_mem_clk_disable => c0_afi_afi_mem_clk_disable, --             .afi_mem_clk_disable
			afi_init_req        => c0_afi_afi_init_req,        --             .afi_init_req
			afi_cal_req         => c0_afi_afi_cal_req,         --             .afi_cal_req
			afi_rdata_en        => c0_afi_afi_rdata_en,        --             .afi_rdata_en
			afi_rdata_en_full   => c0_afi_afi_rdata_en_full,   --             .afi_rdata_en_full
			afi_rdata_valid     => m0_afi_afi_rdata_valid,     --             .afi_rdata_valid
			afi_cal_success     => m0_afi_afi_cal_success,     --             .afi_cal_success
			afi_cal_fail        => m0_afi_afi_cal_fail,        --             .afi_cal_fail
			afi_wlat            => m0_afi_afi_wlat,            --             .afi_wlat
			afi_rlat            => m0_afi_afi_rlat,            --             .afi_rlat
			avl_ready           => avl_ready,                  --          avl.waitrequest_n
			avl_burstbegin      => avl_burstbegin,             --             .beginbursttransfer
			avl_addr            => avl_addr,                   --             .address
			avl_rdata_valid     => avl_rdata_valid,            --             .readdatavalid
			avl_rdata           => avl_rdata,                  --             .readdata
			avl_wdata           => avl_wdata,                  --             .writedata
			avl_be              => avl_be,                     --             .byteenable
			avl_read_req        => avl_read_req,               --             .read
			avl_write_req       => avl_write_req,              --             .write
			avl_size            => avl_size                    --             .burstcount
		);

	afi_clk <= pll0_afi_clk_clk;

	afi_half_clk <= pll0_afi_half_clk_clk;

	afi_reset_n <= p0_afi_reset_reset;

	pll_write_clk <= pll0_pll_sharing_pll_write_clk;

	pll_capture1_clk <= pll0_pll_sharing_pll_capture1_clk;

	pll_capture0_clk <= pll0_pll_sharing_pll_capture0_clk;

	pll_mem_clk <= pll0_pll_sharing_pll_mem_clk;

	pll_locked <= pll0_pll_sharing_pll_locked;

end architecture rtl; -- of ddr3controller_0002
