-- ---------------------------------------------------------------------
-- @file : arbitration.vhd
-- ---------------------------------------------------------------------
--
-- Author: Klaus Schleisiek
-- Last change: KS 11.03.2021 18:32:52
-- Project : arbitration test
-- Language : VHDL-2008
--
-- ---------------------------------------------------------------------
LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.NUMERIC_STD.ALL;

ENTITY bench IS
END bench;

ARCHITECTURE testbench OF bench IS

SIGNAL clk, clk_en            : STD_LOGIC;
SIGNAL reset                  : STD_LOGIC;

SIGNAL req1, req2, req3       : STD_LOGIC;
SIGNAL grant1, grant2, grant3 : STD_LOGIC; -- synchronous grant output

BEGIN

reset <= '1', '0' AFTER 100 ns;

clk_en <= '0' WHEN  (req1 AND grant1) = '1' OR (req2 AND grant2) = '1' OR (req3 AND grant3) = '1'  ELSE  '1';

arbitrator: PROCESS (clk, reset)
BEGIN
   IF  reset = '1'  THEN
      grant1 <= '0';
      grant2 <= '0';
      grant3 <= '0';
   ELSIF  rising_edge(clk)  THEN
      IF  clk_en = '1'  THEN
         IF  req1 = '1'  THEN
            grant1 <= '1';
         ELSIF  req2 = '1'  THEN
            grant2 <= '1';
         ELSIF  req3 = '1'  THEN
            grant3 <= '1';
         END IF;
      END IF;
      IF  req1 = '0'  THEN
         grant1 <= '0';
      END IF;
      IF  req2 = '0'  THEN
         grant2 <= '0';
      END IF;
      IF  req3 = '0'  THEN
         grant3 <= '0';
      END IF;
   END IF;
END PROCESS arbitrator;

parallel_proc1: PROCESS
BEGIN
   req1 <= '0';
   WAIT FOR 270 ns;
   req1 <= '1';
   WAIT UNTIL grant1 <= '1';
   WAIT FOR 40 ns;
   req1 <= '0';
   WAIT FOR 150 ns;
   req1 <= '1';
   WAIT UNTIL grant1 <= '1';
   WAIT FOR 40 ns;
   req1 <= '0';
   WAIT;
END PROCESS parallel_proc1;

parallel_proc2: PROCESS
BEGIN
   req2 <= '0';
   WAIT FOR 280 ns;
   req2 <= '1';
   WAIT UNTIL grant2 <= '1';
   WAIT FOR 160 ns;
   req2 <= '0';
   WAIT;
END PROCESS parallel_proc2;

parallel_proc3: PROCESS
BEGIN
   req3 <= '0';
   WAIT FOR 350 ns;
   req3 <= '1';
   WAIT UNTIL grant3 <= '1';
   WAIT FOR 40 ns;
   req3 <= '0';
   WAIT;
END PROCESS parallel_proc3;

oscillator: PROCESS
BEGIN
  clk <= '0';
  WAIT FOR 150 ns;
  LOOP
    WAIT FOR 50 ns;
    clk <= '1';
    WAIT FOR 50 ns;
    clk <= '0';
  END LOOP;
END PROCESS oscillator;

END testbench;