/************************************************************\
 **  Copyright (c) 2011-2021 Anlogic, Inc.
 **  All Right Reserved.
\************************************************************/
/************************************************************\
 ** Log	:	This file is generated by Anlogic IP Generator.
 ** File	:	/home/olaf/sources/AnyLogic/Projekte/Softcore_6502/MyRam.v
 ** Date	:	1970 01 01
 ** TD version	:	4.2.885
\************************************************************/

`timescale 1ns / 1ps

module MyRam ( 
	doa, dia, addra, clka, wea, rsta, 
	dob, dib, addrb, ceb, clkb, web, rstb
);

	output [7:0] doa;
	output [7:0] dob;


	input  [7:0] dia;
	input  [7:0] dib;
	input  [11:0] addra;
	input  [11:0] addrb;
	input  wea;
	input  web;
	input  ceb;
	input  clka;
	input  clkb;
	input  rsta;
	input  rstb;




	EG_LOGIC_BRAM #( .DATA_WIDTH_A(8),
				.DATA_WIDTH_B(8),
				.ADDR_WIDTH_A(12),
				.ADDR_WIDTH_B(12),
				.DATA_DEPTH_A(4096),
				.DATA_DEPTH_B(4096),
				.MODE("DP"),
				.REGMODE_A("OUTREG"),
				.REGMODE_B("OUTREG"),
				.WRITEMODE_A("NORMAL"),
				.WRITEMODE_B("NORMAL"),
				.RESETMODE("SYNC"),
				.IMPLEMENT("32K"),
				.INIT_FILE("rom.mif"),
				.FILL_ALL("NONE"))
			inst(
				.dia(dia),
				.dib(dib),
				.addra(addra),
				.addrb(addrb),
				.cea(1'b1),
				.ceb(ceb),
				.ocea(1'b1),
				.oceb(1'b1),
				.clka(clka),
				.clkb(clkb),
				.wea(wea),
				.web(web),
				.bea(1'b0),
				.beb(1'b0),
				.rsta(rsta),
				.rstb(rstb),
				.doa(doa),
				.dob(dob));


endmodule