.nolist .include "tn2313def.inc" ; Define device ATtiny2313 .list .macro WriteSram ; (register, const) ldi XL, low(SRAM_START) ldi XH, high(SRAM_START) ldi rmp, 0 j0: cpi rmp, @1 breq j1 st X+, @0 inc rmp rjmp j0 j1: ldi XL, low(SRAM_START) ldi XH, high(SRAM_START) .endmacro ; ***Konstanten*** .equ F_CPU = 10000000 ;.equ F_CPU = 26800000 .equ F_ICR = 256 .equ PWM = F_CPU/F_ICR .equ BAUD = 31250 .equ BRC = (F_CPU/16/BAUD)-1 .equ MAXBUF = 40 ; ***Defs*** .def rsreg = r15 .def rmp = r16 .def rmp2 = r17 .def rudr = r18 .def rkeyoff = r19 .def rstate = r20 .def rchannel = r21 .def rpkl = r22 .def rpkh = r23 .def rbuf = r24 .def rmp3 = r25 .def rZero = r0 .def rbufmax = r1 .def rp1l = r3 .def rp1h = r4 .def rcheck = r11 .def rkey2 = r12 .def rkey3 = r13 ; ***SRAM*** .dseg .org SRAM_START .cseg .org 000000 ;Vectorinit rjmp Main ; Reset vector reti ; INT0 reti ; INT1 reti ; ICP1 reti ; OC1A reti ; OVF1 ersatz! ; rjmp time ; OVF1 reti ; OVF0 rjmp uartrx_isr ; URXC reti ; UDRE reti ; UTXC reti ; ACI reti ; PCI reti ; OC1B reti ; OC0A reti ; OC0B reti ; USI_START reti ; USI_OVF reti ; ERDY reti ; WDT ;ISRs here uartrx_isr: in rsreg, SREG ;Endlicher Automat ; T_T ; |o o| ; |_-_| ; |=[:::]=| ; ]=' [___] '=[ ; /+|_|+\ ; |x| |x| ;etwas fett fuer eine isr... in rudr, UDR cpi rstate, 0 breq s0 cpi rstate, 1 breq s1 cpi rstate, 2 breq s2 s0: cpi rudr, 0x80 brne bye3 ldi rstate, 2 bye3: cpi rudr, 0x90 brne bye0 ldi rstate, 1 bye0: out SREG, rsreg reti s1: cpi rudr, 0x80 ; ?!? muss ich wirklich? brne baibai0 ldi rstate, 2 out SREG, rsreg reti baibai0: ;Alles kleiner 96 wird akzeptiert cpi rudr, 0x60 brsh bye1 ;key speichern mov rbuf, rudr ldi ZH, HIGH(keys*2) ldi ZL, LOW(keys*2) subi rbuf, 9 ;verdoppeln da Woerter statt bytes lsl rbuf ;nun springen zum richtigen Arraypunkt add ZL, rbuf adc ZH, rZero ;laden aus flash in phasensummanden lpm rpkl, Z+ lpm rpkh, Z ;channel 0 ld rchannel, Y tst rchannel brne bye5 st Y, rudr std Y+1, rpkl std Y+2, rpkh rjmp bye1 bye5: ;channel 1 ldd rchannel, Y+5 tst rchannel brne bye6 std Y+5, rudr std Y+6, rpkl std Y+7, rpkh rjmp bye1 bye6: ; ;channel 2 ldd rchannel, Y+10 tst rchannel brne bye1 std Y+10, rudr std Y+11, rpkl std Y+12, rpkh bye1: ldi rstate, 0 out SREG, rsreg reti s2: cpi rudr, 0x80 ; ?!? muss ich wirklich? brne baibai1 ldi rstate, 2 out SREG, rsreg reti baibai1: ;check channel 0 ld rchannel, Y cp rchannel, rudr brne bye2 ;key off slow! sbr rkeyoff, (1<<0) ; set bit 0 rjmp bye10 bye2: ;check channel 1 ldd rchannel, Y+5 cp rchannel, rudr brne bye9 ;key off slow 2! sbr rkeyoff, (1<<1) ;set bit 1 rjmp bye10 bye9: ;check channel 2 ldd rchannel, Y+10 cp rchannel, rudr brne bye10 ;key off slow 2! sbr rkeyoff, (1<<2) ;set bit 2 bye10: ;check channel 2 ldi rstate, 0 out SREG, rsreg reti ;Main prog Main: ;init Stack pointer ldi rmp,LOW(RAMEND) out SPL,rmp ;init SRAM pointer ldi YL, LOW(SRAM_START) ldi YH, HIGH(SRAM_START) WriteSram rZero, 50 ; SRAM mit 0en init ;init Zero register ldi rmp, 0 mov rZero, rmp ;init Buffer fuer uart ldi rmp, LOW(SRAM_START)+MAXBUF mov rbufmax, rmp ;DDB init sbi DDRB, DDB3 ;UART RX init ldi rmp, HIGH(BRC) out UBRRH, rmp ldi rmp, LOW(BRC) out UBRRL, rmp ldi rmp, (1<