----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 27.03.2021 13:14:44
-- Design Name: 
-- Module Name: fsm - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use ieee.numeric_std.all;
use IEEE.std_logic_unsigned.all;
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsm is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           ain : in  STD_LOGIC;
           LED : out STD_LOGIC_VECTOR (7 downto 4);
           LED0 : out STD_LOGIC);
end fsm;

architecture Behavioral of fsm is


type state_type is (S0,S1,S2);
signal state, next_state : state_type;
signal wr_en : std_logic;
signal count : std_logic_vector (3 downto 0);

begin


FSM_REGISTER : process(clk, reset)

    begin
        if reset = '1' then
            count <= "0000";
            state <= S0;
            LED0 <= '0';
        elsif rising_edge(clk) then
            state <= next_state;
                
                if count = "0000" then
                    LED0 <= '1';
                elsif count = "0011" then
                    LED0 <= '1';
                elsif count = "0110" then
                    LED0 <= '1';
                elsif count = "1001" then
                    LED0 <= '1';
                elsif count = "1100" then
                    LED0 <= '1';
                elsif count = "1111" then
                    LED0 <= '1';
                else
                    LED0 <= '0';
                end if;
            
                
            if wr_en = '1' then
                if count = "1111" then
                    count <= "0000";
                else
                    count <= count + '1';
                end if;
            end if;
        end if;
        
       
end process FSM_REGISTER;
LED <= count;
FSM_COMB : process(all)
    begin
        wr_en <= '0';
               
        case state is
       
            when  S0 =>
                if ain = '1' then
                    next_state <= S2;
                else
                   next_state <= S1;
                end if;
            
                
            when S1 =>
                wr_en <= '0';
                if ain = '1' then
                    next_state <= S2;
                else
                    next_state <= S0;
                end if;
                
            when S2 =>
                wr_en <= '1';
                if ain = '1' then
                   next_state <= state;
                else
                    next_state <= S0;
                end if;   
                
                   
         end case;

end process FSM_COMB;
       
              


end Behavioral;