----------------------------------------------------------------------------------
-- Company: 
-- Engineer: 
-- 
-- Create Date: 20.03.2021 18:30:48
-- Design Name: 
-- Module Name: fsm - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsm is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           ain : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(3 downto 0);
           yout : out STD_LOGIC);
end fsm;

architecture Behavioral of fsm is

type state_type is (S0,S1,S2,S3,S4,S5,S6,S7,S8,S9,S10,S11,S12,S13,S14,S15);
signal state, next_state : state_type;


signal yout_int : std_logic := '0';
signal count_int : std_logic_vector(3 downto 0) := (others => '0');
signal wr_en : std_logic;
begin

sync_proc : process(clk)
begin
    if rising_edge(clk) then
        if (reset = '1') then
            state <= S0;
         else
            state <= next_state;
              
        end if;
    end if;

end process;


output_decode : process(state,ain,reset)

begin
    yout <= '0';
    count <= "0000";
              
      case(state) is
        when S0 => 
            count <= "0000";
            if reset = '1' then    
                yout <= '0';
            elsif ain = '1' then
                yout <= '1';
            else
                yout <= '0';
            end if;
            
        when S1 =>
            count <= "0001";
            
 
        when S2 => 
            count <= "0010";   
            
        when S3 =>
            count <= "0011";
            if ain = '1' then    
                yout <= '1';
            else
                yout <= '0';
            end if;
                        
        when S4 => 
            count <= "0100";
            
        when S5 =>
            count <= "0101";
 
        when S6 => 
            count <= "0110";
            if ain = '1' then    
                yout <= '1';
            else
                yout <= '0';
            end if;
            
        when S7 =>
             count <= "0111"; 

        when S8 => 
            count <= "1000";
            
        when S9 =>
            count <= "1001";
            if ain = '1' then    
                yout <= '1';
            else
                yout <= '0';
            end if;
 
        when S10 => 
            count <= "1010";
            
        when S11 =>
            count <= "1011";
                        
        when S12 => 
            count <= "1100";
            if ain = '1' then    
                yout <= '1';
            else
                yout <= '0';
            end if;
            
        when S13 =>
            count <= "1101";
 
        when S14 => 
            count <= "1110";
            
        when S15 =>
            count <= "1111";
            if ain = '1' then    
                yout <= '1';
            else
                yout <= '0';
            end if;     
        
        when others =>
            count <= "0000";
           
        end case;
        
                
                
                
     
    
    

end process;

next_state_decode : process(state, ain)
begin
    
      case(state) is
        when S0 => 
            if ain = '1' then
                next_state <= S1;
            else
                next_state <= state;
            end if;   
            
        when S1 =>
            if ain = '1' then
                next_state <= S2;
            else
                next_state <= state;
            end if; 
 
        when S2 => 
            if ain = '1' then
                next_state <= S3;
            else
                next_state <= state;
            end if;   
            
        when S3 =>
            if ain = '1' then
                next_state <= S4;
            else
                next_state <= state;
            end if;
                        
        when S4 => 
            if ain = '1' then
                next_state <= S5;
            else
                next_state <= state;
            end if;   
            
        when S5 =>
            if ain = '1' then
                next_state <= S6;
            else
                next_state <= state;
            end if; 
 
        when S6 => 
            if ain = '1' then
                next_state <= S7;
            else
                next_state <= state;
            end if;   
            
        when S7 =>
            if ain = '1' then
                next_state <= S8;
            else
                next_state <= state;
            end if;                 

        when S8 => 
            if ain = '1' then
                next_state <= S9;
            else
                next_state <= state;
            end if;   
            
        when S9 =>
            if ain = '1' then
                next_state <= S10;
            else
                next_state <= state;
            end if; 
 
        when S10 => 
            if ain = '1' then
                next_state <= S11;
            else
                next_state <= state;
            end if;   
            
        when S11 =>
            if ain = '1' then
                next_state <= S12;
            else
                next_state <= state;
            end if;
                        
        when S12 => 
            if ain = '1' then
                next_state <= S13;
            else
                next_state <= state;
            end if;   
            
        when S13 =>
            if ain = '1' then
                next_state <= S14;
            else
                next_state <= state;
            end if; 
 
        when S14 => 
            if ain = '1' then
                next_state <= S15;
            else
                next_state <= state;
            end if;   
            
        when S15 =>
            if ain = '1' then
                next_state <= S0;
            else
                next_state <= state;
            end if;   
        
        when others =>
            next_state <= S0;           
            
       end case;
 end process;



end Behavioral;