# Reading pref.tcl
# do {.\testsys\testbench\mentor\init.do}
# external_editor
# reading modelsim.ini
# [exec] file_copy
# List Of Command Line Aliases
# 
# file_copy                                         -- Copy ROM/RAM files to simulation directory
# 
# dev_com                                           -- Compile device library files
# 
# com                                               -- Compile the design files in correct order
# 
# elab                                              -- Elaborate top level design
# 
# elab_debug                                        -- Elaborate the top level design with -voptargs=+acc option
# 
# ld                                                -- Compile all the design files and elaborate the top level design
# 
# ld_debug                                          -- Compile all the design files and elaborate the top level design with -voptargs=+acc
# 
# 
# 
# List Of Variables
# 
# TOP_LEVEL_NAME                                    -- Top level module name.
#                                                      For most designs, this should be overridden
#                                                      to enable the elab/elab_debug aliases.
# 
# SYSTEM_INSTANCE_NAME                              -- Instantiated system module name inside top level module.
# 
# QSYS_SIMDIR                                       -- Platform Designer base simulation directory.
# 
# QUARTUS_INSTALL_DIR                               -- Quartus installation directory.
# 
# USER_DEFINED_COMPILE_OPTIONS                      -- User-defined compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_ELAB_OPTIONS                         -- User-defined elaboration options, added to elab/elab_debug aliases.
# 
# USER_DEFINED_VHDL_COMPILE_OPTIONS                 -- User-defined vhdl compile options, added to com/dev_com aliases.
# 
# USER_DEFINED_VERILOG_COMPILE_OPTIONS              -- User-defined verilog compile options, added to com/dev_com aliases.
com
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:50 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/verbosity_pkg.sv -work altera_common_sv_packages 
# -- Compiling package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 10:17:50 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:50 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/avalon_mm_pkg.sv -work altera_common_sv_packages 
# -- Compiling package avalon_mm_pkg
# -- Importing package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 10:17:50 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:50 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/avalon_utilities_pkg.sv -work altera_common_sv_packages 
# -- Compiling package avalon_utilities_pkg
# 
# Top level modules:
# 	--none--
# End time: 10:17:50 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:50 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_merlin_slave_translator.sv -L altera_common_sv_packages -work uart_s1_translator 
# -- Compiling module altera_merlin_slave_translator
# 
# Top level modules:
# 	altera_merlin_slave_translator
# End time: 10:17:50 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:50 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_merlin_master_translator.sv -L altera_common_sv_packages -work mm_master_bfm_0_m0_translator 
# -- Compiling module altera_merlin_master_translator
# 
# Top level modules:
# 	altera_merlin_master_translator
# End time: 10:17:50 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:50 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/submodules/testsys_mm_interconnect_0.v -work mm_interconnect_0 
# -- Compiling module testsys_mm_interconnect_0
# 
# Top level modules:
# 	testsys_mm_interconnect_0
# End time: 10:17:50 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:50 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/submodules/testsys_uart.v -work uart 
# -- Compiling module testsys_uart_tx
# -- Compiling module testsys_uart_rx_stimulus_source
# -- Compiling module testsys_uart_rx
# -- Compiling module testsys_uart_regs
# -- Compiling module testsys_uart
# 
# Top level modules:
# 	testsys_uart_rx_stimulus_source
# 	testsys_uart
# End time: 10:17:51 on Apr 04,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:51 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_mm_master_bfm.sv -L altera_common_sv_packages -work mm_master_bfm_0 
# -- Compiling module altera_avalon_mm_master_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# -- Importing package altera_common_sv_packages.avalon_utilities_pkg
# 
# Top level modules:
# 	altera_avalon_mm_master_bfm
# End time: 10:17:51 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:51 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_irq_mapper.sv -L altera_common_sv_packages -work irq_mapper 
# -- Compiling module altera_irq_mapper
# 
# Top level modules:
# 	altera_irq_mapper
# End time: 10:17:51 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:51 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_interrupt_sink.sv -L altera_common_sv_packages -work testsys_inst_uart_irq_bfm 
# -- Compiling module altera_avalon_interrupt_sink
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_interrupt_sink
# End time: 10:17:51 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:51 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_conduit_bfm.sv -L altera_common_sv_packages -work testsys_inst_uart_external_connection_bfm 
# -- Compiling module altera_conduit_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_conduit_bfm
# End time: 10:17:51 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:51 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_reset_source.sv -L altera_common_sv_packages -work testsys_inst_reset_bfm 
# -- Compiling module altera_avalon_reset_source
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_reset_source
# End time: 10:17:51 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:51 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_clock_source.sv -L altera_common_sv_packages -work testsys_inst_clk_bfm 
# -- Compiling module altera_avalon_clock_source
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_clock_source
# End time: 10:17:51 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:51 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/submodules/testsys.v -work testsys_inst 
# -- Compiling module testsys
# 
# Top level modules:
# 	testsys
# End time: 10:17:52 on Apr 04,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:17:52 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/master_test_program.sv -L altera_common_sv_packages -work work 
# -- Compiling module master_test_program
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# -- Importing package altera_common_sv_packages.avalon_utilities_pkg
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(34): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(34): near ".": syntax error, unexpected '.'.
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(35): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(35): near ".": syntax error, unexpected '.'.
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(36): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(36): near ".": syntax error, unexpected '.'.
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(37): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(37): near ".": syntax error, unexpected '.'.
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(38): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(38): near ".": syntax error, unexpected '.'.
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(39): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(39): near ".": syntax error, unexpected '.'.
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(40): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(40): near ".": syntax error, unexpected '.'.
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(41): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(41): near ".": syntax error, unexpected '.'.
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(42): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(42): near ".": syntax error, unexpected '.'.
# ** Error: ./../testsys_tb/simulation/master_test_program.sv(43): (vlog-2163) Macro `uart is undefined.
# ** Error: (vlog-13069) ./../testsys_tb/simulation/master_test_program.sv(43): near ".": syntax error, unexpected '.'.
# End time: 10:17:52 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 20, Warnings: 0
# C:/intelFPGA_lite/20.1/modelsim_ase/win32aloem/vlog failed.
com
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:53 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/verbosity_pkg.sv -work altera_common_sv_packages 
# -- Compiling package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 10:18:53 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:53 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/avalon_mm_pkg.sv -work altera_common_sv_packages 
# -- Compiling package avalon_mm_pkg
# -- Importing package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 10:18:53 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:53 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/avalon_utilities_pkg.sv -work altera_common_sv_packages 
# -- Compiling package avalon_utilities_pkg
# 
# Top level modules:
# 	--none--
# End time: 10:18:53 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:53 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_merlin_slave_translator.sv -L altera_common_sv_packages -work uart_s1_translator 
# -- Compiling module altera_merlin_slave_translator
# 
# Top level modules:
# 	altera_merlin_slave_translator
# End time: 10:18:53 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:53 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_merlin_master_translator.sv -L altera_common_sv_packages -work mm_master_bfm_0_m0_translator 
# -- Compiling module altera_merlin_master_translator
# 
# Top level modules:
# 	altera_merlin_master_translator
# End time: 10:18:53 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:53 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/submodules/testsys_mm_interconnect_0.v -work mm_interconnect_0 
# -- Compiling module testsys_mm_interconnect_0
# 
# Top level modules:
# 	testsys_mm_interconnect_0
# End time: 10:18:53 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:53 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/submodules/testsys_uart.v -work uart 
# -- Compiling module testsys_uart_tx
# -- Compiling module testsys_uart_rx_stimulus_source
# -- Compiling module testsys_uart_rx
# -- Compiling module testsys_uart_regs
# -- Compiling module testsys_uart
# 
# Top level modules:
# 	testsys_uart_rx_stimulus_source
# 	testsys_uart
# End time: 10:18:53 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:53 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_mm_master_bfm.sv -L altera_common_sv_packages -work mm_master_bfm_0 
# -- Compiling module altera_avalon_mm_master_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# -- Importing package altera_common_sv_packages.avalon_utilities_pkg
# 
# Top level modules:
# 	altera_avalon_mm_master_bfm
# End time: 10:18:54 on Apr 04,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_irq_mapper.sv -L altera_common_sv_packages -work irq_mapper 
# -- Compiling module altera_irq_mapper
# 
# Top level modules:
# 	altera_irq_mapper
# End time: 10:18:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_interrupt_sink.sv -L altera_common_sv_packages -work testsys_inst_uart_irq_bfm 
# -- Compiling module altera_avalon_interrupt_sink
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_interrupt_sink
# End time: 10:18:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_conduit_bfm.sv -L altera_common_sv_packages -work testsys_inst_uart_external_connection_bfm 
# -- Compiling module altera_conduit_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_conduit_bfm
# End time: 10:18:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_reset_source.sv -L altera_common_sv_packages -work testsys_inst_reset_bfm 
# -- Compiling module altera_avalon_reset_source
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_reset_source
# End time: 10:18:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_clock_source.sv -L altera_common_sv_packages -work testsys_inst_clk_bfm 
# -- Compiling module altera_avalon_clock_source
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_clock_source
# End time: 10:18:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:54 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/submodules/testsys.v -work testsys_inst 
# -- Compiling module testsys
# 
# Top level modules:
# 	testsys
# End time: 10:18:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/master_test_program.sv -L altera_common_sv_packages -work work 
# -- Compiling module master_test_program
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# -- Importing package altera_common_sv_packages.avalon_utilities_pkg
# 
# Top level modules:
# 	master_test_program
# End time: 10:18:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:18:54 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/testsys_tb.v 
# -- Compiling module testsys_tb
# 
# Top level modules:
# 	testsys_tb
# End time: 10:18:55 on Apr 04,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
ld_debug
# [exec] dev_com
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:50 on Apr 04,2021
# vlog -reportprogress 300 C:/intelfpga_lite/20.1/quartus/eda/sim_lib/altera_primitives.v -work altera_ver 
# -- Compiling module global
# -- Compiling module carry
# -- Compiling module cascade
# -- Compiling module carry_sum
# -- Compiling module exp
# -- Compiling module soft
# -- Compiling module opndrn
# -- Compiling module row_global
# -- Compiling module TRI
# -- Compiling module lut_input
# -- Compiling module lut_output
# -- Compiling module latch
# -- Compiling module dlatch
# -- Compiling module prim_gdff
# -- Compiling module dff
# -- Compiling module dffe
# -- Compiling module dffea
# -- Compiling module dffeas
# -- Compiling module dffeas_pr
# -- Compiling module prim_gtff
# -- Compiling module tff
# -- Compiling module tffe
# -- Compiling module prim_gjkff
# -- Compiling module jkff
# -- Compiling module jkffe
# -- Compiling module prim_gsrff
# -- Compiling module srff
# -- Compiling module srffe
# -- Compiling module clklock
# -- Compiling module alt_inbuf
# -- Compiling module alt_outbuf
# -- Compiling module alt_outbuf_tri
# -- Compiling module alt_iobuf
# -- Compiling module alt_inbuf_diff
# -- Compiling module alt_outbuf_diff
# -- Compiling module alt_outbuf_tri_diff
# -- Compiling module alt_iobuf_diff
# -- Compiling module alt_bidir_diff
# -- Compiling module alt_bidir_buf
# -- Compiling UDP PRIM_GDFF_LOW
# -- Compiling UDP PRIM_GDFF_LOW_SCLR_PRIORITY
# -- Compiling UDP PRIM_GDFF_HIGH
# -- Compiling UDP PRIM_GDFF_HIGH_SCLR_PRIORITY
# 
# Top level modules:
# 	global
# 	carry
# 	cascade
# 	carry_sum
# 	exp
# 	soft
# 	opndrn
# 	row_global
# 	TRI
# 	lut_input
# 	lut_output
# 	latch
# 	dlatch
# 	dff
# 	dffe
# 	dffea
# 	dffeas
# 	dffeas_pr
# 	tff
# 	tffe
# 	jkff
# 	jkffe
# 	srff
# 	srffe
# 	clklock
# 	alt_inbuf
# 	alt_outbuf
# 	alt_outbuf_tri
# 	alt_iobuf
# 	alt_inbuf_diff
# 	alt_outbuf_diff
# 	alt_outbuf_tri_diff
# 	alt_iobuf_diff
# 	alt_bidir_diff
# 	alt_bidir_buf
# End time: 10:19:50 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:50 on Apr 04,2021
# vlog -reportprogress 300 C:/intelfpga_lite/20.1/quartus/eda/sim_lib/220model.v -work lpm_ver 
# -- Compiling module LPM_MEMORY_INITIALIZATION
# -- Compiling module LPM_HINT_EVALUATION
# -- Compiling module LPM_DEVICE_FAMILIES
# -- Compiling module lpm_constant
# -- Compiling module lpm_inv
# -- Compiling module lpm_and
# -- Compiling module lpm_or
# -- Compiling module lpm_xor
# -- Compiling module lpm_bustri
# -- Compiling module lpm_mux
# -- Compiling module lpm_decode
# -- Compiling module lpm_clshift
# -- Compiling module lpm_add_sub
# -- Compiling module lpm_compare
# -- Compiling module lpm_mult
# -- Compiling module lpm_divide
# -- Compiling module lpm_abs
# -- Compiling module lpm_counter
# -- Compiling module lpm_latch
# -- Compiling module lpm_ff
# -- Compiling module lpm_shiftreg
# -- Compiling module lpm_ram_dq
# -- Compiling module lpm_ram_dp
# -- Compiling module lpm_ram_io
# -- Compiling module lpm_rom
# -- Compiling module lpm_fifo
# -- Compiling module lpm_fifo_dc_dffpipe
# -- Compiling module lpm_fifo_dc_fefifo
# -- Compiling module lpm_fifo_dc_async
# -- Compiling module lpm_fifo_dc
# -- Compiling module lpm_inpad
# -- Compiling module lpm_outpad
# -- Compiling module lpm_bipad
# 
# Top level modules:
# 	lpm_constant
# 	lpm_inv
# 	lpm_and
# 	lpm_or
# 	lpm_xor
# 	lpm_bustri
# 	lpm_mux
# 	lpm_decode
# 	lpm_clshift
# 	lpm_add_sub
# 	lpm_compare
# 	lpm_mult
# 	lpm_divide
# 	lpm_abs
# 	lpm_counter
# 	lpm_latch
# 	lpm_ff
# 	lpm_shiftreg
# 	lpm_ram_dq
# 	lpm_ram_dp
# 	lpm_ram_io
# 	lpm_rom
# 	lpm_fifo
# 	lpm_fifo_dc
# 	lpm_inpad
# 	lpm_outpad
# 	lpm_bipad
# End time: 10:19:51 on Apr 04,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:51 on Apr 04,2021
# vlog -reportprogress 300 C:/intelfpga_lite/20.1/quartus/eda/sim_lib/sgate.v -work sgate_ver 
# -- Compiling module oper_add
# -- Compiling module oper_addsub
# -- Compiling module mux21
# -- Compiling module io_buf_tri
# -- Compiling module io_buf_opdrn
# -- Compiling module oper_mult
# -- Compiling module tri_bus
# -- Compiling module oper_div
# -- Compiling module oper_mod
# -- Compiling module oper_left_shift
# -- Compiling module oper_right_shift
# -- Compiling module oper_rotate_left
# -- Compiling module oper_rotate_right
# -- Compiling module oper_less_than
# -- Compiling module oper_mux
# -- Compiling module oper_selector
# -- Compiling module oper_decoder
# -- Compiling module oper_bus_mux
# -- Compiling module oper_latch
# 
# Top level modules:
# 	oper_add
# 	oper_addsub
# 	mux21
# 	io_buf_tri
# 	io_buf_opdrn
# 	oper_mult
# 	tri_bus
# 	oper_div
# 	oper_mod
# 	oper_left_shift
# 	oper_right_shift
# 	oper_rotate_left
# 	oper_rotate_right
# 	oper_less_than
# 	oper_mux
# 	oper_selector
# 	oper_decoder
# 	oper_bus_mux
# 	oper_latch
# End time: 10:19:51 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:51 on Apr 04,2021
# vlog -reportprogress 300 C:/intelfpga_lite/20.1/quartus/eda/sim_lib/altera_mf.v -work altera_mf_ver 
# -- Compiling module lcell
# -- Compiling module ALTERA_MF_MEMORY_INITIALIZATION
# -- Compiling module ALTERA_MF_HINT_EVALUATION
# -- Compiling module ALTERA_DEVICE_FAMILIES
# -- Compiling module dffp
# -- Compiling module pll_iobuf
# -- Compiling module stx_m_cntr
# -- Compiling module stx_n_cntr
# -- Compiling module stx_scale_cntr
# -- Compiling module MF_pll_reg
# -- Compiling module MF_stratix_pll
# -- Compiling module arm_m_cntr
# -- Compiling module arm_n_cntr
# -- Compiling module arm_scale_cntr
# -- Compiling module MF_stratixii_pll
# -- Compiling module ttn_m_cntr
# -- Compiling module ttn_n_cntr
# -- Compiling module ttn_scale_cntr
# -- Compiling module MF_stratixiii_pll
# -- Compiling module cda_m_cntr
# -- Compiling module cda_n_cntr
# -- Compiling module cda_scale_cntr
# -- Compiling module MF_cycloneiii_pll
# -- Compiling module MF_cycloneiiigl_m_cntr
# -- Compiling module MF_cycloneiiigl_n_cntr
# -- Compiling module MF_cycloneiiigl_scale_cntr
# -- Compiling module cycloneiiigl_post_divider
# -- Compiling module MF_cycloneiiigl_pll
# -- Compiling module altpll
# -- Compiling module altlvds_rx
# -- Compiling module stratix_lvds_rx
# -- Compiling module stratixgx_dpa_lvds_rx
# -- Compiling module stratixii_lvds_rx
# -- Compiling module flexible_lvds_rx
# -- Compiling module stratixiii_lvds_rx
# -- Compiling module stratixiii_lvds_rx_channel
# -- Compiling module stratixiii_lvds_rx_dpa
# -- Compiling module altlvds_tx
# -- Compiling module stratixv_local_clk_divider
# -- Compiling module stratix_tx_outclk
# -- Compiling module stratixii_tx_outclk
# -- Compiling module flexible_lvds_tx
# -- Compiling module dcfifo_dffpipe
# -- Compiling module dcfifo_fefifo
# -- Compiling module dcfifo_async
# -- Compiling module dcfifo_sync
# -- Compiling module dcfifo_low_latency
# -- Compiling module dcfifo_mixed_widths
# -- Compiling module dcfifo
# -- Compiling module altera_syncram_derived
# -- Compiling module altera_syncram_derived_forwarding_logic
# -- Compiling module altaccumulate
# -- Compiling module altmult_accum
# -- Compiling module altmult_add
# -- Compiling module altfp_mult
# -- Compiling module altsqrt
# -- Compiling module altclklock
# -- Compiling module altddio_in
# -- Compiling module altddio_out
# -- Compiling module altddio_bidir
# -- Compiling module altdpram
# -- Compiling module altsyncram
# -- Compiling module altsyncram_body
# -- Compiling module alt3pram
# -- Compiling module parallel_add
# -- Compiling module scfifo
# -- Compiling module altshift_taps
# -- Compiling module a_graycounter
# -- Compiling module altsquare
# -- Compiling module altera_std_synchronizer
# -- Compiling module altera_std_synchronizer_bundle
# -- Compiling module alt_cal
# -- Compiling module alt_cal_mm
# -- Compiling module alt_cal_c3gxb
# -- Compiling module alt_cal_sv
# -- Compiling module alt_cal_av
# -- Compiling module alt_aeq_s4
# -- Compiling module alt_eyemon
# -- Compiling module alt_dfe
# -- Compiling module signal_gen
# -- Compiling module jtag_tap_controller
# -- Compiling module dummy_hub
# -- Compiling module sld_virtual_jtag
# -- Compiling module sld_signaltap
# -- Compiling module altstratixii_oct
# -- Compiling module altparallel_flash_loader
# -- Compiling module altserial_flash_loader
# -- Compiling module alt_fault_injection
# -- Compiling module sld_virtual_jtag_basic
# -- Compiling module altsource_probe
# 
# Top level modules:
# 	lcell
# 	altpll
# 	altlvds_rx
# 	altlvds_tx
# 	dcfifo
# 	altaccumulate
# 	altmult_accum
# 	altmult_add
# 	altfp_mult
# 	altsqrt
# 	altclklock
# 	altddio_bidir
# 	altdpram
# 	alt3pram
# 	parallel_add
# 	scfifo
# 	altshift_taps
# 	a_graycounter
# 	altsquare
# 	altera_std_synchronizer_bundle
# 	alt_cal
# 	alt_cal_mm
# 	alt_cal_c3gxb
# 	alt_cal_sv
# 	alt_cal_av
# 	alt_aeq_s4
# 	alt_eyemon
# 	alt_dfe
# 	sld_virtual_jtag
# 	sld_signaltap
# 	altstratixii_oct
# 	altparallel_flash_loader
# 	altserial_flash_loader
# 	alt_fault_injection
# 	sld_virtual_jtag_basic
# 	altsource_probe
# End time: 10:19:52 on Apr 04,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:53 on Apr 04,2021
# vlog -reportprogress 300 -sv C:/intelfpga_lite/20.1/quartus/eda/sim_lib/altera_lnsim.sv -work altera_lnsim_ver 
# -- Compiling package altera_lnsim_functions
# -- Compiling package altera_generic_pll_functions
# -- Compiling module generic_pll
# -- Importing package altera_lnsim_functions
# -- Importing package altera_generic_pll_functions
# -- Compiling module generic_cdr
# -- Compiling module common_28nm_ram_pulse_generator
# -- Compiling module common_28nm_ram_register
# -- Compiling module common_28nm_ram_block
# -- Compiling module generic_m20k
# -- Compiling module generic_m10k
# -- Compiling module common_28nm_mlab_cell_pulse_generator
# -- Compiling module common_28nm_mlab_latch
# -- Compiling module common_28nm_mlab_cell_core
# -- Compiling module common_porta_latches
# -- Compiling module generic_28nm_hp_mlab_cell_impl
# -- Compiling module common_porta_registers
# -- Compiling module generic_28nm_lc_mlab_cell_impl
# -- Compiling module common_28nm_lutram_register
# -- Compiling module generic_14nm_mlab_cell_impl
# -- Compiling module common_14nm_lutram_register
# -- Compiling module generic_mux
# -- Compiling module generic_device_pll
# -- Compiling module altera_mult_add
# -- Compiling module altera_mult_add_rtl
# -- Compiling module ama_signed_extension_function
# -- Compiling module ama_dynamic_signed_function
# -- Compiling module ama_register_function
# -- Compiling module ama_register_with_ext_function
# -- Compiling module ama_data_split_reg_ext_function
# -- Compiling module ama_coef_reg_ext_function
# -- Compiling module ama_adder_function
# -- Compiling module ama_multiplier_function
# -- Compiling module ama_preadder_function
# -- Compiling module ama_chainout_adder_accumulator_function
# -- Compiling module ama_systolic_adder_function
# -- Compiling module ama_scanchain
# -- Compiling module ama_latency_function
# -- Compiling module altera_pll_reconfig_tasks
# -- Compiling module altera_syncram
# -- Compiling module altera_syncram_forwarding_logic
# -- Compiling module ALTERA_LNSIM_MEMORY_INITIALIZATION
# -- Compiling module altera_stratixv_pll
# -- Compiling module altera_arriav_pll
# -- Compiling module altera_arriavgz_pll
# -- Compiling module altera_cyclonev_pll
# -- Compiling module altera_pll
# -- Compiling module dps_extra_kick
# -- Compiling module dprio_init
# -- Compiling module dps_pulse_gen
# -- Compiling module altera_iopll
# -- Compiling module dps_pulse_gen_iopll
# -- Compiling module twentynm_iopll_arlol
# -- Compiling module fourteennm_altera_iopll
# -- Compiling module dps_pulse_gen_fourteennm_iopll
# -- Compiling package fourteennm_iopll_functions
# -- Compiling module fourteennm_simple_iopll
# -- Importing package fourteennm_iopll_functions
# -- Compiling module fourteennm_sub_iopll
# -- Compiling module twentynm_iopll_ip
# -- Compiling module altera_iopll_rotation_lcells
# -- Compiling module altera_pll_dps_lcell_comb
# -- Compiling module iopll_bootstrap
# 
# Top level modules:
# 	generic_cdr
# 	generic_m20k
# 	generic_m10k
# 	common_porta_latches
# 	generic_28nm_hp_mlab_cell_impl
# 	generic_28nm_lc_mlab_cell_impl
# 	generic_14nm_mlab_cell_impl
# 	generic_mux
# 	generic_device_pll
# 	altera_mult_add
# 	altera_pll_reconfig_tasks
# 	altera_syncram
# 	altera_pll
# 	altera_iopll
# 	fourteennm_altera_iopll
# 	fourteennm_simple_iopll
# End time: 10:19:53 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:53 on Apr 04,2021
# vlog -reportprogress 300 C:/intelfpga_lite/20.1/quartus/eda/sim_lib/cycloneive_atoms.v -work cycloneive_ver 
# -- Compiling UDP CYCLONEIVE_PRIM_DFFE
# -- Compiling UDP CYCLONEIVE_PRIM_DFFEAS
# -- Compiling UDP CYCLONEIVE_PRIM_DFFEAS_HIGH
# -- Compiling module cycloneive_dffe
# -- Compiling module cycloneive_mux21
# -- Compiling module cycloneive_mux41
# -- Compiling module cycloneive_and1
# -- Compiling module cycloneive_and16
# -- Compiling module cycloneive_bmux21
# -- Compiling module cycloneive_b17mux21
# -- Compiling module cycloneive_nmux21
# -- Compiling module cycloneive_b5mux21
# -- Compiling module cycloneive_latch
# -- Compiling module cycloneive_routing_wire
# -- Compiling module cycloneive_m_cntr
# -- Compiling module cycloneive_n_cntr
# -- Compiling module cycloneive_scale_cntr
# -- Compiling module cycloneive_pll_reg
# -- Compiling module cycloneive_pll
# -- Compiling module cycloneive_lcell_comb
# -- Compiling module cycloneive_ff
# -- Compiling module cycloneive_ram_pulse_generator
# -- Compiling module cycloneive_ram_register
# -- Compiling module cycloneive_ram_block
# -- Compiling module cycloneive_mac_data_reg
# -- Compiling module cycloneive_mac_sign_reg
# -- Compiling module cycloneive_mac_mult_internal
# -- Compiling module cycloneive_mac_mult
# -- Compiling module cycloneive_mac_out
# -- Compiling module cycloneive_io_ibuf
# -- Compiling module cycloneive_io_obuf
# -- Compiling module cycloneive_ddio_out
# -- Compiling module cycloneive_ddio_oe
# -- Compiling module cycloneive_pseudo_diff_out
# -- Compiling module cycloneive_io_pad
# -- Compiling module cycloneive_asmiblock
# -- Compiling module cycloneive_ena_reg
# -- Compiling module cycloneive_clkctrl
# -- Compiling module cycloneive_rublock
# -- Compiling module cycloneive_apfcontroller
# -- Compiling module cycloneive_termination_ctrl
# -- Compiling module cycloneive_termination_rupdn
# -- Compiling module cycloneive_termination
# -- Compiling module cycloneive_jtag
# -- Compiling module cycloneive_crcblock
# -- Compiling module cycloneive_oscillator
# 
# Top level modules:
# 	cycloneive_dffe
# 	cycloneive_and1
# 	cycloneive_and16
# 	cycloneive_bmux21
# 	cycloneive_b17mux21
# 	cycloneive_nmux21
# 	cycloneive_b5mux21
# 	cycloneive_pll_reg
# 	cycloneive_pll
# 	cycloneive_lcell_comb
# 	cycloneive_ff
# 	cycloneive_ram_block
# 	cycloneive_mac_mult
# 	cycloneive_mac_out
# 	cycloneive_io_ibuf
# 	cycloneive_io_obuf
# 	cycloneive_ddio_out
# 	cycloneive_ddio_oe
# 	cycloneive_pseudo_diff_out
# 	cycloneive_io_pad
# 	cycloneive_asmiblock
# 	cycloneive_clkctrl
# 	cycloneive_rublock
# 	cycloneive_apfcontroller
# 	cycloneive_termination
# 	cycloneive_jtag
# 	cycloneive_crcblock
# 	cycloneive_oscillator
# End time: 10:19:54 on Apr 04,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# [exec] com
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/verbosity_pkg.sv -work altera_common_sv_packages 
# -- Compiling package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 10:19:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/avalon_mm_pkg.sv -work altera_common_sv_packages 
# -- Compiling package avalon_mm_pkg
# -- Importing package verbosity_pkg
# 
# Top level modules:
# 	--none--
# End time: 10:19:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/avalon_utilities_pkg.sv -work altera_common_sv_packages 
# -- Compiling package avalon_utilities_pkg
# 
# Top level modules:
# 	--none--
# End time: 10:19:54 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:54 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_merlin_slave_translator.sv -L altera_common_sv_packages -work uart_s1_translator 
# -- Compiling module altera_merlin_slave_translator
# 
# Top level modules:
# 	altera_merlin_slave_translator
# End time: 10:19:55 on Apr 04,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:55 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_merlin_master_translator.sv -L altera_common_sv_packages -work mm_master_bfm_0_m0_translator 
# -- Compiling module altera_merlin_master_translator
# 
# Top level modules:
# 	altera_merlin_master_translator
# End time: 10:19:55 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:55 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/submodules/testsys_mm_interconnect_0.v -work mm_interconnect_0 
# -- Compiling module testsys_mm_interconnect_0
# 
# Top level modules:
# 	testsys_mm_interconnect_0
# End time: 10:19:55 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:55 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/submodules/testsys_uart.v -work uart 
# -- Compiling module testsys_uart_tx
# -- Compiling module testsys_uart_rx_stimulus_source
# -- Compiling module testsys_uart_rx
# -- Compiling module testsys_uart_regs
# -- Compiling module testsys_uart
# 
# Top level modules:
# 	testsys_uart_rx_stimulus_source
# 	testsys_uart
# End time: 10:19:55 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:55 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_mm_master_bfm.sv -L altera_common_sv_packages -work mm_master_bfm_0 
# -- Compiling module altera_avalon_mm_master_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# -- Importing package altera_common_sv_packages.avalon_utilities_pkg
# 
# Top level modules:
# 	altera_avalon_mm_master_bfm
# End time: 10:19:55 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:55 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_irq_mapper.sv -L altera_common_sv_packages -work irq_mapper 
# -- Compiling module altera_irq_mapper
# 
# Top level modules:
# 	altera_irq_mapper
# End time: 10:19:55 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:55 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_interrupt_sink.sv -L altera_common_sv_packages -work testsys_inst_uart_irq_bfm 
# -- Compiling module altera_avalon_interrupt_sink
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_interrupt_sink
# End time: 10:19:55 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:55 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_conduit_bfm.sv -L altera_common_sv_packages -work testsys_inst_uart_external_connection_bfm 
# -- Compiling module altera_conduit_bfm
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_conduit_bfm
# End time: 10:19:55 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:55 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_reset_source.sv -L altera_common_sv_packages -work testsys_inst_reset_bfm 
# -- Compiling module altera_avalon_reset_source
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_reset_source
# End time: 10:19:56 on Apr 04,2021, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:56 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/submodules/altera_avalon_clock_source.sv -L altera_common_sv_packages -work testsys_inst_clk_bfm 
# -- Compiling module altera_avalon_clock_source
# -- Importing package altera_common_sv_packages.verbosity_pkg
# 
# Top level modules:
# 	altera_avalon_clock_source
# End time: 10:19:56 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:56 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/submodules/testsys.v -work testsys_inst 
# -- Compiling module testsys
# 
# Top level modules:
# 	testsys
# End time: 10:19:56 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:56 on Apr 04,2021
# vlog -reportprogress 300 -sv ./../testsys_tb/simulation/master_test_program.sv -L altera_common_sv_packages -work work 
# -- Compiling module master_test_program
# -- Importing package altera_common_sv_packages.verbosity_pkg
# -- Importing package altera_common_sv_packages.avalon_mm_pkg
# -- Importing package altera_common_sv_packages.avalon_utilities_pkg
# 
# Top level modules:
# 	master_test_program
# End time: 10:19:56 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# Model Technology ModelSim - Intel FPGA Edition vlog 2020.1 Compiler 2020.02 Feb 28 2020
# Start time: 10:19:56 on Apr 04,2021
# vlog -reportprogress 300 ./../testsys_tb/simulation/testsys_tb.v 
# -- Compiling module testsys_tb
# 
# Top level modules:
# 	testsys_tb
# End time: 10:19:56 on Apr 04,2021, Elapsed time: 0:00:00
# Errors: 0, Warnings: 0
# [exec] elab_debug
# vsim -voptargs="+acc" -t ps -L work -L work_lib -L altera_common_sv_packages -L uart_s1_translator -L mm_master_bfm_0_m0_translator -L mm_interconnect_0 -L uart -L mm_master_bfm_0 -L irq_mapper -L testsys_inst_uart_irq_bfm -L testsys_inst_uart_external_connection_bfm -L testsys_inst_reset_bfm -L testsys_inst_clk_bfm -L testsys_inst -L altera_ver -L lpm_ver -L sgate_ver -L altera_mf_ver -L altera_lnsim_ver -L cycloneive_ver testsys_tb 
# Start time: 10:19:56 on Apr 04,2021
# Loading work.testsys_tb
# Loading testsys_inst.testsys
# Loading sv_std.std
# Loading altera_common_sv_packages.avalon_utilities_pkg
# Loading altera_common_sv_packages.verbosity_pkg
# Loading altera_common_sv_packages.avalon_mm_pkg
# Loading mm_master_bfm_0.altera_avalon_mm_master_bfm
# Loading uart.testsys_uart
# Loading uart.testsys_uart_tx
# Loading uart.testsys_uart_rx
# Loading altera_mf_ver.altera_std_synchronizer
# Loading uart.testsys_uart_regs
# Loading mm_interconnect_0.testsys_mm_interconnect_0
# Loading mm_master_bfm_0_m0_translator.altera_merlin_master_translator
# Loading uart_s1_translator.altera_merlin_slave_translator
# Loading testsys_inst_clk_bfm.altera_avalon_clock_source
# Loading testsys_inst_reset_bfm.altera_avalon_reset_source
# Loading testsys_inst_uart_external_connection_bfm.altera_conduit_bfm
# Loading testsys_inst_uart_irq_bfm.altera_avalon_interrupt_sink
# Loading irq_mapper.altera_irq_mapper
# Loading work.master_test_program
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'mm_master_bfm_0'.  Expected 25, found 24.
#    Time: 0 ps  Iteration: 0  Instance: /testsys_tb/testsys_inst/mm_master_bfm_0 File: ./../testsys_tb/simulation/submodules/testsys.v Line: 62
# ** Warning: (vsim-3722) ./../testsys_tb/simulation/submodules/testsys.v(62): [TFMPC] - Missing connection for port 'avm_writeresponserequest'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'uart'.  Expected 14, found 12.
#    Time: 0 ps  Iteration: 0  Instance: /testsys_tb/testsys_inst/uart File: ./../testsys_tb/simulation/submodules/testsys.v Line: 89
# ** Warning: (vsim-3722) ./../testsys_tb/simulation/submodules/testsys.v(89): [TFMPC] - Missing connection for port 'dataavailable'.
# ** Warning: (vsim-3722) ./../testsys_tb/simulation/submodules/testsys.v(89): [TFMPC] - Missing connection for port 'readyfordata'.
do wave.do
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/baud_divisor'.
# Executing ONERROR command at macro ./wave.do line 137
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/clk'.
# Executing ONERROR command at macro ./wave.do line 138
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/clk_en'.
# Executing ONERROR command at macro ./wave.do line 139
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/d1_stim_data'.
# Executing ONERROR command at macro ./wave.do line 140
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/delayed_unxrx_char_readyxx0'.
# Executing ONERROR command at macro ./wave.do line 141
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/do_send_stim_data'.
# Executing ONERROR command at macro ./wave.do line 142
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/pickup_pulse'.
# Executing ONERROR command at macro ./wave.do line 143
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/reset_n'.
# Executing ONERROR command at macro ./wave.do line 144
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/rx_char_ready'.
# Executing ONERROR command at macro ./wave.do line 145
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/rxd'.
# Executing ONERROR command at macro ./wave.do line 146
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/source_rxd'.
# Executing ONERROR command at macro ./wave.do line 147
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stim_data'.
# Executing ONERROR command at macro ./wave.do line 148
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/unused_empty'.
# Executing ONERROR command at macro ./wave.do line 149
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/unused_overrun'.
# Executing ONERROR command at macro ./wave.do line 150
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/unused_ready'.
# Executing ONERROR command at macro ./wave.do line 151
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/baud_clk_en'.
# Executing ONERROR command at macro ./wave.do line 152
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/baud_divisor'.
# Executing ONERROR command at macro ./wave.do line 153
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/baud_rate_counter'.
# Executing ONERROR command at macro ./wave.do line 154
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/baud_rate_counter_is_zero'.
# Executing ONERROR command at macro ./wave.do line 155
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/begintransfer'.
# Executing ONERROR command at macro ./wave.do line 156
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/clk'.
# Executing ONERROR command at macro ./wave.do line 157
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/clk_en'.
# Executing ONERROR command at macro ./wave.do line 158
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/do_force_break'.
# Executing ONERROR command at macro ./wave.do line 159
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/do_load_shifter'.
# Executing ONERROR command at macro ./wave.do line 160
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/do_shift'.
# Executing ONERROR command at macro ./wave.do line 161
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/pre_txd'.
# Executing ONERROR command at macro ./wave.do line 162
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/reset_n'.
# Executing ONERROR command at macro ./wave.do line 163
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/shift_done'.
# Executing ONERROR command at macro ./wave.do line 164
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/status_wr_strobe'.
# Executing ONERROR command at macro ./wave.do line 165
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/tx_data'.
# Executing ONERROR command at macro ./wave.do line 166
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/tx_load_val'.
# Executing ONERROR command at macro ./wave.do line 167
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/tx_overrun'.
# Executing ONERROR command at macro ./wave.do line 168
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/tx_ready'.
# Executing ONERROR command at macro ./wave.do line 169
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/tx_shift_empty'.
# Executing ONERROR command at macro ./wave.do line 170
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/tx_shift_reg_out'.
# Executing ONERROR command at macro ./wave.do line 171
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/tx_shift_register_contents'.
# Executing ONERROR command at macro ./wave.do line 172
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/tx_wr_strobe'.
# Executing ONERROR command at macro ./wave.do line 173
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/tx_wr_strobe_onset'.
# Executing ONERROR command at macro ./wave.do line 174
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/txd'.
# Executing ONERROR command at macro ./wave.do line 175
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_in'.
# Executing ONERROR command at macro ./wave.do line 176
# ** UI-Msg: (vish-4014) No objects found matching '/testsys_tb/testsys_inst/uart/the_testsys_uart_rx/the_testsys_uart_rx_stimulus_source/stimulus_transmitter/unxshiftxtx_shift_register_contentsxtx_shift_reg_outxx5_out'.
# Executing ONERROR command at macro ./wave.do line 177
write format wave -window .main_pane.wave.interior.cs.body.pw.wf C:/source/FPGAprojects/QSYS_UART_SIM_test/testsys/testbench/mentor/wave.do
do restart.do
# ** Note: (vsim-12125) Error and warning message counts have been reset to '0' because of 'restart'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'mm_master_bfm_0'.  Expected 25, found 24.
#    Time: 0 ps  Iteration: 0  Instance: /testsys_tb/testsys_inst/mm_master_bfm_0 File: ./../testsys_tb/simulation/submodules/testsys.v Line: 62
# ** Warning: (vsim-3722) ./../testsys_tb/simulation/submodules/testsys.v(62): [TFMPC] - Missing connection for port 'avm_writeresponserequest'.
# ** Warning: (vsim-2685) [TFMPC] - Too few port connections for 'uart'.  Expected 14, found 12.
#    Time: 0 ps  Iteration: 0  Instance: /testsys_tb/testsys_inst/uart File: ./../testsys_tb/simulation/submodules/testsys.v Line: 89
# ** Warning: (vsim-3722) ./../testsys_tb/simulation/submodules/testsys.v(89): [TFMPC] - Missing connection for port 'dataavailable'.
# ** Warning: (vsim-3722) ./../testsys_tb/simulation/submodules/testsys.v(89): [TFMPC] - Missing connection for port 'readyfordata'.
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: - Hello from altera_avalon_mm_master_bfm
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   $Revision: #1 $
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   $Date: 2019/10/06 $
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   AV_ADDRESS_W             = 32
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   AV_SYMBOL_W              = 8
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   AV_NUMSYMBOLS            = 4
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   AV_BURSTCOUNT_W          = 3
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   REGISTER_WAITREQUEST     = 1
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   AV_FIX_READ_LATENCY      = 1
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   AV_MAX_PENDING_READS     = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   AV_MAX_PENDING_WRITES    = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_READ                 = 1
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_WRITE                = 1
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_ADDRESS              = 1
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_BYTE_ENABLE          = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_BURSTCOUNT           = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_READ_DATA            = 1
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_READ_DATA_VALID      = 1
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_WRITE_DATA           = 1
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_BEGIN_TRANSFER       = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_BEGIN_BURST_TRANSFER = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_WAIT_REQUEST         = 1
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_LOCK                 = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_DEBUGACCESS          = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_TRANSACTIONID        = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_WRITERESPONSE        = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_READRESPONSE         = 0
#                    0: INFO: testsys_tb.testsys_inst.mm_master_bfm_0.__hello: -   USE_CLKEN                = 0
#                    0: INFO: ------------------------------------------------------------
#                    0: INFO: testsys_tb.testsys_inst_clk_bfm.__hello: - Hello from altera_clock_source.
#                    0: INFO: testsys_tb.testsys_inst_clk_bfm.__hello: -   $Revision: #1 $
#                    0: INFO: testsys_tb.testsys_inst_clk_bfm.__hello: -   $Date: 2019/10/06 $
#                    0: INFO: testsys_tb.testsys_inst_clk_bfm.__hello: -   CLOCK_RATE = 100000000 Hz
#                    0: INFO: ------------------------------------------------------------
#                    0: INFO: testsys_tb.testsys_inst_reset_bfm.__hello: - Hello from altera_reset_source
#                    0: INFO: testsys_tb.testsys_inst_reset_bfm.__hello: -   $Revision: #1 $
#                    0: INFO: testsys_tb.testsys_inst_reset_bfm.__hello: -   $Date: 2019/10/06 $
#                    0: INFO: testsys_tb.testsys_inst_reset_bfm.__hello: -   ASSERT_HIGH_RESET = 0
#                    0: INFO: testsys_tb.testsys_inst_reset_bfm.__hello: -   INITIAL_RESET_CYCLES = 50
#                    0: INFO: ------------------------------------------------------------
#                    0: INFO: testsys_tb.testsys_inst_reset_bfm.reset_assert: Reset asserted
#                    0: INFO: testsys_tb.testsys_inst_uart_irq_bfm.hello: - Hello from altera_avalon_interrupt_sink
#                    0: INFO: testsys_tb.testsys_inst_uart_irq_bfm.hello: -   $Revision: #1 $
#                    0: INFO: testsys_tb.testsys_inst_uart_irq_bfm.hello: -   $Date: 2019/10/06 $
#                    0: INFO: testsys_tb.testsys_inst_uart_irq_bfm.hello: -   AV_IRQ_W 	            = 1
#                    0: INFO: testsys_tb.testsys_inst_uart_irq_bfm.hello: -   ASSERT_HIGH_IRQ         = 1
#                    0: INFO: testsys_tb.testsys_inst_uart_irq_bfm.hello: -   ASYNCHRONOUS_INTERRUPT  = 0
# @                    0 master_test_program: uart pins bfm version: 20.1
#               495000: INFO: testsys_tb.testsys_inst_reset_bfm.reset_deassert: Reset deasserted
# @               495000, master_test_program: reset complete
# @             10495000, master_test_program: simulated delay
# @             10495000, master_test_program: uart_send started
# @             10995000, master_test_program: uart_send finished
# @             15995000, master_test_program: uart_send started
# @             16495000, master_test_program: uart_send finished
# @             21495000, master_test_program: uart_send started
# @             21995000, master_test_program: uart_send finished
# @             26995000, master_test_program: uart_send started
# @             27495000, master_test_program: uart_send finished
# @             32495000, master_test_program: uart_send started
# @             32995000, master_test_program: uart_send finished
# @             37995000, master_test_program: finished
quit -sim
# End time: 10:21:46 on Apr 04,2021, Elapsed time: 0:01:50
# Errors: 0, Warnings: 5
