library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counter is generic ( sys_clk :INTEGER := 50_000_000; periode : time := 40.0 ns; resolution : natural:= 5; n_Bit : natural:= 10); port( clk_in, n_reset : in std_logic; Upwm0 : in std_logic_vector(n_Bit-6 downto 0); -- 5 Bit for parallel load Upwm1 : in std_logic_vector(n_Bit-1 downto 5); -- 5 Bit for parallel load Upwm0_out : out std_logic_vector(n_Bit-6 downto 0); -- 5 Bit for parallel load Upwm1_out : out std_logic_vector(n_Bit-1 downto 5)); -- 5 Bit for parallel load end entity counter; architecture counter_a of counter is signal pwm0 :unsigned(n_Bit-6 downto 0):=(others=> '0'); signal pwm1 :unsigned(n_Bit-1 downto 5):=(others=> '0'); begin count: process(clk_in,n_reset)--sensitivity list begin if(n_reset = '0') then pwm0 <= unsigned(Upwm0); pwm1 <= unsigned(Upwm1); else if(rising_edge(clk_in)) then if(pwm0 < to_unsigned(31,n_Bit))then-- pwm1 < to_unsigned(31,n_Bit))then pwm0<= (pwm0 + 1); --pwm1<= (pwm1 + 1); else pwm0 <= unsigned(Upwm0); --pwm1 <= unsigned(Upwm1); end if; -- pwm0&1 end if; -- rising_edge end if; -- reset end process count; output: Upwm0_out <= std_logic_vector(pwm0); Upwm1_out <= std_logic_vector(pwm1); end architecture counter_a;