--Eskandari, 30.03.2021 -- 5Bit Phase Correct PWM -- library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity counter is generic ( n_Bit : natural:= 10); port( clk_in, n_reset : in std_logic Upwm0 : in std_logic_vector(n_Bit-1 downto 0); pwm0_out : out std_logic; pwm1_out : out std_logic; ); end entity counter; architecture counter_a of counter is signal pwm0 :unsigned(n_Bit-6 downto 0):= (others=>'0'); signal pwm1 :unsigned(n_Bit-1 downto 4):= (others=>'0'); signal pwm_control :std_logic:='0'; signal pwm :std_logic:='0'; begin count: process(clk_in,n_reset)--sensitivity list begin if(n_reset = '0') then pwm0 <= unsigned(Upwm0); pwm_control <= '0'; else if(rising_edge(clk_in)) then if(pwm0 < to_unsigned(31,n_Bit)) then pwm0 <= (pwm0 + 1); pwm_control <= '1'; else if(pwm0 > to_unsigned(0,n_Bit))then pwm0 <= (pwm0 - 1); pwm_control <='0'; end if;--pwm0 fall end if; -- pwm0 rise end if; -- rising_edge end if; -- reset end process count; pwm_logic:process(clk_in) begin if(rising_edge(clk_in)) then if(pwm0 => Upwm0) then pwm <= '1'; else pwm <= '0'; end if; end if; end process pwm_logic; output: Upwm0_out <= std_logic(pwm); end architecture counter_a;