library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity SOURCE is
	Port(
		CLK      : in  STD_LOGIC;
		SOP      : out STD_LOGIC;
		EOP      : out STD_LOGIC;
		DATA_IN  : in  STD_LOGIC_VECTOR(7 downto 0);
		DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0);
		SCHALTER : in  STD_LOGIC_VECTOR(9 downto 0)
	);
end SOURCE;

architecture Behavioral of SOURCE is

signal COUNT: unsigned(9 downto 0):=(others => '0');

begin
process (CLK) begin
	if rising_edge(CLK) then
		COUNT <= COUNT+1;
	end if;
end process;

end;