library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity sync_upcounter_tb is
end entity;

architecture tb of sync_upcounter_tb is

component SOURCE is
	Port(
		CLK      : in  STD_LOGIC;
		SOP      : out STD_LOGIC;
		EOP      : out STD_LOGIC;
		DATA_IN  : in  STD_LOGIC_VECTOR(7 downto 0);
		DATA_OUT : out STD_LOGIC_VECTOR(7 downto 0);
		SCHALTER : in  STD_LOGIC_VECTOR(9 downto 0)
	);
end component;

signal CLK              : STD_LOGIC := '0';
signal RST              : STD_LOGIC := '0';
signal SOP              : STD_LOGIC := '0';
signal EOP              : STD_LOGIC := '0';
signal DATA_TO_SOURCE   : unsigned(7 downto 0):=(others => '0');
signal DATA_FROM_SOURCE : STD_LOGIC_VECTOR(7 downto 0):=(others => '0');
signal SCHALTER : STD_LOGIC_VECTOR(9 downto 0):=(others => '0');
signal paketlaenge      : integer range 0 to 1023:=13;

begin

CLK <= not CLK after 10 ns;
DATA_TO_SOURCE <= DATA_TO_SOURCE + 1 after 100 ns;
SCHALTER <= STD_LOGIC_VECTOR(to_unsigned(paketlaenge,10));

uut: SOURCE
	port map(
		CLK => CLK,
		SOP => SOP,
		EOP => EOP,
		DATA_IN => STD_LOGIC_VECTOR(DATA_TO_SOURCE),
		DATA_OUT => DATA_FROM_SOURCE,
		SCHALTER => SCHALTER
	);

end;