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-- Company: 
-- Engineer: 
-- 
-- Create Date: 20.03.2021 18:30:48
-- Design Name: 
-- Module Name: fsm - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
----------------------------------------------------------------------------------


library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsm is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           ain : in STD_LOGIC;
           count : out STD_LOGIC_VECTOR(3 downto 0);
           yout : out STD_LOGIC);
end fsm;

architecture Behavioral of fsm is

type state_type is (S0,S1,S2);
signal state, next_state : state_type;


signal count_next : unsigned (3 downto 0) := "0000";
signal count_int : unsigned (3 downto 0) := "0000";

begin

sync_proc : process(clk)
begin
    if rising_edge(clk) then
        if (reset = '1') then
            state <= S0;
         else
            state <= next_state;
            count_int <= count_next;  
        end if;
    end if;

end process;


output_decode : process(state,ain,reset)

begin
    yout <= '0';
   
              
      case(state) is
        
              
       when S0 => 
            if reset = '0' then
              if ain = '1' then
                yout <= '1';
              else
                yout <= '0';
              end if;
            end if;
        when S1 =>
        
            yout <= '0';
            
 
        when S2 => 
            
            yout <= '0';
        
        when others =>
            yout <= '0';
           
        end case;
        
end process;

count <= std_logic_vector(count_int);

next_state_decode : process(state, ain, count_int)
begin
      
            
       case(state) is
                              
        when S0 => 
           
                if ain = '1' then
                    if count_int = "1111" then
                        next_state <= state;
                        count_next <= "0000";
                    else
                        next_state <= S1;
                        count_next <= count_int + 1;
                    end if;
                else
                    next_state <= state;
                    count_next <= count_int;
                   
           end if;   
            
        when S1 =>
            if ain = '1' then
                next_state <= S2;
                count_next <= count_int + 1;
            else
                next_state <= state;
                count_next <= count_int;
                                
            end if; 
 
        when S2 => 
            if ain = '1' then
                next_state <= S0;
                count_next <= count_int + 1;
            else
                next_state <= state;
                count_next <= count_int;
                
            end if;   
            
        
        when others =>
            next_state <= S0;  
            count_next <= "0000";         
            
       end case;
 end process;



end Behavioral;