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-- Company: 
-- Engineer: 
-- 
-- Create Date: 20.03.2021 18:30:48
-- Design Name: 
-- Module Name: fsm - Behavioral
-- Project Name: 
-- Target Devices: 
-- Tool Versions: 
-- Description: 
-- 
-- Dependencies: 
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
-- 
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx leaf cells in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity fsm is
    Port ( clk : in STD_LOGIC;
           reset : in STD_LOGIC;
           ain : in STD_LOGIC_VECTOR(1 downto 0);
           yout : out STD_LOGIC);
end fsm;

architecture Behavioral of fsm is

type state_type is (Idle, A1, A11, B1, B11, C1, C11);
signal state, next_state : state_type;

signal yout_int : std_logic;

begin

sync_proc : process(clk)
begin
    if rising_edge(clk) then
        if (reset = '1') then
            state <= Idle;
        else
            state <= next_state;
        end if;
    end if;

end process;


output_decode : process(state, yout_int)

begin

                 
      case(state) is
        
             
       when Idle => 
            
            yout_int <= '0';
            
        when A1 =>
        
                     
        when B1 => 
                  
            
        when C1 => 
            
           
            
        when A11 =>
        
            yout_int <= '0';
            
 
        when B11 => 
            
            yout_int <= '1';
         
            
        when C11 => 
            
            yout_int <= not yout_int;          
            
                    
        when others =>
            yout_int <= '0';
           
        end case;
        
end process;

yout <= yout_int;

next_state_decode : process(state, ain)
begin
      
       next_state <= Idle;
            
       case(state) is
                              
        when Idle => 
             
            if ain = "01" then
                next_state <= A1;                
            elsif ain = "11" then
                next_state <= B1;
            elsif ain = "10" then
                next_state <= C1;
            else
                next_state <= Idle;
            end if;   
            
        when A1 =>
             
            if ain = "00" then
                next_state <= A11;
            elsif ain = "11" then
                next_state <= B1;
            elsif ain = "10" then
                next_state <= C1;
            else
                next_state <= A1;
            end if;   
                       
        when B1 =>
             
            if ain = "00" then
                next_state <= B11;
            elsif ain = "01" then
                next_state <= A1;
            elsif ain = "10" then
                next_state <= C1;
            else
                next_state <= B1;
            end if;  
            
        when C1 =>
             
            if ain = "00" then
                next_state <= C11;
            elsif ain = "11" then
                next_state <= B1;
            elsif ain = "01" then
                next_state <= A1;
            else
                next_state <= C1;
            end if;  
        
        when A11 =>
             
            if ain = "01" then
                next_state <= A1;
            elsif ain = "11" then
                next_state <= B1;
            elsif ain = "10" then
                next_state <= C1;
            else
                next_state <= A11;
                
            end if;
            
            
        when B11 =>
             
            if ain = "01" then
                next_state <= A1;
            elsif ain = "11" then
                next_state <= B1;
            elsif ain = "10" then
                next_state <= C1;
            else
                next_state <= B11;
            end if;
            
        when C11 =>
             
            if ain = "01" then
                next_state <= A1;
                
            elsif ain = "11" then
                next_state <= B1;
            elsif ain = "10" then
                next_state <= C1;
            else
                next_state <= C11;
            end if;                
        
        when others =>
            next_state <= Idle;  
      
            
       end case;
 end process;



end Behavioral;