.include "tn13def.inc"

.def	a0	= r20
.def	a1	= r21
.def	a2	= r22
.def	a3	= r23
.def	a4	= r24
.def	a5	= r25
.def	a6	= r26
.def	a7	= r27

.def	b0	= r12
.def	b1	= r13
.def	b2	= r14
.def	b3	= r15
.def	b4	= r16
.def	b5	= r17
.def	b6	= r18
.def	b7	= r19

.def	t0	= r4
.def	t1	= r5
.def	t2	= r6
.def	t3	= r7
.def	t4	= r8
.def	t5	= r9
.def	t6	= r10
.def	t7	= r11
.def	cnt	= r28

;************************************************************************
;*									*
;*			unsigned division 64 bit			*
;*									*
;************************************************************************

; a3..0 = a3..0 / b3..0
; b3..0 = remainde

;cycle: max 684

udiv32:
	clr	t0
	clr	t1
	movw	t3:t2, t1:t0
	movw	t5:t4, t1:t0
	movw	t7:t6, t1:t0
	ldi	cnt, 64
udi1:	lsl	a0
	rol	a1
	rol	a2
	rol	a3
	rol	a4
	rol	a5
	rol	a6
	rol	a7
	rol	t0
	rol	t1
	rol	t2
	rol	t3
	rol	t4
	rol	t5
	rol	t6
	rol	t7
	cp	t0, b0
	cpc	t1, b1
	cpc	t2, b2
	cpc	t3, b3
	cpc	t4, b4
	cpc	t5, b5
	cpc	t6, b6
	cpc	t7, b7
	brcs	udi2
	sub	t0, b0
	sbc	t1, b1
	sbc	t2, b2
	sbc	t3, b3
	sbc	t4, b4
	sbc	t5, b5
	sbc	t6, b6
	sbc	t7, b7
	inc	a0
udi2:	dec	t4
	brne	udi1
	movw	b1:b0, t1:t0
	movw	b3:b2, t3:t2
	movw	b5:b4, t5:t4
	movw	b7:b6, t7:t6
	ret