; ############################################################################## ; ############################################################################## ; ############################################################################## BEISPIEL: ldi temp1,0x00 ; Divident 24.000.000.000.000 = 0x15D3EF798000 ldi temp2,0x80 ldi temp3,0x79 ldi temp4,0xEF ldi temp5,0xD3 ldi temp6,0x15 ldi temp7,0x00 ldi temp8,0x00 ldi temp,BYTE1(24000000) ; Divisor STS(adr_DIVISOR0),temp ldi temp,BYTE2(24000000) STS(adr_DIVISOR1),temp ldi temp,BYTE3(24000000) STS(adr_DIVISOR2),temp ldi temp,BYTE4(24000000) STS(adr_DIVISOR3),temp ldi temp,0x00 STS(adr_DIVISOR4),temp ldi temp,0x00 STS(adr_DIVISOR5),temp ldi temp,0x00 STS(adr_DIVISOR6),temp ldi temp,0x00 STS(adr_DIVISOR7),temp rcall DIVISION_64_64 ret ;############################################################################### ;############################################################################### ;############################################################################### ; Version: 04/2021 ; https://www.translatorscafe.com/unit-converter/de-DE/numbers/3-4/Dezimal-Hexadezimal/ ; ;.def temp = R16 ;.def temp1 = R17 ;.def temp2 = R18 ;.def temp3 = R19 ;.def temp4 = R20 ;.def temp5 = R21 ;.def temp6 = R22 ;.def temp7 = R23 ;.def temp8 = R24 ;.def temp9 = R25 ; ;.equ adr_ZWE0 =SRAM_START+300 Zwischenergebnis ;.equ adr_ZWE1 =SRAM_START+301 ;.equ adr_ZWE2 =SRAM_START+302 ;.equ adr_ZWE3 =SRAM_START+303 ;.equ adr_ZWE4 =SRAM_START+304 ;.equ adr_ZWE5 =SRAM_START+305 ;.equ adr_ZWE6 =SRAM_START+306 ;.equ adr_ZWE7 =SRAM_START+307 ; ;.equ adr_DIVISOR0 =SRAM_START+400 Divisor ;.equ adr_DIVISOR1 =SRAM_START+401 ;.equ adr_DIVISOR2 =SRAM_START+402 ;.equ adr_DIVISOR3 =SRAM_START+403 ;.equ adr_DIVISOR4 =SRAM_START+404 ;.equ adr_DIVISOR5 =SRAM_START+405 ;.equ adr_DIVISOR6 =SRAM_START+406 ;.equ adr_DIVISOR7 =SRAM_START+407 ; ; 8Bit 255 ;16Bit 65.536 ;24Bit 16.777.215 ;32Bit 4.294.967.295 ;40Bit 1.099.511.627.775 ;48Bit 281.474.976.710.655 ;56Bit 72.057.594.037.927.935 ;64Bit 18.446.744.073.709.551.615 ; ; INPUT: TEMP1...8 (0....18.446.744.073.709.551.615) Divident ; SRAM (1....18.446.744.073.709.551.615) Divisor ; SRAM adr_DIVISOR0...7 ; OUTPUT; TEMP1...8 (0....18.446.744.073.709.500.000) Quotient ; ; Hilfsregister: ; R0,R1,R2,R3,R4,R5,R6;R7,TEMP nicht gesichert ; SRAM adr_ZWE0...7 ; DIVISION_64_64: mov R0,EINS ; HILFSREGISTER =1 clr R1 clr R2 clr R3 clr R4 clr R5 clr R6 clr R7 clr temp STS(adr_ZWE0),temp ; Zwischenergebnis STS(adr_ZWE1),temp STS(adr_ZWE2),temp STS(adr_ZWE3),temp STS(adr_ZWE4),temp STS(adr_ZWE5),temp STS(adr_ZWE6),temp STS(adr_ZWE7),temp ;------------------------------------------------------------------------------- ; Divisor linksbündig DIVISION_LINKS: LDS temp,(adr_DIVISOR7) tst temp ; DIVIDENT Linksbündig ? brmi DIVISION_START ; ja ==> SPRUNG LSL R0 ; HILFSREGISTER 1x links ROL R1 ROL R2 ROL R3 ROL R4 ROL R5 ROL R6 ROL R7 LDS temp,(adr_DIVISOR0) ; DIVISOR 1x links LSL temp STS(adr_DIVISOR0),temp LDS temp,(adr_DIVISOR1) ROL temp STS(adr_DIVISOR1),temp LDS temp,(adr_DIVISOR2) ROL temp STS(adr_DIVISOR2),temp LDS temp,(adr_DIVISOR3) ROL temp STS(adr_DIVISOR3),temp LDS temp,(adr_DIVISOR4) ROL temp STS(adr_DIVISOR4),temp LDS temp,(adr_DIVISOR5) ROL temp STS(adr_DIVISOR5),temp LDS temp,(adr_DIVISOR6) ROL temp STS(adr_DIVISOR6),temp LDS temp,(adr_DIVISOR7) ROL temp STS(adr_DIVISOR7),temp rjmp DIVISION_LINKS ;------------------------------------------------------------------------------- ; DIVISION START DIVISION_START: LDS temp,(adr_DIVISOR7) cp temp8,temp ; DIVIDENT ">=" DIVISOR ? breq DIVISION_w1 brsh DIVISION_ADD_SUB rjmp DIVISION_SCHIEBEN DIVISION_w1: LDS temp,(adr_DIVISOR6) cp temp7,temp ; DIVIDENT ">=" DIVISOR ? breq DIVISION_w2 brsh DIVISION_ADD_SUB rjmp DIVISION_SCHIEBEN DIVISION_w2: LDS temp,(adr_DIVISOR5) cp temp6,temp ; DIVIDENT ">=" DIVISOR ? breq DIVISION_w3 brsh DIVISION_ADD_SUB rjmp DIVISION_SCHIEBEN DIVISION_w3: LDS temp,(adr_DIVISOR4) cp temp5,temp ; DIVIDENT ">=" DIVISOR ? breq DIVISION_w4 brsh DIVISION_ADD_SUB rjmp DIVISION_SCHIEBEN DIVISION_w4: LDS temp,(adr_DIVISOR3) cp temp4,temp ; DIVIDENT ">=" DIVISOR ? breq DIVISION_w5 brsh DIVISION_ADD_SUB rjmp DIVISION_SCHIEBEN DIVISION_w5: LDS temp,(adr_DIVISOR2) cp temp3,temp ; DIVIDENT ">=" DIVISOR ? breq DIVISION_w6 brsh DIVISION_ADD_SUB rjmp DIVISION_SCHIEBEN DIVISION_w6: LDS temp,(adr_DIVISOR1) cp temp2,temp ; DIVIDENT ">=" DIVISOR ? breq DIVISION_w7 brsh DIVISION_ADD_SUB rjmp DIVISION_SCHIEBEN DIVISION_w7: LDS temp,(adr_DIVISOR0) cp temp1,temp ; DIVIDENT ">=" DIVISOR ? breq DIVISION_ADD_SUB brsh DIVISION_ADD_SUB rjmp DIVISION_SCHIEBEN ;------------------------------------------------------------------------------- ; ADDIEREN und SUBTRAHIEREN DIVISION_ADD_SUB: LDS temp,(adr_ZWE0) ; Zwischenergebnis vergrößern add temp,R0 STS(adr_ZWE0),temp LDS temp,(adr_ZWE1) adc temp,R1 STS(adr_ZWE1),temp LDS temp,(adr_ZWE2) adc temp,R2 STS(adr_ZWE2),temp LDS temp,(adr_ZWE3) adc temp,R3 STS(adr_ZWE3),temp LDS temp,(adr_ZWE4) adc temp,R4 STS(adr_ZWE4),temp LDS temp,(adr_ZWE5) adc temp,R5 STS(adr_ZWE5),temp LDS temp,(adr_ZWE6) adc temp,R6 STS(adr_ZWE6),temp LDS temp,(adr_ZWE7) adc temp,R7 STS(adr_ZWE7),temp LDS temp,(adr_DIVISOR0) ; DIVIDENT verkleinern sub temp1,temp LDS temp,(adr_DIVISOR1) sbc temp2,temp LDS temp,(adr_DIVISOR2) sbc temp3,temp LDS temp,(adr_DIVISOR3) sbc temp4,temp LDS temp,(adr_DIVISOR4) sbc temp5,temp LDS temp,(adr_DIVISOR5) sbc temp6,temp LDS temp,(adr_DIVISOR6) sbc temp7,temp LDS temp,(adr_DIVISOR7) sbc temp8,temp ;------------------------------------------------------------------------------- DIVISION_SCHIEBEN: LDS temp,(adr_DIVISOR7) ; DIVISOR 1 x rechts LSR temp STS(adr_DIVISOR7),temp LDS temp,(adr_DIVISOR6) ROR temp STS(adr_DIVISOR6),temp LDS temp,(adr_DIVISOR5) ROR temp STS(adr_DIVISOR5),temp LDS temp,(adr_DIVISOR4) ROR temp STS(adr_DIVISOR4),temp LDS temp,(adr_DIVISOR3) ROR temp STS(adr_DIVISOR3),temp LDS temp,(adr_DIVISOR2) ROR temp STS(adr_DIVISOR2),temp LDS temp,(adr_DIVISOR1) ROR temp STS(adr_DIVISOR1),temp LDS temp,(adr_DIVISOR0) ROR temp STS(adr_DIVISOR0),temp LSR R7 ; HILFSREGISTER => 1 x rechts ROR R6 ROR R5 ROR R4 ROR R3 ROR R2 ROR R1 ROR R0 ; HILFSREGISTER=0 ? TST R7 ; =0 ? brne DIVISION_ST ; nein ==> SPRUNG TST R6 brne DIVISION_ST TST R5 brne DIVISION_ST TST R4 brne DIVISION_ST TST R3 brne DIVISION_ST TST R2 brne DIVISION_ST TST R1 brne DIVISION_ST TST R0 brne DIVISION_ST rjmp DIVISION_EXIT DIVISION_ST: rjmp DIVISION_START ;------------------------------------------------------------------------------- ; ERGEBNIS DIVISION_EXIT: LDS temp1,(adr_ZWE0) LDS temp2,(adr_ZWE1) LDS temp3,(adr_ZWE2) LDS temp4,(adr_ZWE3) LDS temp5,(adr_ZWE4) LDS temp6,(adr_ZWE5) LDS temp7,(adr_ZWE6) LDS temp8,(adr_ZWE7) ret ;############################################################################### ;############################################################################### ;###############################################################################