library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.ALL;

entity tb_lightLED is
end tb_lightLED;

architecture tb of tb_lightLED is

component lightLED is port(
	Button      : in std_logic;
	Switches    : in std_logic_vector(3 downto 0);
	Clk         : in std_logic;
	Rst         : in std_logic;
	LED         : out std_logic);
end component;

signal Clk      : std_logic:='1';
signal Switches : std_logic_vector(3 downto 0):="0000";
signal Button   : std_logic:='1';
signal Rst      : std_logic:='1';
signal LED      : std_logic:='0';

begin

Clk <= not Clk after 5 ns;

process begin
	Switches <= std_logic_vector(to_unsigned(13,4));
	wait for 100 ns;
	Button <= '0';
	wait for 10 ns;
	Button <= '1';
	wait for 200 ns;
	Button <= '0';
	wait for 10 ns;
	Button <= '1';
	wait for 100 ns;
	Button <= '0';
	wait for 10 ns;
	Button <= '1';
	wait for 200 ns;
	Button <= '0';
	wait for 10 ns;
	Button <= '1';
	wait for 80 ns;
	Rst <= '0';
	wait for 10 ns;
	Rst <= '1';
	wait;
end process;

UUT: lightLED port map(
	Button      => Button,
	Switches    => Switches,
	Clk         => Clk,
	Rst         => Rst,
	LED         => LED);

end;