library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity cart_to_polar_tb is
end entity cart_to_polar_tb;

architecture testbench of cart_to_polar_tb is

    constant order          : natural               := 4;

    constant clk_frequency  : natural               := 100000000;
    constant clk_period     : time                  := 1 sec / clk_frequency;

    signal simulation_run   : boolean               := true;

    signal tb_clk           : std_ulogic            := '1';
    --                      
    signal tb_en            : std_ulogic            := '0';
    signal tb_y            : signed(  7 downto 0)  := to_signed( 0, 8);
    signal tb_x            : signed(  7 downto 0)  := to_signed( 0, 8);
    --                      
    signal tb_sum           : unsigned(  7 downto 0);
    signal tb_phase         : signed(  8 downto 0);
    signal tb_result_en     : std_ulogic;


begin

    tb_clk  <= not tb_clk after clk_period / 2 when simulation_run;

    dut: entity work.cart_to_polar
    port map
    (
        clk         => tb_clk,        -- : in    std_ulogic;
        --
        in_enable   => tb_en,         -- : in    std_ulogic;
        y_in        => tb_y,         -- : in    signed(  7 downto 0);
        x_in        => tb_x,         -- : in    signed(  7 downto 0);
        --
        radius_out       => tb_sum,        -- : out   unsigned(  7 downto 0);
        angle_out   => tb_phase,      -- : out   signed(  8 downto 0);
        out_enable  => tb_result_en   -- : out   std_ulogic
    );

    main: process
        variable result_sum     : natural;
        variable result_phase   : integer;
        variable x              : integer   := 100;
        variable y              : integer   := 0;
    begin
        wait for 10 * clk_period;

        for fy in -order to order loop
            report "outer loop: " & integer'image( fy);
            for fx in -order to order loop
                x   := fx * 31;
                y   := fy * 31;

                wait until rising_edge( tb_clk);
                tb_y    <= to_signed( y, tb_y'length);
                tb_x    <= to_signed( x, tb_x'length);
                tb_en   <= '1';
                wait until rising_edge( tb_clk);
                tb_en   <= '0';

                wait until tb_result_en = '1';
                result_sum      := to_integer( tb_sum);
                result_phase    := to_integer( tb_phase);
                wait until rising_edge( tb_clk);

                report "x: " & integer'image( x) & ", y: " & integer'image( y) & " --> radius: " & integer'image( result_sum) & ", angle: " & integer'image( result_phase);
                wait for 5 * clk_period;
            end loop;
        end loop;


        simulation_run  <= false;
        report "ready. done.";
        wait; -- forever
    end process;

end architecture testbench;