library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity hysterese is port(
	Spannungslimit   : in  std_logic_vector(7 downto 0);
	HysVariable      : in  std_logic_vector(7 downto 0);
	ADC_WERT         : in  std_logic_vector(7 downto 0);
	Portpin          : out std_logic);
end hysterese;
 
architecture rtl of hysterese is

signal Speicher      : std_logic:='0';

begin

Portpin <= Speicher;

process (Spannungslimit, HysVariable, ADC_WERT) begin
	if unsigned(ADC_WERT) > unsigned(Spannungslimit) then
		Speicher <= '0';
	end if;
	
	if unsigned(HysVariable) <= unsigned(Spannungslimit) then
		if unsigned(ADC_WERT) < unsigned(Spannungslimit) - unsigned(HysVariable) then
			Speicher <= '1';
		end if;
	end if;
end process;

end;