C:\Users\Worker\AppData\Local\Temp\arduino_build_209462\PinTemplateVirtual.ino.elf: file format elf32-avr Disassembly of section .text: 00000000 <__vectors>: 0: 0c 94 51 00 jmp 0xa2 ; 0xa2 <__ctors_end> 4: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 8: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 10: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 14: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 18: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 1c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 20: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 24: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 28: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 2c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 30: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 34: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 38: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 3c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 40: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 44: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 48: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 4c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 50: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 54: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 58: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 5c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 60: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 64: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 68: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 6c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 70: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 74: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 78: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 7c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 80: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 84: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 88: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 8c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 90: 0c 94 de 00 jmp 0x1bc ; 0x1bc <__vector_36> 94: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 98: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 9c: 0c 94 79 00 jmp 0xf2 ; 0xf2 <__bad_interrupt> 000000a0 <__ctors_start>: a0: 40 01 movw r8, r0 000000a2 <__ctors_end>: a2: 11 24 eor r1, r1 a4: 1f be out 0x3f, r1 ; 63 a6: cf ef ldi r28, 0xFF ; 255 a8: cd bf out 0x3d, r28 ; 61 aa: df e3 ldi r29, 0x3F ; 63 ac: de bf out 0x3e, r29 ; 62 000000ae <__do_copy_data>: ae: 18 e2 ldi r17, 0x28 ; 40 b0: a0 e0 ldi r26, 0x00 ; 0 b2: b8 e2 ldi r27, 0x28 ; 40 b4: ea ed ldi r30, 0xDA ; 218 b6: f4 e0 ldi r31, 0x04 ; 4 b8: 02 c0 rjmp .+4 ; 0xbe <__do_copy_data+0x10> ba: 05 90 lpm r0, Z+ bc: 0d 92 st X+, r0 be: a8 30 cpi r26, 0x08 ; 8 c0: b1 07 cpc r27, r17 c2: d9 f7 brne .-10 ; 0xba <__do_copy_data+0xc> 000000c4 <__do_clear_bss>: c4: 28 e2 ldi r18, 0x28 ; 40 c6: a8 e0 ldi r26, 0x08 ; 8 c8: b8 e2 ldi r27, 0x28 ; 40 ca: 01 c0 rjmp .+2 ; 0xce <.do_clear_bss_start> 000000cc <.do_clear_bss_loop>: cc: 1d 92 st X+, r1 000000ce <.do_clear_bss_start>: ce: ae 31 cpi r26, 0x1E ; 30 d0: b2 07 cpc r27, r18 d2: e1 f7 brne .-8 ; 0xcc <.do_clear_bss_loop> 000000d4 <__do_global_ctors>: d4: 10 e0 ldi r17, 0x00 ; 0 d6: c1 e5 ldi r28, 0x51 ; 81 d8: d0 e0 ldi r29, 0x00 ; 0 da: 04 c0 rjmp .+8 ; 0xe4 <__do_global_ctors+0x10> dc: 21 97 sbiw r28, 0x01 ; 1 de: fe 01 movw r30, r28 e0: 0e 94 33 02 call 0x466 ; 0x466 <__tablejump2__> e4: c0 35 cpi r28, 0x50 ; 80 e6: d1 07 cpc r29, r17 e8: c9 f7 brne .-14 ; 0xdc <__do_global_ctors+0x8> ea: 0e 94 4d 01 call 0x29a ; 0x29a
ee: 0c 94 39 02 jmp 0x472 ; 0x472 <_exit> 000000f2 <__bad_interrupt>: f2: 0c 94 00 00 jmp 0 ; 0x0 <__vectors> 000000f6 <_ZN9OutputPinILh13EE4initEv>: extern "C" void __cxa_deleted_virtual(void) __attribute__ ((__noreturn__)); void __cxa_pure_virtual(void) { // We might want to write some diagnostics to uart in this case //std::terminate(); abort(); f6: 82 9a sbi 0x10, 2 ; 16 f8: 08 95 ret 000000fa <_ZN3PinILh13EE5setOnEv>: fa: 8a 9a sbi 0x11, 2 ; 17 fc: 08 95 ret 000000fe <_ZN3PinILh13EE6setOffEv>: fe: 8a 98 cbi 0x11, 2 ; 17 100: 08 95 ret 00000102 <_ZN3PinILh13EE6toggleEv>: 102: 84 e0 ldi r24, 0x04 ; 4 104: 82 bb out 0x12, r24 ; 18 106: 08 95 ret 00000108 <_ZNK3PinILh13EE4isOnEv>: 108: 82 b3 in r24, 0x12 ; 18 10a: 82 fb bst r24, 2 10c: 88 27 eor r24, r24 10e: 80 f9 bld r24, 0 110: 08 95 ret 00000112 <_ZN3PinILh13EE14enableSlewRateEv>: 112: ea e8 ldi r30, 0x8A ; 138 114: f4 e0 ldi r31, 0x04 ; 4 116: 80 81 ld r24, Z 118: 81 60 ori r24, 0x01 ; 1 11a: 80 83 st Z, r24 11c: 08 95 ret 0000011e <_ZN3PinILh13EE15disableSlewRateEv>: 11e: ea e8 ldi r30, 0x8A ; 138 120: f4 e0 ldi r31, 0x04 ; 4 122: 80 81 ld r24, Z 124: 8e 7f andi r24, 0xFE ; 254 126: 80 83 st Z, r24 128: 08 95 ret 0000012a <_ZN3PinILh13EE14enableInvertIOEv>: 12a: e2 e9 ldi r30, 0x92 ; 146 12c: f4 e0 ldi r31, 0x04 ; 4 12e: 80 81 ld r24, Z 130: 80 68 ori r24, 0x80 ; 128 132: 80 83 st Z, r24 134: 08 95 ret 00000136 <_ZN3PinILh13EE15disableInvertIOEv>: 136: e2 e9 ldi r30, 0x92 ; 146 138: f4 e0 ldi r31, 0x04 ; 4 13a: 80 81 ld r24, Z 13c: 8f 77 andi r24, 0x7F ; 127 13e: 80 83 st Z, r24 140: 08 95 ret 00000142 <_ZN3PinILh13EE12enablePullupEv>: 142: e2 e9 ldi r30, 0x92 ; 146 144: f4 e0 ldi r31, 0x04 ; 4 146: 80 81 ld r24, Z 148: 88 60 ori r24, 0x08 ; 8 14a: 80 83 st Z, r24 14c: 08 95 ret 0000014e <_ZN3PinILh13EE13disablePullupEv>: 14e: e2 e9 ldi r30, 0x92 ; 146 150: f4 e0 ldi r31, 0x04 ; 4 152: 80 81 ld r24, Z 154: 87 7f andi r24, 0xF7 ; 247 156: 80 83 st Z, r24 158: 08 95 ret 0000015a <_ZN9OutputPinILh12EE4initEv>: 15a: 81 9a sbi 0x10, 1 ; 16 15c: 08 95 ret 0000015e <_ZN3PinILh12EE5setOnEv>: 15e: 89 9a sbi 0x11, 1 ; 17 160: 08 95 ret 00000162 <_ZN3PinILh12EE6setOffEv>: 162: 89 98 cbi 0x11, 1 ; 17 164: 08 95 ret 00000166 <_ZN3PinILh12EE6toggleEv>: 166: 82 e0 ldi r24, 0x02 ; 2 168: 82 bb out 0x12, r24 ; 18 16a: 08 95 ret 0000016c <_ZNK3PinILh12EE4isOnEv>: 16c: 82 b3 in r24, 0x12 ; 18 16e: 86 95 lsr r24 170: 81 70 andi r24, 0x01 ; 1 172: 08 95 ret 00000174 <_ZN3PinILh12EE14enableSlewRateEv>: 174: ea e8 ldi r30, 0x8A ; 138 176: f4 e0 ldi r31, 0x04 ; 4 178: 80 81 ld r24, Z 17a: 81 60 ori r24, 0x01 ; 1 17c: 80 83 st Z, r24 17e: 08 95 ret 00000180 <_ZN3PinILh12EE15disableSlewRateEv>: 180: ea e8 ldi r30, 0x8A ; 138 182: f4 e0 ldi r31, 0x04 ; 4 184: 80 81 ld r24, Z 186: 8e 7f andi r24, 0xFE ; 254 188: 80 83 st Z, r24 18a: 08 95 ret 0000018c <_ZN3PinILh12EE14enableInvertIOEv>: 18c: e1 e9 ldi r30, 0x91 ; 145 18e: f4 e0 ldi r31, 0x04 ; 4 190: 80 81 ld r24, Z 192: 80 68 ori r24, 0x80 ; 128 194: 80 83 st Z, r24 196: 08 95 ret 00000198 <_ZN3PinILh12EE15disableInvertIOEv>: 198: e1 e9 ldi r30, 0x91 ; 145 19a: f4 e0 ldi r31, 0x04 ; 4 19c: 80 81 ld r24, Z 19e: 8f 77 andi r24, 0x7F ; 127 1a0: 80 83 st Z, r24 1a2: 08 95 ret 000001a4 <_ZN3PinILh12EE12enablePullupEv>: 1a4: e1 e9 ldi r30, 0x91 ; 145 1a6: f4 e0 ldi r31, 0x04 ; 4 1a8: 80 81 ld r24, Z 1aa: 88 60 ori r24, 0x08 ; 8 1ac: 80 83 st Z, r24 1ae: 08 95 ret 000001b0 <_ZN3PinILh12EE13disablePullupEv>: 1b0: e1 e9 ldi r30, 0x91 ; 145 1b2: f4 e0 ldi r31, 0x04 ; 4 1b4: 80 81 ld r24, Z 1b6: 87 7f andi r24, 0xF7 ; 247 1b8: 80 83 st Z, r24 1ba: 08 95 ret 000001bc <__vector_36>: 1bc: 1f 92 push r1 1be: 1f b6 in r1, 0x3f ; 63 1c0: 1f 92 push r1 1c2: 11 24 eor r1, r1 1c4: 2f 93 push r18 1c6: 3f 93 push r19 1c8: 4f 93 push r20 1ca: 5f 93 push r21 1cc: 6f 93 push r22 1ce: 7f 93 push r23 1d0: 8f 93 push r24 1d2: 9f 93 push r25 1d4: af 93 push r26 1d6: bf 93 push r27 1d8: 40 91 0e 28 lds r20, 0x280E 1dc: 50 91 0f 28 lds r21, 0x280F 1e0: 60 91 10 28 lds r22, 0x2810 1e4: 70 91 11 28 lds r23, 0x2811 1e8: 80 91 0c 28 lds r24, 0x280C 1ec: 90 91 0d 28 lds r25, 0x280D 1f0: 20 91 14 28 lds r18, 0x2814 1f4: 30 91 15 28 lds r19, 0x2815 1f8: 42 0f add r20, r18 1fa: 53 1f adc r21, r19 1fc: 61 1d adc r22, r1 1fe: 71 1d adc r23, r1 200: 20 91 12 28 lds r18, 0x2812 204: 30 91 13 28 lds r19, 0x2813 208: 82 0f add r24, r18 20a: 93 1f adc r25, r19 20c: 88 3e cpi r24, 0xE8 ; 232 20e: 23 e0 ldi r18, 0x03 ; 3 210: 92 07 cpc r25, r18 212: 30 f0 brcs .+12 ; 0x220 <__vector_36+0x64> 214: 88 5e subi r24, 0xE8 ; 232 216: 93 40 sbci r25, 0x03 ; 3 218: 4f 5f subi r20, 0xFF ; 255 21a: 5f 4f sbci r21, 0xFF ; 255 21c: 6f 4f sbci r22, 0xFF ; 255 21e: 7f 4f sbci r23, 0xFF ; 255 220: 80 93 0c 28 sts 0x280C, r24 224: 90 93 0d 28 sts 0x280D, r25 228: 40 93 0e 28 sts 0x280E, r20 22c: 50 93 0f 28 sts 0x280F, r21 230: 60 93 10 28 sts 0x2810, r22 234: 70 93 11 28 sts 0x2811, r23 238: 80 91 08 28 lds r24, 0x2808 23c: 90 91 09 28 lds r25, 0x2809 240: a0 91 0a 28 lds r26, 0x280A 244: b0 91 0b 28 lds r27, 0x280B 248: 01 96 adiw r24, 0x01 ; 1 24a: a1 1d adc r26, r1 24c: b1 1d adc r27, r1 24e: 80 93 08 28 sts 0x2808, r24 252: 90 93 09 28 sts 0x2809, r25 256: a0 93 0a 28 sts 0x280A, r26 25a: b0 93 0b 28 sts 0x280B, r27 25e: 81 e0 ldi r24, 0x01 ; 1 260: 80 93 b6 0a sts 0x0AB6, r24 264: bf 91 pop r27 266: af 91 pop r26 268: 9f 91 pop r25 26a: 8f 91 pop r24 26c: 7f 91 pop r23 26e: 6f 91 pop r22 270: 5f 91 pop r21 272: 4f 91 pop r20 274: 3f 91 pop r19 276: 2f 91 pop r18 278: 1f 90 pop r1 27a: 1f be out 0x3f, r1 ; 63 27c: 1f 90 pop r1 27e: 18 95 reti 00000280 <_GLOBAL__sub_I_led12>: Pin::deleteFlag(); } }; template class OutputPin : protected Pin , public virtual Interface 280: 84 ec ldi r24, 0xC4 ; 196 282: 94 e4 ldi r25, 0x44 ; 68 284: 80 93 1c 28 sts 0x281C, r24 288: 90 93 1d 28 sts 0x281D, r25 28c: 82 e9 ldi r24, 0x92 ; 146 28e: 94 e4 ldi r25, 0x44 ; 68 290: 80 93 1a 28 sts 0x281A, r24 294: 90 93 1b 28 sts 0x281B, r25 298: 08 95 ret 0000029a
: #elif (F_CPU == 16000000) cpu_freq = 16000000; /* No division on clock */ _PROTECTED_WRITE(CLKCTRL_MCLKCTRLB, 0x00); 29a: 88 ed ldi r24, 0xD8 ; 216 29c: 90 e0 ldi r25, 0x00 ; 0 29e: 84 bf out 0x34, r24 ; 52 2a0: 90 93 61 00 sts 0x0061, r25 /* No division on clock */ _PROTECTED_WRITE(CLKCTRL_MCLKCTRLB, 0x00); #endif /* Apply calculated value to F_CPU_CORRECTED */ F_CPU_CORRECTED = (uint32_t)cpu_freq; 2a4: 80 e0 ldi r24, 0x00 ; 0 2a6: 94 e2 ldi r25, 0x24 ; 36 2a8: a4 ef ldi r26, 0xF4 ; 244 2aa: b0 e0 ldi r27, 0x00 ; 0 2ac: 80 93 00 28 sts 0x2800, r24 2b0: 90 93 01 28 sts 0x2801, r25 2b4: a0 93 02 28 sts 0x2802, r26 2b8: b0 93 03 28 sts 0x2803, r27 /* ADC clock between 50-200 kHz */ #if F_CPU >= 20000000 // 20 MHz / 128 = 156.250 kHz ADC0.CTRLC |= ADC_PRESC_DIV128_gc; #elif F_CPU >= 16000000 // 16 MHz / 128 = 125 kHz ADC0.CTRLC |= ADC_PRESC_DIV128_gc; 2bc: 80 91 02 06 lds r24, 0x0602 2c0: 86 60 ori r24, 0x06 ; 6 2c2: 80 93 02 06 sts 0x0602, r24 #else // 128 kHz / 2 = 64 kHz -> This is the closest you can get, the prescaler is 2 ADC0.CTRLC |= ADC_PRESC_DIV2_gc; #endif /* Enable ADC */ ADC0.CTRLA |= ADC_ENABLE_bm; 2c6: 80 91 00 06 lds r24, 0x0600 2ca: 81 60 ori r24, 0x01 ; 1 2cc: 80 93 00 06 sts 0x0600, r24 uint8_t analog_reference = DEFAULT; void analogReference(uint8_t mode) { /* Clear relevant settings */ ADC0.CTRLC &= ~(ADC_REFSEL_gm); 2d0: 80 91 02 06 lds r24, 0x0602 2d4: 8f 7c andi r24, 0xCF ; 207 2d6: 80 93 02 06 sts 0x0602, r24 VREF.CTRLA &= ~(VREF_ADC0REFSEL_gm); 2da: 80 91 a0 00 lds r24, 0x00A0 2de: 8f 78 andi r24, 0x8F ; 143 2e0: 80 93 a0 00 sts 0x00A0, r24 /* If reference NOT using internal reference from VREF */ if((mode == EXTERNAL) || (mode == VDD)) { /* Set reference in ADC peripheral */ ADC0.CTRLC |= mode; 2e4: 80 91 02 06 lds r24, 0x0602 2e8: 80 61 ori r24, 0x10 ; 16 2ea: 80 93 02 06 sts 0x0602, r24 analogReference(VDD); #endif PORTMUX.USARTROUTEA = 0; 2ee: 10 92 e2 05 sts 0x05E2, r1 void setup_timers() { // TYPE A TIMER // PORTMUX setting for TCA -> all outputs [0:2] point to PORTB pins [0:2] PORTMUX.TCAROUTEA = PORTMUX_TCA0_PORTB_gc; 2f2: 81 e0 ldi r24, 0x01 ; 1 2f4: 80 93 e4 05 sts 0x05E4, r24 // Setup timers for single slope PWM, but do not enable, will do in analogWrite() TCA0.SINGLE.CTRLB = TCA_SINGLE_WGMODE_SINGLESLOPE_gc; 2f8: 83 e0 ldi r24, 0x03 ; 3 2fa: 80 93 01 0a sts 0x0A01, r24 // Period setting, 16 bit register but val resolution is 8 bit TCA0.SINGLE.PER = PWM_TIMER_PERIOD; 2fe: 8f ef ldi r24, 0xFF ; 255 300: 90 e0 ldi r25, 0x00 ; 0 302: 80 93 26 0a sts 0x0A26, r24 306: 90 93 27 0a sts 0x0A27, r25 // Default duty 50%, will re-assign in analogWrite() TCA0.SINGLE.CMP0BUF = PWM_TIMER_COMPARE; 30a: 80 e8 ldi r24, 0x80 ; 128 30c: 90 e0 ldi r25, 0x00 ; 0 30e: 80 93 38 0a sts 0x0A38, r24 312: 90 93 39 0a sts 0x0A39, r25 TCA0.SINGLE.CMP1BUF = PWM_TIMER_COMPARE; 316: 80 93 3a 0a sts 0x0A3A, r24 31a: 90 93 3b 0a sts 0x0A3B, r25 TCA0.SINGLE.CMP2BUF = PWM_TIMER_COMPARE; 31e: 80 93 3c 0a sts 0x0A3C, r24 322: 90 93 3d 0a sts 0x0A3D, r25 // Use DIV64 prescaler (giving 250kHz clock), enable TCA timer TCA0.SINGLE.CTRLA = (TCA_SINGLE_CLKSEL_DIV64_gc) | (TCA_SINGLE_ENABLE_bm); 326: 8b e0 ldi r24, 0x0B ; 11 328: 80 93 00 0a sts 0x0A00, r24 // TYPE B TIMERS // Setup TCB0 routing #if defined(TCB0) PORTMUX.TCBROUTEA |= PORTMUX_TCB0_bm; // Route signal to PF4 32c: 80 91 e5 05 lds r24, 0x05E5 330: 81 60 ori r24, 0x01 ; 1 332: 80 93 e5 05 sts 0x05E5, r24 #endif // Setup TCB1 routing #if defined(TCB1) PORTMUX.TCBROUTEA |= PORTMUX_TCB1_bm; // Route signal to PF5 336: 80 91 e5 05 lds r24, 0x05E5 33a: 82 60 ori r24, 0x02 ; 2 33c: 80 93 e5 05 sts 0x05E5, r24 #endif // Start with TCB0 TCB_t *timer_B = (TCB_t *)&TCB0; 340: e0 e8 ldi r30, 0x80 ; 128 342: fa e0 ldi r31, 0x0A ; 10 // Timer B Setup loop for TCB[0:3] do { // 8 bit PWM mode, but do not enable output yet, will do in analogWrite() timer_B->CTRLB = (TCB_CNTMODE_PWM8_gc); 344: 37 e0 ldi r19, 0x07 ; 7 // Assign 8-bit period timer_B->CCMPL = PWM_TIMER_PERIOD; 346: 2f ef ldi r18, 0xFF ; 255 // default duty 50%, set when output enabled timer_B->CCMPH = PWM_TIMER_COMPARE; 348: 90 e8 ldi r25, 0x80 ; 128 // Use TCA clock (250kHz) and enable // (sync update commented out, might try to synchronize later timer_B->CTRLA = (TCB_CLKSEL_CLKTCA_gc) 34a: 85 e0 ldi r24, 0x05 ; 5 // Timer B Setup loop for TCB[0:3] do { // 8 bit PWM mode, but do not enable output yet, will do in analogWrite() timer_B->CTRLB = (TCB_CNTMODE_PWM8_gc); 34c: 31 83 std Z+1, r19 ; 0x01 // Assign 8-bit period timer_B->CCMPL = PWM_TIMER_PERIOD; 34e: 24 87 std Z+12, r18 ; 0x0c // default duty 50%, set when output enabled timer_B->CCMPH = PWM_TIMER_COMPARE; 350: 95 87 std Z+13, r25 ; 0x0d // Use TCA clock (250kHz) and enable // (sync update commented out, might try to synchronize later timer_B->CTRLA = (TCB_CLKSEL_CLKTCA_gc) 352: 80 83 st Z, r24 //|(TCB_SYNCUPD_bm) |(TCB_ENABLE_bm); // Increment pointer to next TCB instance timer_B++; 354: 70 96 adiw r30, 0x10 ; 16 // Stop when pointing to TCB3 } while (timer_B <= timer_B_end); 356: e0 3c cpi r30, 0xC0 ; 192 358: 4a e0 ldi r20, 0x0A ; 10 35a: f4 07 cpc r31, r20 35c: b9 f7 brne .-18 ; 0x34c setup_timers(); /********************* TIMER for system time tracking **************************/ /* Calculate relevant time tracking values */ microseconds_per_timer_overflow = clockCyclesToMicroseconds(TIME_TRACKING_CYCLES_PER_OVF); 35e: 80 e0 ldi r24, 0x00 ; 0 360: 94 e0 ldi r25, 0x04 ; 4 362: 80 93 18 28 sts 0x2818, r24 366: 90 93 19 28 sts 0x2819, r25 microseconds_per_timer_tick = microseconds_per_timer_overflow/TIME_TRACKING_TIMER_PERIOD; 36a: 80 91 18 28 lds r24, 0x2818 36e: 90 91 19 28 lds r25, 0x2819 372: 2f ef ldi r18, 0xFF ; 255 374: 30 e0 ldi r19, 0x00 ; 0 376: b9 01 movw r22, r18 378: 0e 94 1f 02 call 0x43e ; 0x43e <__udivmodhi4> 37c: 60 93 16 28 sts 0x2816, r22 380: 70 93 17 28 sts 0x2817, r23 millis_inc = microseconds_per_timer_overflow / 1000; 384: 80 91 18 28 lds r24, 0x2818 388: 90 91 19 28 lds r25, 0x2819 38c: e8 ee ldi r30, 0xE8 ; 232 38e: f3 e0 ldi r31, 0x03 ; 3 390: bf 01 movw r22, r30 392: 0e 94 1f 02 call 0x43e ; 0x43e <__udivmodhi4> 396: 60 93 14 28 sts 0x2814, r22 39a: 70 93 15 28 sts 0x2815, r23 fract_inc = ((microseconds_per_timer_overflow % 1000)); 39e: 80 91 18 28 lds r24, 0x2818 3a2: 90 91 19 28 lds r25, 0x2819 3a6: bf 01 movw r22, r30 3a8: 0e 94 1f 02 call 0x43e ; 0x43e <__udivmodhi4> 3ac: 80 93 12 28 sts 0x2812, r24 3b0: 90 93 13 28 sts 0x2813, r25 /* Default Periodic Interrupt Mode */ /* TOP value for overflow every 1024 clock cycles */ _timer->CCMP = TIME_TRACKING_TIMER_PERIOD; 3b4: 20 93 bc 0a sts 0x0ABC, r18 3b8: 30 93 bd 0a sts 0x0ABD, r19 /* Enable timer interrupt */ _timer->INTCTRL |= TCB_CAPT_bm; 3bc: 80 91 b5 0a lds r24, 0x0AB5 3c0: 81 60 ori r24, 0x01 ; 1 3c2: 80 93 b5 0a sts 0x0AB5, r24 /* Clock selection -> same as TCA (F_CPU/64 -- 250kHz) */ _timer->CTRLA = TCB_CLKSEL_CLKTCA_gc; 3c6: 84 e0 ldi r24, 0x04 ; 4 3c8: 80 93 b0 0a sts 0x0AB0, r24 /* Enable & start */ _timer->CTRLA |= TCB_ENABLE_bm; /* Keep this last before enabling interrupts to ensure tracking as accurate as possible */ 3cc: 80 91 b0 0a lds r24, 0x0AB0 3d0: 81 60 ori r24, 0x01 ; 1 3d2: 80 93 b0 0a sts 0x0AB0, r24 /*************************** ENABLE GLOBAL INTERRUPTS *************************/ sei(); 3d6: 78 94 sei 3d8: 80 91 04 28 lds r24, 0x2804 3dc: 90 91 05 28 lds r25, 0x2805 3e0: dc 01 movw r26, r24 3e2: ed 91 ld r30, X+ 3e4: fc 91 ld r31, X 3e6: 01 90 ld r0, Z+ 3e8: f0 81 ld r31, Z 3ea: e0 2d mov r30, r0 3ec: 09 95 icall 3ee: 80 91 06 28 lds r24, 0x2806 3f2: 90 91 07 28 lds r25, 0x2807 3f6: dc 01 movw r26, r24 3f8: ed 91 ld r30, X+ 3fa: fc 91 ld r31, X 3fc: 01 90 ld r0, Z+ 3fe: f0 81 ld r31, Z 400: e0 2d mov r30, r0 402: 09 95 icall setup(); for (;;) { loop(); if (serialEventRun) serialEventRun(); 404: c0 e0 ldi r28, 0x00 ; 0 406: d0 e0 ldi r29, 0x00 ; 0 408: 80 91 04 28 lds r24, 0x2804 40c: 90 91 05 28 lds r25, 0x2805 410: dc 01 movw r26, r24 412: ed 91 ld r30, X+ 414: fc 91 ld r31, X 416: 06 80 ldd r0, Z+6 ; 0x06 418: f7 81 ldd r31, Z+7 ; 0x07 41a: e0 2d mov r30, r0 41c: 09 95 icall 41e: 80 91 06 28 lds r24, 0x2806 422: 90 91 07 28 lds r25, 0x2807 426: dc 01 movw r26, r24 428: ed 91 ld r30, X+ 42a: fc 91 ld r31, X 42c: 06 80 ldd r0, Z+6 ; 0x06 42e: f7 81 ldd r31, Z+7 ; 0x07 430: e0 2d mov r30, r0 432: 09 95 icall 434: 20 97 sbiw r28, 0x00 ; 0 436: 41 f3 breq .-48 ; 0x408 <__LOCK_REGION_LENGTH__+0x8> 438: 0e 94 00 00 call 0 ; 0x0 <__vectors> 43c: e5 cf rjmp .-54 ; 0x408 <__LOCK_REGION_LENGTH__+0x8> 0000043e <__udivmodhi4>: 43e: aa 1b sub r26, r26 440: bb 1b sub r27, r27 442: 51 e1 ldi r21, 0x11 ; 17 444: 07 c0 rjmp .+14 ; 0x454 <__udivmodhi4_ep> 00000446 <__udivmodhi4_loop>: 446: aa 1f adc r26, r26 448: bb 1f adc r27, r27 44a: a6 17 cp r26, r22 44c: b7 07 cpc r27, r23 44e: 10 f0 brcs .+4 ; 0x454 <__udivmodhi4_ep> 450: a6 1b sub r26, r22 452: b7 0b sbc r27, r23 00000454 <__udivmodhi4_ep>: 454: 88 1f adc r24, r24 456: 99 1f adc r25, r25 458: 5a 95 dec r21 45a: a9 f7 brne .-22 ; 0x446 <__udivmodhi4_loop> 45c: 80 95 com r24 45e: 90 95 com r25 460: bc 01 movw r22, r24 462: cd 01 movw r24, r26 464: 08 95 ret 00000466 <__tablejump2__>: 466: ee 0f add r30, r30 468: ff 1f adc r31, r31 46a: 05 90 lpm r0, Z+ 46c: f4 91 lpm r31, Z 46e: e0 2d mov r30, r0 470: 09 94 ijmp 00000472 <_exit>: 472: f8 94 cli 00000474 <__stop_program>: 474: ff cf rjmp .-2 ; 0x474 <__stop_program>