C:\Users\Worker\AppData\Local\Temp\arduino_build_9702\PinKlasse_klassisch_toggle_Forum.ino.elf:     file format elf32-avr


Disassembly of section .text:

00000000 <__vectors>:
   0:	0c 94 51 00 	jmp	0xa2	; 0xa2 <__ctors_end>
   4:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
   8:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
   c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  10:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  14:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  18:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  1c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  20:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  24:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  28:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  2c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  30:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  34:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  38:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  3c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  40:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  44:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  48:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  4c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  50:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  54:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  58:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  5c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  60:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  64:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  68:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  6c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  70:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  74:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  78:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  7c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  80:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  84:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  88:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  8c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  90:	0c 94 89 00 	jmp	0x112	; 0x112 <__vector_36>
  94:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  98:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>
  9c:	0c 94 79 00 	jmp	0xf2	; 0xf2 <__bad_interrupt>

000000a0 <__ctors_start>:
  a0:	eb 00       	.word	0x00eb	; ????

000000a2 <__ctors_end>:
  a2:	11 24       	eor	r1, r1
  a4:	1f be       	out	0x3f, r1	; 63
  a6:	cf ef       	ldi	r28, 0xFF	; 255
  a8:	cd bf       	out	0x3d, r28	; 61
  aa:	df e3       	ldi	r29, 0x3F	; 63
  ac:	de bf       	out	0x3e, r29	; 62

000000ae <__do_copy_data>:
  ae:	18 e2       	ldi	r17, 0x28	; 40
  b0:	a0 e0       	ldi	r26, 0x00	; 0
  b2:	b8 e2       	ldi	r27, 0x28	; 40
  b4:	e6 e2       	ldi	r30, 0x26	; 38
  b6:	f4 e0       	ldi	r31, 0x04	; 4
  b8:	02 c0       	rjmp	.+4      	; 0xbe <__do_copy_data+0x10>
  ba:	05 90       	lpm	r0, Z+
  bc:	0d 92       	st	X+, r0
  be:	a4 30       	cpi	r26, 0x04	; 4
  c0:	b1 07       	cpc	r27, r17
  c2:	d9 f7       	brne	.-10     	; 0xba <__do_copy_data+0xc>

000000c4 <__do_clear_bss>:
  c4:	28 e2       	ldi	r18, 0x28	; 40
  c6:	a4 e0       	ldi	r26, 0x04	; 4
  c8:	b8 e2       	ldi	r27, 0x28	; 40
  ca:	01 c0       	rjmp	.+2      	; 0xce <.do_clear_bss_start>

000000cc <.do_clear_bss_loop>:
  cc:	1d 92       	st	X+, r1

000000ce <.do_clear_bss_start>:
  ce:	a7 31       	cpi	r26, 0x17	; 23
  d0:	b2 07       	cpc	r27, r18
  d2:	e1 f7       	brne	.-8      	; 0xcc <.do_clear_bss_loop>

000000d4 <__do_global_ctors>:
  d4:	10 e0       	ldi	r17, 0x00	; 0
  d6:	c1 e5       	ldi	r28, 0x51	; 81
  d8:	d0 e0       	ldi	r29, 0x00	; 0
  da:	04 c0       	rjmp	.+8      	; 0xe4 <__do_global_ctors+0x10>
  dc:	21 97       	sbiw	r28, 0x01	; 1
  de:	fe 01       	movw	r30, r28
  e0:	0e 94 c3 01 	call	0x386	; 0x386 <__tablejump2__>
  e4:	c0 35       	cpi	r28, 0x50	; 80
  e6:	d1 07       	cpc	r29, r17
  e8:	c9 f7       	brne	.-14     	; 0xdc <__do_global_ctors+0x8>
  ea:	0e 94 ef 00 	call	0x1de	; 0x1de <main>
  ee:	0c 94 c9 01 	jmp	0x392	; 0x392 <_exit>

000000f2 <__bad_interrupt>:
  f2:	0c 94 00 00 	jmp	0	; 0x0 <__vectors>

000000f6 <_ZN7OutputP6toggleEv.constprop.0>:

// Invert, Input-Level, Pullup, Interrupt
constexpr Register8 regPinCtrl(const uint8_t pin)       { using namespace Pins::Addr; return (Register8) (baseAddr[pin].port + baseAddr[pin].pinCtrl); }
*/  
// Pin Bitmaske
constexpr uint8_t getMask(const uint8_t pin)            { using namespace Pins::Addr; return (baseAddr[pin].mask); } 
  f6:	e0 91 16 28 	lds	r30, 0x2816
  fa:	86 e0       	ldi	r24, 0x06	; 6
  fc:	e8 9f       	mul	r30, r24
  fe:	f0 01       	movw	r30, r0
 100:	11 24       	eor	r1, r1
 102:	ea 56       	subi	r30, 0x6A	; 106
 104:	fc 4b       	sbci	r31, 0xBC	; 188
 106:	85 81       	ldd	r24, Z+5	; 0x05
  
// Output Level
//constexpr Register8 regVPORTout(const uint8_t pin)      { using namespace Pins::Addr; return (Register8) (baseAddr[pin].vport + addrOffset.vOut); }

// Input Level Status
constexpr Register8 regVPORTin(const uint8_t pin)       { using namespace Pins::Addr; return (Register8) (baseAddr[pin].vport + addrOffset.vIn); }
 108:	01 90       	ld	r0, Z+
 10a:	f0 81       	ld	r31, Z
 10c:	e0 2d       	mov	r30, r0
  
// Outputs
void OutputP::init() { *regVPORTdir(pin) = *regVPORTdir(pin) | getMask(pin); }
//void OutputP::setOn()      { *regVPORTout(pin) = *regVPORTout(pin) | getMask(pin); }
//void OutputP::setOff()     { *regVPORTout(pin) = *regVPORTout(pin) & ~getMask(pin); }
void OutputP::toggle() { *regVPORTin(pin)  = getMask(pin); }
 10e:	82 83       	std	Z+2, r24	; 0x02
 110:	08 95       	ret

00000112 <__vector_36>:
ISR(TCB3_INT_vect)
#else
// fallback to TCB0 (every platform has it)
ISR(TCB0_INT_vect)
#endif
{
 112:	1f 92       	push	r1
 114:	1f b6       	in	r1, 0x3f	; 63
 116:	1f 92       	push	r1
 118:	11 24       	eor	r1, r1
 11a:	2f 93       	push	r18
 11c:	3f 93       	push	r19
 11e:	4f 93       	push	r20
 120:	5f 93       	push	r21
 122:	6f 93       	push	r22
 124:	7f 93       	push	r23
 126:	8f 93       	push	r24
 128:	9f 93       	push	r25
 12a:	af 93       	push	r26
 12c:	bf 93       	push	r27
	// copy these to local variables so they can be stored in registers
	// (volatile variables must be read from memory on every access)
	uint32_t m = timer_millis;
 12e:	40 91 0a 28 	lds	r20, 0x280A
 132:	50 91 0b 28 	lds	r21, 0x280B
 136:	60 91 0c 28 	lds	r22, 0x280C
 13a:	70 91 0d 28 	lds	r23, 0x280D
	uint16_t f = timer_fract;
 13e:	80 91 08 28 	lds	r24, 0x2808
 142:	90 91 09 28 	lds	r25, 0x2809

	m += millis_inc;
 146:	20 91 10 28 	lds	r18, 0x2810
 14a:	30 91 11 28 	lds	r19, 0x2811
 14e:	42 0f       	add	r20, r18
 150:	53 1f       	adc	r21, r19
 152:	61 1d       	adc	r22, r1
 154:	71 1d       	adc	r23, r1
	f += fract_inc;
 156:	20 91 0e 28 	lds	r18, 0x280E
 15a:	30 91 0f 28 	lds	r19, 0x280F
 15e:	82 0f       	add	r24, r18
 160:	93 1f       	adc	r25, r19
	if (f >= FRACT_MAX) {
 162:	88 3e       	cpi	r24, 0xE8	; 232
 164:	23 e0       	ldi	r18, 0x03	; 3
 166:	92 07       	cpc	r25, r18
 168:	30 f0       	brcs	.+12     	; 0x176 <__vector_36+0x64>

		f -= FRACT_MAX;
 16a:	88 5e       	subi	r24, 0xE8	; 232
 16c:	93 40       	sbci	r25, 0x03	; 3
		m += 1;
 16e:	4f 5f       	subi	r20, 0xFF	; 255
 170:	5f 4f       	sbci	r21, 0xFF	; 255
 172:	6f 4f       	sbci	r22, 0xFF	; 255
 174:	7f 4f       	sbci	r23, 0xFF	; 255
	}

	timer_fract = f;
 176:	80 93 08 28 	sts	0x2808, r24
 17a:	90 93 09 28 	sts	0x2809, r25
	timer_millis = m;
 17e:	40 93 0a 28 	sts	0x280A, r20
 182:	50 93 0b 28 	sts	0x280B, r21
 186:	60 93 0c 28 	sts	0x280C, r22
 18a:	70 93 0d 28 	sts	0x280D, r23
	timer_overflow_count++;
 18e:	80 91 04 28 	lds	r24, 0x2804
 192:	90 91 05 28 	lds	r25, 0x2805
 196:	a0 91 06 28 	lds	r26, 0x2806
 19a:	b0 91 07 28 	lds	r27, 0x2807
 19e:	01 96       	adiw	r24, 0x01	; 1
 1a0:	a1 1d       	adc	r26, r1
 1a2:	b1 1d       	adc	r27, r1
 1a4:	80 93 04 28 	sts	0x2804, r24
 1a8:	90 93 05 28 	sts	0x2805, r25
 1ac:	a0 93 06 28 	sts	0x2806, r26
 1b0:	b0 93 07 28 	sts	0x2807, r27

	/* Clear flag */
	_timer->INTFLAGS = TCB_CAPT_bm;
 1b4:	81 e0       	ldi	r24, 0x01	; 1
 1b6:	80 93 b6 0a 	sts	0x0AB6, r24
}
 1ba:	bf 91       	pop	r27
 1bc:	af 91       	pop	r26
 1be:	9f 91       	pop	r25
 1c0:	8f 91       	pop	r24
 1c2:	7f 91       	pop	r23
 1c4:	6f 91       	pop	r22
 1c6:	5f 91       	pop	r21
 1c8:	4f 91       	pop	r20
 1ca:	3f 91       	pop	r19
 1cc:	2f 91       	pop	r18
 1ce:	1f 90       	pop	r1
 1d0:	1f be       	out	0x3f, r1	; 63
 1d2:	1f 90       	pop	r1
 1d4:	18 95       	reti

000001d6 <_GLOBAL__sub_I_p13>:
  }
}
*/          
//static_assert(pin < 22, "Pin number too large, valid range 0...21");

OutputP::OutputP(uint8_t p) : pin {p}
 1d6:	8d e0       	ldi	r24, 0x0D	; 13
 1d8:	80 93 16 28 	sts	0x2816, r24
  p13.toggle();
  p13.toggle();
  p13.toggle();
  p13.toggle();
  p13.toggle(); 
}
 1dc:	08 95       	ret

000001de <main>:
	
	#elif (F_CPU == 16000000)
		cpu_freq = 16000000;
		
		/* No division on clock */
		_PROTECTED_WRITE(CLKCTRL_MCLKCTRLB, 0x00);
 1de:	88 ed       	ldi	r24, 0xD8	; 216
 1e0:	90 e0       	ldi	r25, 0x00	; 0
 1e2:	84 bf       	out	0x34, r24	; 52
 1e4:	90 93 61 00 	sts	0x0061, r25
		/* No division on clock */
		_PROTECTED_WRITE(CLKCTRL_MCLKCTRLB, 0x00);
	#endif

	/* Apply calculated value to F_CPU_CORRECTED */
	F_CPU_CORRECTED = (uint32_t)cpu_freq;
 1e8:	80 e0       	ldi	r24, 0x00	; 0
 1ea:	94 e2       	ldi	r25, 0x24	; 36
 1ec:	a4 ef       	ldi	r26, 0xF4	; 244
 1ee:	b0 e0       	ldi	r27, 0x00	; 0
 1f0:	80 93 00 28 	sts	0x2800, r24
 1f4:	90 93 01 28 	sts	0x2801, r25
 1f8:	a0 93 02 28 	sts	0x2802, r26
 1fc:	b0 93 03 28 	sts	0x2803, r27
	/* ADC clock between 50-200 kHz */

	#if F_CPU >= 20000000 // 20 MHz / 128 = 156.250 kHz
		ADC0.CTRLC |= ADC_PRESC_DIV128_gc;
	#elif F_CPU >= 16000000 // 16 MHz / 128 = 125 kHz
		ADC0.CTRLC |= ADC_PRESC_DIV128_gc;
 200:	80 91 02 06 	lds	r24, 0x0602
 204:	86 60       	ori	r24, 0x06	; 6
 206:	80 93 02 06 	sts	0x0602, r24
	#else // 128 kHz / 2 = 64 kHz -> This is the closest you can get, the prescaler is 2
		ADC0.CTRLC |= ADC_PRESC_DIV2_gc;
	#endif

	/* Enable ADC */
	ADC0.CTRLA |= ADC_ENABLE_bm;
 20a:	80 91 00 06 	lds	r24, 0x0600
 20e:	81 60       	ori	r24, 0x01	; 1
 210:	80 93 00 06 	sts	0x0600, r24
uint8_t analog_reference = DEFAULT;

void analogReference(uint8_t mode)
{
	/* Clear relevant settings */
	ADC0.CTRLC &= ~(ADC_REFSEL_gm);
 214:	80 91 02 06 	lds	r24, 0x0602
 218:	8f 7c       	andi	r24, 0xCF	; 207
 21a:	80 93 02 06 	sts	0x0602, r24
	VREF.CTRLA &= ~(VREF_ADC0REFSEL_gm);
 21e:	80 91 a0 00 	lds	r24, 0x00A0
 222:	8f 78       	andi	r24, 0x8F	; 143
 224:	80 93 a0 00 	sts	0x00A0, r24

	/* If reference NOT using internal reference from VREF */
	if((mode == EXTERNAL) || (mode == VDD)) {

		/* Set reference in ADC peripheral */
		ADC0.CTRLC |= mode;
 228:	80 91 02 06 	lds	r24, 0x0602
 22c:	80 61       	ori	r24, 0x10	; 16
 22e:	80 93 02 06 	sts	0x0602, r24
	analogReference(VDD);

#endif

	PORTMUX.USARTROUTEA = 0;
 232:	10 92 e2 05 	sts	0x05E2, r1
void setup_timers() {

  //  TYPE A TIMER  

  // PORTMUX setting for TCA -> all outputs [0:2] point to PORTB pins [0:2]
  PORTMUX.TCAROUTEA  = PORTMUX_TCA0_PORTB_gc;
 236:	81 e0       	ldi	r24, 0x01	; 1
 238:	80 93 e4 05 	sts	0x05E4, r24

  // Setup timers for single slope PWM, but do not enable, will do in analogWrite()
  TCA0.SINGLE.CTRLB = TCA_SINGLE_WGMODE_SINGLESLOPE_gc;
 23c:	83 e0       	ldi	r24, 0x03	; 3
 23e:	80 93 01 0a 	sts	0x0A01, r24

  // Period setting, 16 bit register but val resolution is 8 bit
  TCA0.SINGLE.PER = PWM_TIMER_PERIOD;
 242:	8f ef       	ldi	r24, 0xFF	; 255
 244:	90 e0       	ldi	r25, 0x00	; 0
 246:	80 93 26 0a 	sts	0x0A26, r24
 24a:	90 93 27 0a 	sts	0x0A27, r25

  // Default duty 50%, will re-assign in analogWrite()
  TCA0.SINGLE.CMP0BUF = PWM_TIMER_COMPARE;
 24e:	80 e8       	ldi	r24, 0x80	; 128
 250:	90 e0       	ldi	r25, 0x00	; 0
 252:	80 93 38 0a 	sts	0x0A38, r24
 256:	90 93 39 0a 	sts	0x0A39, r25
  TCA0.SINGLE.CMP1BUF = PWM_TIMER_COMPARE;
 25a:	80 93 3a 0a 	sts	0x0A3A, r24
 25e:	90 93 3b 0a 	sts	0x0A3B, r25
  TCA0.SINGLE.CMP2BUF = PWM_TIMER_COMPARE;
 262:	80 93 3c 0a 	sts	0x0A3C, r24
 266:	90 93 3d 0a 	sts	0x0A3D, r25

  // Use DIV64 prescaler (giving 250kHz clock), enable TCA timer
  TCA0.SINGLE.CTRLA = (TCA_SINGLE_CLKSEL_DIV64_gc) | (TCA_SINGLE_ENABLE_bm);
 26a:	8b e0       	ldi	r24, 0x0B	; 11
 26c:	80 93 00 0a 	sts	0x0A00, r24

  //  TYPE B TIMERS 
  
  // Setup TCB0 routing
  #if defined(TCB0)
    PORTMUX.TCBROUTEA |= PORTMUX_TCB0_bm; // Route signal to PF4
 270:	80 91 e5 05 	lds	r24, 0x05E5
 274:	81 60       	ori	r24, 0x01	; 1
 276:	80 93 e5 05 	sts	0x05E5, r24
  #endif
  
  // Setup TCB1 routing
  #if defined(TCB1)
    PORTMUX.TCBROUTEA  |= PORTMUX_TCB1_bm; // Route signal to PF5
 27a:	80 91 e5 05 	lds	r24, 0x05E5
 27e:	82 60       	ori	r24, 0x02	; 2
 280:	80 93 e5 05 	sts	0x05E5, r24
  #endif

  // Start with TCB0
  TCB_t *timer_B = (TCB_t *)&TCB0;
 284:	e0 e8       	ldi	r30, 0x80	; 128
 286:	fa e0       	ldi	r31, 0x0A	; 10

  // Timer B Setup loop for TCB[0:3]
  do
  {
    // 8 bit PWM mode, but do not enable output yet, will do in analogWrite()
    timer_B->CTRLB = (TCB_CNTMODE_PWM8_gc);
 288:	37 e0       	ldi	r19, 0x07	; 7

    // Assign 8-bit period
    timer_B->CCMPL = PWM_TIMER_PERIOD;
 28a:	2f ef       	ldi	r18, 0xFF	; 255

    // default duty 50%, set when output enabled
    timer_B->CCMPH = PWM_TIMER_COMPARE;
 28c:	90 e8       	ldi	r25, 0x80	; 128

    // Use TCA clock (250kHz) and enable
    // (sync update commented out, might try to synchronize later
    timer_B->CTRLA = (TCB_CLKSEL_CLKTCA_gc)
 28e:	85 e0       	ldi	r24, 0x05	; 5

  // Timer B Setup loop for TCB[0:3]
  do
  {
    // 8 bit PWM mode, but do not enable output yet, will do in analogWrite()
    timer_B->CTRLB = (TCB_CNTMODE_PWM8_gc);
 290:	31 83       	std	Z+1, r19	; 0x01

    // Assign 8-bit period
    timer_B->CCMPL = PWM_TIMER_PERIOD;
 292:	24 87       	std	Z+12, r18	; 0x0c

    // default duty 50%, set when output enabled
    timer_B->CCMPH = PWM_TIMER_COMPARE;
 294:	95 87       	std	Z+13, r25	; 0x0d

    // Use TCA clock (250kHz) and enable
    // (sync update commented out, might try to synchronize later
    timer_B->CTRLA = (TCB_CLKSEL_CLKTCA_gc)
 296:	80 83       	st	Z, r24
            //|(TCB_SYNCUPD_bm)
            |(TCB_ENABLE_bm);

    // Increment pointer to next TCB instance
    timer_B++;
 298:	70 96       	adiw	r30, 0x10	; 16

  // Stop when pointing to TCB3
  } while (timer_B <= timer_B_end);
 29a:	e0 3c       	cpi	r30, 0xC0	; 192
 29c:	4a e0       	ldi	r20, 0x0A	; 10
 29e:	f4 07       	cpc	r31, r20
 2a0:	b9 f7       	brne	.-18     	; 0x290 <main+0xb2>
	setup_timers();

	/********************* TIMER for system time tracking **************************/

	/* Calculate relevant time tracking values */
	microseconds_per_timer_overflow = clockCyclesToMicroseconds(TIME_TRACKING_CYCLES_PER_OVF);
 2a2:	80 e0       	ldi	r24, 0x00	; 0
 2a4:	94 e0       	ldi	r25, 0x04	; 4
 2a6:	80 93 14 28 	sts	0x2814, r24
 2aa:	90 93 15 28 	sts	0x2815, r25
	microseconds_per_timer_tick = microseconds_per_timer_overflow/TIME_TRACKING_TIMER_PERIOD;
 2ae:	80 91 14 28 	lds	r24, 0x2814
 2b2:	90 91 15 28 	lds	r25, 0x2815
 2b6:	2f ef       	ldi	r18, 0xFF	; 255
 2b8:	30 e0       	ldi	r19, 0x00	; 0
 2ba:	b9 01       	movw	r22, r18
 2bc:	0e 94 af 01 	call	0x35e	; 0x35e <__udivmodhi4>
 2c0:	60 93 12 28 	sts	0x2812, r22
 2c4:	70 93 13 28 	sts	0x2813, r23

	millis_inc = microseconds_per_timer_overflow / 1000;
 2c8:	80 91 14 28 	lds	r24, 0x2814
 2cc:	90 91 15 28 	lds	r25, 0x2815
 2d0:	e8 ee       	ldi	r30, 0xE8	; 232
 2d2:	f3 e0       	ldi	r31, 0x03	; 3
 2d4:	bf 01       	movw	r22, r30
 2d6:	0e 94 af 01 	call	0x35e	; 0x35e <__udivmodhi4>
 2da:	60 93 10 28 	sts	0x2810, r22
 2de:	70 93 11 28 	sts	0x2811, r23
	fract_inc = ((microseconds_per_timer_overflow % 1000));
 2e2:	80 91 14 28 	lds	r24, 0x2814
 2e6:	90 91 15 28 	lds	r25, 0x2815
 2ea:	bf 01       	movw	r22, r30
 2ec:	0e 94 af 01 	call	0x35e	; 0x35e <__udivmodhi4>
 2f0:	80 93 0e 28 	sts	0x280E, r24
 2f4:	90 93 0f 28 	sts	0x280F, r25

	/* Default Periodic Interrupt Mode */
	/* TOP value for overflow every 1024 clock cycles */
	_timer->CCMP = TIME_TRACKING_TIMER_PERIOD;
 2f8:	20 93 bc 0a 	sts	0x0ABC, r18
 2fc:	30 93 bd 0a 	sts	0x0ABD, r19

	/* Enable timer interrupt */
	_timer->INTCTRL |= TCB_CAPT_bm;
 300:	80 91 b5 0a 	lds	r24, 0x0AB5
 304:	81 60       	ori	r24, 0x01	; 1
 306:	80 93 b5 0a 	sts	0x0AB5, r24

	/* Clock selection -> same as TCA (F_CPU/64 -- 250kHz) */
	_timer->CTRLA = TCB_CLKSEL_CLKTCA_gc;
 30a:	84 e0       	ldi	r24, 0x04	; 4
 30c:	80 93 b0 0a 	sts	0x0AB0, r24

	/* Enable & start */
	_timer->CTRLA |= TCB_ENABLE_bm;	/* Keep this last before enabling interrupts to ensure tracking as accurate as possible */
 310:	80 91 b0 0a 	lds	r24, 0x0AB0
 314:	81 60       	ori	r24, 0x01	; 1
 316:	80 93 b0 0a 	sts	0x0AB0, r24

/*************************** ENABLE GLOBAL INTERRUPTS *************************/

	sei();
 31a:	78 94       	sei

using Register8 = volatile uint8_t*;

// ------------------ VPORTs ----------------------------------------------------------------------------------------------- //                
// Direction
constexpr Register8 regVPORTdir(const uint8_t pin)      { using namespace Pins::Addr; return (Register8) (baseAddr[pin].vport + addrOffset.vDir); }
 31c:	e0 91 16 28 	lds	r30, 0x2816
 320:	86 e0       	ldi	r24, 0x06	; 6
 322:	e8 9f       	mul	r30, r24
 324:	f0 01       	movw	r30, r0
 326:	11 24       	eor	r1, r1
 328:	ea 56       	subi	r30, 0x6A	; 106
 32a:	fc 4b       	sbci	r31, 0xBC	; 188
 32c:	a0 81       	ld	r26, Z
 32e:	b1 81       	ldd	r27, Z+1	; 0x01

OutputP::OutputP(uint8_t p) : pin {p}
{}
  
// Outputs
void OutputP::init() { *regVPORTdir(pin) = *regVPORTdir(pin) | getMask(pin); }
 330:	8c 91       	ld	r24, X
 332:	95 81       	ldd	r25, Z+5	; 0x05
 334:	89 2b       	or	r24, r25
 336:	8c 93       	st	X, r24

	setup();

	for (;;) {
		loop();
		if (serialEventRun) serialEventRun();
 338:	c0 e0       	ldi	r28, 0x00	; 0
 33a:	d0 e0       	ldi	r29, 0x00	; 0
  p13.init(); 
}

void loop()
{
  p13.toggle();   // 2µs
 33c:	0e 94 7b 00 	call	0xf6	; 0xf6 <_ZN7OutputP6toggleEv.constprop.0>
  p13.toggle();
 340:	0e 94 7b 00 	call	0xf6	; 0xf6 <_ZN7OutputP6toggleEv.constprop.0>
  p13.toggle();
 344:	0e 94 7b 00 	call	0xf6	; 0xf6 <_ZN7OutputP6toggleEv.constprop.0>
  p13.toggle();
 348:	0e 94 7b 00 	call	0xf6	; 0xf6 <_ZN7OutputP6toggleEv.constprop.0>
  p13.toggle();
 34c:	0e 94 7b 00 	call	0xf6	; 0xf6 <_ZN7OutputP6toggleEv.constprop.0>
  p13.toggle(); 
 350:	0e 94 7b 00 	call	0xf6	; 0xf6 <_ZN7OutputP6toggleEv.constprop.0>
 354:	20 97       	sbiw	r28, 0x00	; 0
 356:	91 f3       	breq	.-28     	; 0x33c <main+0x15e>
 358:	0e 94 00 00 	call	0	; 0x0 <__vectors>
 35c:	ef cf       	rjmp	.-34     	; 0x33c <main+0x15e>

0000035e <__udivmodhi4>:
 35e:	aa 1b       	sub	r26, r26
 360:	bb 1b       	sub	r27, r27
 362:	51 e1       	ldi	r21, 0x11	; 17
 364:	07 c0       	rjmp	.+14     	; 0x374 <__udivmodhi4_ep>

00000366 <__udivmodhi4_loop>:
 366:	aa 1f       	adc	r26, r26
 368:	bb 1f       	adc	r27, r27
 36a:	a6 17       	cp	r26, r22
 36c:	b7 07       	cpc	r27, r23
 36e:	10 f0       	brcs	.+4      	; 0x374 <__udivmodhi4_ep>
 370:	a6 1b       	sub	r26, r22
 372:	b7 0b       	sbc	r27, r23

00000374 <__udivmodhi4_ep>:
 374:	88 1f       	adc	r24, r24
 376:	99 1f       	adc	r25, r25
 378:	5a 95       	dec	r21
 37a:	a9 f7       	brne	.-22     	; 0x366 <__udivmodhi4_loop>
 37c:	80 95       	com	r24
 37e:	90 95       	com	r25
 380:	bc 01       	movw	r22, r24
 382:	cd 01       	movw	r24, r26
 384:	08 95       	ret

00000386 <__tablejump2__>:
 386:	ee 0f       	add	r30, r30
 388:	ff 1f       	adc	r31, r31
 38a:	05 90       	lpm	r0, Z+
 38c:	f4 91       	lpm	r31, Z
 38e:	e0 2d       	mov	r30, r0
 390:	09 94       	ijmp

00000392 <_exit>:
 392:	f8 94       	cli

00000394 <__stop_program>:
 394:	ff cf       	rjmp	.-2      	; 0x394 <__stop_program>