----------------------------------------------------------------------------------
-- Company: www.Circuit-Break.de
-- Engineer: Jens Weiss
-- 
-- Create Date:    22:28:14 12/03/2020 
-- Design Name: 
-- Module Name:    SRAM_Operation - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity SRAM_Operation is
	Generic (ADDR_WIDTH : integer range 8 to 24 := 19;
				DATA_WIDTH : integer range 8 to 32 := 8;
				WAITSTATES : integer range 0 to 31 := 3;
				INIT_CRC : std_logic_vector(7 downto 0) := "01011010");
    Port ( clk : in  std_logic;
           reset : in  std_logic;
           SRAM_Addr : out  std_logic_vector(ADDR_WIDTH-1 downto 0);
           SRAM_Data_in : in  std_ulogic_vector(DATA_WIDTH-1 downto 0);
           SRAM_Data_out : out  std_ulogic_vector(DATA_WIDTH-1 downto 0);
           SRAM_CSn : out  std_logic;
           SRAM_rw : out  std_logic;
           SRAM_exe : out  std_logic;
			  SRAM_done : in std_logic;
			  Execution : in std_logic);
end SRAM_Operation;

architecture Behavioral of SRAM_Operation is
	type state_type is (idle, read_ram1, read_ram2, modify, write_ram1, write_ram2, write_ram3, increment, check);
	signal state_reg : state_type;
	
	signal int_SRAM_Addr : integer range 0 to (2**ADDR_WIDTH);
	signal internal_SRAM_Data_out : std_logic_vector(DATA_WIDTH-1 downto 0);
   signal internal_SRAM_CSn : std_logic;
   signal internal_SRAM_rw : std_logic;
   signal internal_SRAM_exe : std_logic;
	signal delay : integer range 0 to WAITSTATES;
	signal int_crc : std_logic_vector(DATA_WIDTH-1 downto 0) := INIT_CRC;
	
begin

	process(clk)
	begin
		if rising_edge(clk) then
			if (reset = '1') then
				internal_SRAM_CSn <= '1';
				internal_SRAM_rw <= '0';
				internal_SRAM_exe <= '0';
				int_SRAM_Addr <= 0;
				state_reg <= idle;
			else
			
				case state_reg is										--stay idle until "Execution" is triggered
					when idle =>
						internal_SRAM_CSn <= '1';
						internal_SRAM_rw <= '0';
						internal_SRAM_exe <= '0';
						int_SRAM_Addr <= 0;
						
						if(Execution = '1') then					--if triggered, select SRAM
							internal_SRAM_CSn <= '0';				--select SRAM
							state_reg <= read_ram1;
						end if;
						
					when read_ram1 =>									--read value from SRAM
						if(SRAM_done = '1') then					--wait for SRAM ready
							internal_SRAM_exe <= '1';				--start process
							internal_SRAM_rw <= '0';				--read first value from SRAM
							state_reg <= read_ram2;
						end if;
												
					when read_ram2 =>
						if (SRAM_done = '0') then					--check that SRAM is working
							internal_SRAM_exe <= '0';
							state_reg <= modify;
						end if;
						
					when modify =>		
						internal_SRAM_Data_out <= to_stdlogicvector(SRAM_Data_in) XOR int_crc;	--sample new value	
						if (SRAM_done = '1') then					--wait for completion read operation
							state_reg <= write_ram1;
						end if;
					
					when write_ram1 =>								--write value back
						int_crc <= internal_SRAM_Data_out;
						internal_SRAM_exe <= '1';					--start process
						internal_SRAM_rw <= '1';					--perform writing
						state_reg <= write_ram2;
						
					when write_ram2 =>
						if (SRAM_done = '0') then					--check that SRAM is working
							internal_SRAM_exe <= '0';	
							state_reg <= write_ram3;
						end if;
						
					when write_ram3 =>
						if (SRAM_done = '1') then					--wait for completion read operation
							state_reg <= increment;
						end if;
						
					when increment =>									--increment address and go on
						int_SRAM_Addr <= int_SRAM_Addr + 1;
						state_reg <= check;
												
					when check =>
						if(int_SRAM_Addr <= 2**ADDR_WIDTH-1) then
							state_reg <= read_ram1;
						else
							state_reg <= idle;						--finish operation
						end if;
					
				end case;
			end if;
		end if;
	end process;
	
	SRAM_Addr <= std_logic_vector(to_unsigned(int_SRAM_Addr, ADDR_WIDTH));
	SRAM_Data_out <= to_stdulogicvector(internal_SRAM_Data_out);
   SRAM_CSn <= internal_SRAM_CSn;
   SRAM_rw <= internal_SRAM_rw;
   SRAM_exe <= internal_SRAM_exe;

end Behavioral;