----------------------------------------------------------------------------------
-- Company: www.Circuit-Break.de
-- Engineer: Jens Weiss
-- 
-- Create Date:    00:50:20 06/06/2021 
-- Design Name: 
-- Module Name:    SRAM_Bus_Interface - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity SRAM_Bus_Interface is
	Generic(	DATA_WIDTH : integer := 8;
				ADRESS_WIDTH : integer := 19);
				
	Port(-- Signale to external SRAM
			CEn : in std_logic;
			OEn : in std_logic;
			WEn : in std_logic;
			SRAM_CEn : out std_logic;
			SRAM_OEn : out std_logic;
			SRAM_WEn : out std_logic;
			SRAM_Addr : out std_logic_vector(ADRESS_WIDTH-1 downto 0);
			SRAM_Data : inout std_logic_vector(DATA_WIDTH-1 downto 0);
			uC_Adress : in std_logic_vector(ADRESS_WIDTH-1 downto 0);
			uC_Data_in : in std_ulogic_vector(DATA_WIDTH-1 downto 0);
			uC_Data_out : out std_ulogic_vector(DATA_WIDTH-1 downto 0);
			FPGA_Adress : in std_logic_vector(ADRESS_WIDTH-1 downto 0);
			FPGA_Data_in : in std_ulogic_vector(DATA_WIDTH-1 downto 0);
			FPGA_Data_out : out std_ulogic_vector(DATA_WIDTH-1 downto 0);
			Data_Select : in std_logic;
			Data_Direction : in std_logic);				
end SRAM_Bus_Interface;

architecture Behavioral of SRAM_Bus_Interface is

begin

	process(Data_Select, Data_Direction, uC_Data_in, FPGA_Data_in, uC_Adress, FPGA_Adress)
	begin
		if(Data_Select = '0') and (Data_Direction = '1') then
			SRAM_Data <= to_stdlogicvector(uC_Data_in);
			SRAM_Addr <= uC_Adress;
			
		elsif (Data_Select = '1') and (Data_Direction = '1') then
			SRAM_Data <= to_stdlogicvector(FPGA_Data_in);
			SRAM_Addr <= FPGA_Adress;
			
		elsif (Data_Select <= '0') and (Data_Direction <= '0') then 
			SRAM_Data <= (others => 'Z');	
			SRAM_Addr <= uC_Adress;
			
		elsif (Data_Select <= '1') and (Data_Direction <= '0') then 
			SRAM_Data <= (others => 'Z');	
			SRAM_Addr <= FPGA_Adress;
		
		else
			SRAM_Data <= (others => 'Z');	
			SRAM_Addr <= (others => 'Z');			
		end if;
	end process;

SRAM_CEn <= CEn;
SRAM_OEn <= OEn;
SRAM_WEn <= WEn;
uC_Data_out <= to_stdulogicvector(SRAM_Data);
FPGA_Data_out <= to_stdulogicvector(SRAM_Data);

end Behavioral;