--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   11:32:11 12/02/2020
-- Design Name:   
-- Module Name:   D:/Xilinx_Projekts/Dual_Port_SRAM/Mem_Controller_tb.vhd
-- Project Name:  Dual_Port_SRAM
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: Memory_Controller
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;
 
-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
--USE ieee.numeric_std.ALL;
 
ENTITY Mem_Controller_tb IS
END Mem_Controller_tb;
 
ARCHITECTURE behavior OF Mem_Controller_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT Memory_Controller
    PORT(
         clk : IN  std_logic;
			reset : IN  std_logic;
         RAM_uC_Adress : out std_logic_vector(18 downto 0);
			RAM_uC_Data_in : in std_ulogic_vector(7 downto 0);
			RAM_uC_Data_out : out std_ulogic_vector(7 downto 0);
			RAM_FPGA_Adress : out std_logic_vector(18 downto 0);
			RAM_FPGA_Data_in : in std_ulogic_vector(7 downto 0);
			RAM_FPGA_Data_out : out std_ulogic_vector(7 downto 0);
			RAM_Data_Select : out std_logic;
			RAM_Data_Direction : out std_logic;	
			RAM_CEn : out std_logic;
			RAM_OEn : out std_logic;
			RAM_WEn : out std_logic;
         uC_Data_Addr : INOUT  std_logic_vector(7 downto 0);
         uC_AD16 : IN  std_logic;
         uC_AD17 : IN  std_logic;
         uC_AD18 : IN  std_logic;
         uC_ALE0 : IN  std_logic;
         uC_ALE1 : IN  std_logic;
         uC_CEn : IN  std_logic;
         uC_OEn : IN  std_logic;
         uC_WEn : IN  std_logic;
         Ram_busy : OUT  std_logic;
         Ram_error : OUT  std_logic;
			RAM_done : out std_logic;
         FPGA_Addr : IN  std_logic_vector(18 downto 0);
         FPGA_Data_in : IN  std_ulogic_vector(7 downto 0);
         FPGA_Data_out : OUT  std_ulogic_vector(7 downto 0);
         FPGA_CEn : IN  std_logic;
         FPGA_rw : IN  std_logic;
			FPGA_start : IN std_logic
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
	signal reset : std_logic := '0';
   signal uC_AD16 : std_logic := '0';
   signal uC_AD17 : std_logic := '0';
   signal uC_AD18 : std_logic := '0';
   signal uC_ALE0 : std_logic := '0';
   signal uC_ALE1 : std_logic := '0';
   signal uC_CEn : std_logic := '1';
   signal uC_OEn : std_logic := '1';
   signal uC_WEn : std_logic := '1';
   signal FPGA_Addr : std_logic_vector(18 downto 0) := (others => '0');
   signal FPGA_Data_in : std_ulogic_vector(7 downto 0) := (others => '0');
   signal FPGA_CEn : std_logic := '1';
   signal FPGA_rw : std_logic := '0';
	signal FPGA_start : std_logic := '0';
	signal RAM_uC_Data_in : std_ulogic_vector(7 downto 0);
	signal RAM_FPGA_Data_in : std_ulogic_vector(7 downto 0);

	--BiDirs
   signal uC_Data_Addr : std_logic_vector(7 downto 0);

 	--Outputs
   signal RAM_uC_Adress : std_logic_vector(18 downto 0);
	signal RAM_uC_Data_out : std_ulogic_vector(7 downto 0);
	signal RAM_FPGA_Adress : std_logic_vector(18 downto 0);
	signal RAM_FPGA_Data_out : std_ulogic_vector(7 downto 0);
	signal RAM_Data_Select : std_logic := '0';
	signal RAM_Data_Direction : std_logic := '0';	
	signal RAM_CEn : std_logic := '1';
	signal RAM_OEn : std_logic := '1';
	signal RAM_WEn : std_logic := '1';
   signal Ram_busy : std_logic;
   signal Ram_error : std_logic;
	signal RAM_done : std_logic;
   signal FPGA_Data_out : std_ulogic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 10.42 ns;
	
	-- Steuerleitung für SRAM
	signal file_download : boolean := FALSE;
	signal file_dump : boolean := FALSE;
	 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: Memory_Controller PORT MAP (
          clk => clk,
			 reset => reset,
          RAM_uC_Adress => RAM_uC_Adress,
			 RAM_uC_Data_in => RAM_uC_Data_in,
			 RAM_uC_Data_out => RAM_uC_Data_out,
			 RAM_FPGA_Adress => RAM_FPGA_Adress,
			 RAM_FPGA_Data_in => RAM_FPGA_Data_in,
			 RAM_FPGA_Data_out => RAM_FPGA_Data_out,
			 RAM_Data_Select => RAM_Data_Select,
			 RAM_Data_Direction => RAM_Data_Direction,
			 RAM_CEn => RAM_CEn,
			 RAM_OEn => RAM_OEn,
			 RAM_WEn => RAM_WEn,
          uC_Data_Addr => uC_Data_Addr,
          uC_AD16 => uC_AD16,
          uC_AD17 => uC_AD17,
          uC_AD18 => uC_AD18,
          uC_ALE0 => uC_ALE0,
          uC_ALE1 => uC_ALE1,
          uC_CEn => uC_CEn,
          uC_OEn => uC_OEn,
          uC_WEn => uC_WEn,
          Ram_busy => Ram_busy,
          Ram_error => Ram_error,
			 RAM_done => RAM_done,
          FPGA_Addr => FPGA_Addr,
          FPGA_Data_in => FPGA_Data_in,
          FPGA_Data_out => FPGA_Data_out,
          FPGA_CEn => FPGA_CEn,
          FPGA_rw => FPGA_rw,
			 FPGA_start => FPGA_start
        );
		  
--	sram: entity work.sram 
--	PORT MAP(
--		nCE => SRAM_CEn,
--		nOE => SRAM_OEn,
--		nWE => SRAM_WEn,
--		download => file_download,
--		dump => file_dump,
--		A => SRAM_Addr,
--		D => SRAM_Data		
--		);

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
	
	 
   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 100 ns;	
		
		--reset operation
		reset <= '1';
		wait for 35ns;	
		reset <= '0';
		wait for 35ns;	
		
		--uC read operation
		uC_CEn <= '0';
		wait for 32ns;
		uC_AD16	<= '0'; 
      uC_AD17	<= '0'; 
      uC_AD18	<= '0'; 
		
		uC_Data_Addr <= std_logic_vector(to_unsigned(0, 8));
		uC_ALE1 <= '1';
		wait for 32ns;
		uC_ALE1 <= '0';
		wait for 32ns;
		
		uC_Data_Addr <= std_logic_vector(to_unsigned(0, 8));
		uC_ALE0 <= '1';
		wait for 32ns;
		uC_ALE0 <= '0';
		wait for 32ns;
		
		uC_Data_Addr <= (others => 'Z');
		uC_OEn <= '0';
		wait for 32ns;
		uC_OEn <= '1';
		wait for 32ns;		
		uC_CEn <= '1';		
		
		wait for 200ns;
		
		--uC write operation
		uC_CEn <= '0';
		wait for 32ns;
		uC_AD16	<= '0'; 
      uC_AD17	<= '0'; 
      uC_AD18	<= '0'; 
		
		uC_Data_Addr <= std_logic_vector(to_unsigned(0, 8));
		uC_ALE1 <= '1';
		wait for 32ns;
		uC_ALE1 <= '0';
		wait for 32ns;
		
		uC_Data_Addr <= std_logic_vector(to_unsigned(1, 8));
		uC_ALE0 <= '1';
		wait for 32ns;
		uC_ALE0 <= '0';
		wait for 32ns;
		
		uC_Data_Addr <= std_logic_vector(to_unsigned(30, 8));
		uC_WEn <= '0';
		wait for 32ns;
		uC_WEn <= '1';
		wait for 32ns;		
		uC_Data_Addr <= (others => 'Z');
		uC_CEn <= '1';		
		
		wait for 200ns;
		
		--uC read operation
		uC_CEn <= '0';
		wait for 32ns;
		uC_AD16	<= '0'; 
      uC_AD17	<= '0'; 
      uC_AD18	<= '0'; 
		
		uC_Data_Addr <= std_logic_vector(to_unsigned(0, 8));
		uC_ALE1 <= '1';
		wait for 32ns;
		uC_ALE1 <= '0';
		wait for 32ns;
		
		uC_Data_Addr <= std_logic_vector(to_unsigned(1, 8));
		uC_ALE0 <= '1';
		wait for 32ns;
		uC_ALE0 <= '0';
		wait for 32ns;
		
		uC_Data_Addr <= (others => 'Z');
		uC_OEn <= '0';
		wait for 32ns;
		uC_OEn <= '1';
		wait for 32ns;		
		uC_CEn <= '1';		
		
		wait for 200ns;

		--FPGA read operation
		FPGA_CEn <= '0';
		wait for 35ns;
		RAM_FPGA_Data_in <= "11001111";
		FPGA_Addr <= "0000000000000000000";
		FPGA_rw <= '0';
		FPGA_start <= '1';
		wait for 15ns;
		FPGA_start <= '0';
		wait for 135ns;
		
		--FPGA write operation
		FPGA_CEn <= '0';
		wait for 35ns;
		FPGA_Data_in <= "00001111";
		FPGA_Addr <= "0000000000000000000";
		FPGA_rw <= '1';
		FPGA_start <= '1';
		wait for 15ns;
		FPGA_start <= '0';
		wait for 135ns;
		
		FPGA_CEn <= '1';
		wait for 200ns;
		
		--write results to file
		file_dump <= TRUE; 
		wait for 100ns;
		file_dump <= FALSE;
		wait for 100ns;


      wait;
   end process;

END;