-- Vhdl test bench created from schematic D:\Xilinx_Projekts\Dual_Port_SRAM\Memory_Interface.sch - Mon Jun 07 08:34:44 2021
--
-- Notes: 
-- 1) This testbench template has been automatically generated using types
-- std_logic and std_logic_vector for the ports of the unit under test.
-- Xilinx recommends that these types always be used for the top-level
-- I/O of a design in order to guarantee that the testbench will bind
-- correctly to the timing (post-route) simulation model.
-- 2) To use this template as your testbench, change the filename to any
-- name of your choice with the extension .vhd, and use the "Source->Add"
-- menu in Project Navigator to import the testbench. Then
-- edit the user defined section below, adding code to generate the 
-- stimulus for your design.
--
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.numeric_std.ALL;


ENTITY Memory_Interface_Memory_Interface_sch_tb IS
END Memory_Interface_Memory_Interface_sch_tb;
ARCHITECTURE behavioral OF Memory_Interface_Memory_Interface_sch_tb IS 

   COMPONENT Memory_Interface
   PORT( uC_Data_Addr	:	INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          uC_AD16	:	IN	STD_LOGIC; 
          uC_AD17	:	IN	STD_LOGIC; 
          uC_AD18	:	IN	STD_LOGIC; 
          uC_ALE0	:	IN	STD_LOGIC; 
          uC_ALE1	:	IN	STD_LOGIC; 
          uC_CEn	:	IN	STD_LOGIC; 
          uC_OEn	:	IN	STD_LOGIC; 
          uC_WEn	:	IN	STD_LOGIC; 
          uC_clk	:	IN	STD_LOGIC; 
          uC_Execution	:	IN	STD_LOGIC; 
          uC_busy	:	OUT	STD_LOGIC; 
          uC_error	:	OUT	STD_LOGIC; 
          CEn	:	OUT	STD_LOGIC; 
          OEn	:	OUT	STD_LOGIC; 
          WEn	:	OUT	STD_LOGIC; 
          error	:	OUT	STD_LOGIC; 
          uC_reset	:	IN	STD_LOGIC; 
          SRAM_Data	:	INOUT	STD_LOGIC_VECTOR (7 DOWNTO 0); 
          SRAM_Addr	:	OUT	STD_LOGIC_VECTOR (18 DOWNTO 0); 
          SRAM_CEn	:	OUT	STD_LOGIC; 
          SRAM_OEn	:	OUT	STD_LOGIC; 
          SRAM_WEn	:	OUT	STD_LOGIC);
   END COMPONENT;

	--inputs
	signal uC_clk	:	STD_LOGIC := '0';
	signal uC_reset	:	STD_LOGIC := '0';
	signal uC_AD16	:	STD_LOGIC := '0';
   signal uC_AD17	:	STD_LOGIC := '0';
   signal uC_AD18	:	STD_LOGIC := '0';
   signal uC_ALE0	:	STD_LOGIC := '0';
   signal uC_ALE1	:	STD_LOGIC := '0';
   signal uC_CEn	:	STD_LOGIC := '1';
   signal uC_OEn	:	STD_LOGIC := '1';
   signal uC_WEn	:	STD_LOGIC := '1';   
   signal uC_Execution	:	STD_LOGIC := '0';	
	
	--outputs
	signal uC_busy	:	STD_LOGIC;
   signal uC_error	:	STD_LOGIC;
	signal CEn	:	STD_LOGIC := '1';
   signal OEn	:	STD_LOGIC := '1';
   signal WEn	:	STD_LOGIC := '1';
   signal error	:	STD_LOGIC;
	signal SRAM_Addr	:	STD_LOGIC_VECTOR (18 DOWNTO 0);
	signal SRAM_CEn	:	STD_LOGIC := '1';
   signal SRAM_OEn	:	STD_LOGIC := '1';
   signal SRAM_WEn	:	STD_LOGIC := '1';
	
	--Bidirectional
	signal uC_Data_Addr	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   signal SRAM_Data	:	STD_LOGIC_VECTOR (7 DOWNTO 0);
   
	-- Clock period definitions
   constant uC_clk_period : time := 31.25 ns;
	
	-- Steuerleitung für SRAM
	signal file_download : boolean := FALSE;
	signal file_dump : boolean := FALSE;
	
BEGIN

   UUT: Memory_Interface PORT MAP(
		uC_Data_Addr => uC_Data_Addr, 
		uC_AD16 => uC_AD16, 
		uC_AD17 => uC_AD17, 
		uC_AD18 => uC_AD18, 
		uC_ALE0 => uC_ALE0, 
		uC_ALE1 => uC_ALE1, 
		uC_CEn => uC_CEn, 
		uC_OEn => uC_OEn, 
		uC_WEn => uC_WEn, 
		uC_clk => uC_clk, 
		uC_Execution => uC_Execution, 
		uC_busy => uC_busy, 
		uC_error => uC_error, 
		CEn => CEn, 
		OEn => OEn, 
		WEn => WEn, 
		error => error, 
		uC_reset => uC_reset, 
		SRAM_Data => SRAM_Data, 
		SRAM_Addr => SRAM_Addr, 
		SRAM_CEn => SRAM_CEn, 
		SRAM_OEn => SRAM_OEn, 
		SRAM_WEn => SRAM_WEn
   );

Sram: entity work.Sram 
	PORT MAP(
		nCE => SRAM_CEn,
		nOE => SRAM_OEn,
		nWE => SRAM_WEn,
		download => file_download,
		dump => file_dump,
		A => SRAM_Addr,
		D => SRAM_Data		
		);
	
	-- Clock process definitions
   uC_clk_process :process
   begin
		uC_clk <= '0';
		wait for uC_clk_period/2;
		uC_clk <= '1';
		wait for uC_clk_period/2;
   end process;
	
	
	-- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
      wait for 500 ns;	

      -- insert stimulus here 
		uC_reset <= '1';
		wait for 50ns;
		uC_reset <= '0';
		wait for 500ns;
		
		uC_Execution <= '1';
		wait for 50ns;
		uC_Execution <= '0';
		wait for 50ns;
		
		wait for 6us;
		file_dump <= TRUE;
		
		wait;
   end process;

END;