----------------------------------------------------------------------------------
-- Company: www.Circuit-Break.de
-- Engineer: Jens Weiss
-- 
-- Create Date:    13:29:13 12/17/2020 
-- Design Name: 
-- Module Name:    Memory_Interface - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;


entity Memory_Interface is
    Port ( uC_clk : in  std_logic;
           uC_reset : in  std_logic;
           uc_error : out  std_logic;
           uC_busy : out  std_logic;
           uC_Data_Addr : inout  std_logic_vector (7 downto 0);
           uC_AD16 : in  std_logic;
           uC_AD17 : in  std_logic;
           uC_AD18 : in  std_logic;
           uC_ALE0 : in  std_logic;
           uC_ALE1 : in  std_logic;
           uC_CEn : in  std_logic;
           uC_OEn : in  std_logic;
           uC_WEn : in  std_logic;
			  uC_Execution : in std_logic;
           SRAM_Data : inout  std_logic_vector (7 downto 0);
           SRAM_Addr : out  std_logic_vector (18 downto 0);
           SRAM_CEn : out  std_logic;
           SRAM_OEn : out  std_logic;
           SRAM_WEn : out  std_logic;
			  FPGA_IO_out : out std_logic_vector(3 downto 0));
end Memory_Interface;

architecture Behavioral of Memory_Interface is
signal clk_160 : std_logic;
signal clk_locked : std_logic;
signal internal_ram_error : std_logic;
signal internal_ram_busy : std_logic;
signal internal_RAM_done : std_logic;
signal internal_FPGA_Addr : std_logic_vector (18 downto 0);
signal internal_FPGA_Data_out : std_logic_vector (7 downto 0);
signal internal_FPGA_Data_in : std_logic_vector (7 downto 0);
signal internal_FPGA_CEn : std_logic;
signal internal_FPGA_rw : std_logic;
signal internal_FPGA_start : std_logic;

begin

my_memory_controller: entity work.Memory_Controller
	port map(-- clock signal 
				clk => clk_160,
				reset => uC_reset,
				SRAM_CEn => SRAM_CEn,
				SRAM_OEn => SRAM_OEn,
				SRAM_WEn => SRAM_WEn,
				SRAM_Addr => SRAM_Addr,
				SRAM_Data => SRAM_Data,
				uC_Data_Addr => uC_Data_Addr,
				uC_AD16 => uC_AD16,
				uC_AD17 => uC_AD17,
				uC_AD18 => uC_AD18,
				uC_ALE0 => uC_ALE0,
				uC_ALE1 => uC_ALE1,
				uC_CEn => uC_CEn,
				uC_OEn => uC_OEn,
				uC_WEn => uC_WEn,
				Ram_busy => internal_ram_busy,
				Ram_error => internal_ram_error,
				RAM_done => internal_RAM_done,
				FPGA_Addr => internal_FPGA_Addr,
				FPGA_Data_in => internal_FPGA_Data_in,
				FPGA_Data_out => internal_FPGA_Data_out,
				FPGA_CEn => internal_FPGA_CEn,
				FPGA_rw => internal_FPGA_rw,
				FPGA_start => internal_FPGA_start);
	
my_sram_operation: entity work.SRAM_Operation
	port map(clk => clk_160,
           reset => uC_reset,
           SRAM_Addr => internal_FPGA_Addr,
           SRAM_Data_in => internal_FPGA_Data_out,
           SRAM_Data_out => internal_FPGA_Data_in,
           SRAM_CSn => internal_FPGA_CEn,
           SRAM_rw => internal_FPGA_rw,
           SRAM_exe => internal_FPGA_start,
			  SRAM_done => internal_RAM_done,
			  Execution => uC_Execution);
	
my_clk_manager: entity work.clk_manager
	port map(clk_in => uC_clk,
				clk_160 => clk_160,
				reset  => uC_reset,
				locked => clk_locked);
				
uC_error <= (not clk_locked) or internal_ram_error;
uC_busy <= internal_ram_busy;
FPGA_IO_out(3) <= uC_Execution;
FPGA_IO_out(2) <= internal_ram_busy;
FPGA_IO_out(1) <= internal_ram_error;
FPGA_IO_out(0) <= uC_reset;

end Behavioral;