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-- Company: 
-- Engineer: 
-- 
-- Create Date:    21:36:50 06/11/2021 
-- Design Name: 
-- Module Name:    Top - Behavioral 
-- Project Name: 
-- Target Devices: 
-- Tool versions: 
-- Description: 
--
-- Dependencies: 
--
-- Revision: 
-- Revision 0.01 - File Created
-- Additional Comments: 
--
--
----------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

-- Uncomment the following library declaration if using
-- arithmetic functions with Signed or Unsigned values
use IEEE.NUMERIC_STD.ALL;

-- Uncomment the following library declaration if instantiating
-- any Xilinx primitives in this code.
--library UNISIM;
--use UNISIM.VComponents.all;

entity Top is
	port (
		-- LVDS input
		IN_CLK_P: IN std_logic;					-- Clock is appr. 100 MHz
		IN_CLK_N: IN std_logic;
		IN_DATA0_P: IN std_logic;
		IN_DATA0_N: IN std_logic;
		IN_DATA1_P: IN std_logic;
		IN_DATA1_N: IN std_logic;
		OUT_X_P: OUT std_logic;
		OUT_X_N: OUT std_logic;
		-- LVDS output
		OUT_CLK_P: OUT std_logic;
		OUT_CLK_N: OUT std_logic;
		OUT_DATA0_P: OUT std_logic;
		OUT_DATA0_N: OUT std_logic;
		OUT_DATA1_P: OUT std_logic;
		OUT_DATA1_N: OUT std_logic;
		IN_X_P: IN std_logic;
		IN_X_N: IN std_logic;
		-- Miscellaneous
		IN_BTN_TEST : IN std_logic				-- Test button (to avoid optimization)
	);
end Top;

architecture Behavioral of Top is

	COMPONENT IBUFDS
	PORT (
		O: OUT std_logic;
		I: IN std_logic;
		IB: IN std_logic
		);
	END COMPONENT;
	
	COMPONENT IBUFGDS
	PORT (
		O: OUT std_logic;
		I: IN std_logic;
		IB: IN std_logic
		);
	END COMPONENT;
	
	COMPONENT OBUFDS
	PORT (
		I: IN std_logic;
		O: OUT std_logic;
		OB: OUT std_logic
		);
	END COMPONENT;
	

	signal IN_CLK: std_logic := '0';				-- LVDS input: Clock
	signal IN_DATA0: std_logic := '0';			-- LVDS input: Data 0
	signal IN_DATA1: std_logic := '0';			-- LVDS input: Data 1
	signal IN_X: std_logic := '0';				-- LVDS input: signal not in scope
	signal OUT_CLK: std_logic := '0';			-- LVDS output: Clock
	signal OUT_DATA0: std_logic := '0';			-- LVDS output: Data 0
	signal OUT_DATA1: std_logic := '0';			-- LVDS output: Data 1
	signal OUT_X: std_logic := '0';				-- LVDS output: signal not in scope
	
	attribute box_type: string;
	attribute box_type of IBUFDS: component is "black_box";
	attribute box_type of IBUFGDS: component is "black_box";
	attribute box_type of OBUFDS: component is "black_box";
	attribute keep: string;
	attribute keep of IN_CLK: signal is "true";

begin

	Inst_IBUFGDS_CLK: IBUFGDS PORT MAP(
		O => IN_CLK,
		I => IN_CLK_P,
		IB => IN_CLK_N
		);

	Inst_IBUFDS_DATA0: IBUFDS PORT MAP(
		O => IN_DATA0,
		I => IN_DATA0_P,
		IB => IN_DATA0_N
		);
	Inst_IBUFDS_DATA1: IBUFDS PORT MAP(
		O => IN_DATA1,
		I => IN_DATA1_P,
		IB => IN_DATA1_N
		);
	Inst_IBUFDS_X: IBUFDS PORT MAP(
		O => IN_X,
		I => IN_X_P,
		IB => IN_X_N
		);

	Inst_OBUFDS_CLK: OBUFDS PORT MAP(
		I => OUT_CLK,
		O => OUT_CLK_P,
		OB => OUT_CLK_N
		);

	Inst_OBUFDS_DATA0: OBUFDS PORT MAP(
		I => OUT_DATA0,
		O => OUT_DATA0_P,
		OB => OUT_DATA0_N
		);

	Inst_OBUFDS_DATA1: OBUFDS PORT MAP(
		I => OUT_DATA1,
		O => OUT_DATA1_P,
		OB => OUT_DATA1_N
		);

	Inst_OBUFDS_X: OBUFDS PORT MAP(
		I => OUT_X,
		O => OUT_X_P,
		OB => OUT_X_N
		);

	
	OUT_DATA0 <= '0' when (IN_BTN_TEST = '1') else IN_DATA0;
	OUT_DATA1 <= '0' when (IN_BTN_TEST = '1') else IN_DATA1;
	OUT_X <= IN_X;

end Behavioral;