library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity Top is
	port (
		-- LVDS input
		IN_CLK_P: IN std_logic;					-- Clock is appr. 100 MHz
		IN_CLK_N: IN std_logic;
		IN_DATA0_P: IN std_logic;
		IN_DATA0_N: IN std_logic;
		IN_DATA1_P: IN std_logic;
		IN_DATA1_N: IN std_logic;
		OUT_X_P: OUT std_logic;
		OUT_X_N: OUT std_logic;
		-- LVDS output
		OUT_CLK_P: OUT std_logic;
		OUT_CLK_N: OUT std_logic;
		OUT_DATA0_P: OUT std_logic;
		OUT_DATA0_N: OUT std_logic;
		OUT_DATA1_P: OUT std_logic;
		OUT_DATA1_N: OUT std_logic;
		IN_X_P: IN std_logic;
		IN_X_N: IN std_logic;
		-- Miscellaneous
		IN_BTN_TEST : IN std_logic				-- Test button (to avoid optimization)
	);
end Top;

architecture Behavioral of Top is

signal IN_CLK: std_logic := '0';				-- LVDS input: Clock
signal IN_DATA0: std_logic := '0';			-- LVDS input: Data 0
signal IN_DATA1: std_logic := '0';			-- LVDS input: Data 1
signal IN_X: std_logic := '0';				-- LVDS input: signal not in scope
signal OUT_CLK: std_logic := '0';			-- LVDS output: Clock
signal OUT_DATA0: std_logic := '0';			-- LVDS output: Data 0
signal OUT_DATA1: std_logic := '0';			-- LVDS output: Data 1
signal OUT_X: std_logic := '0';				-- LVDS output: signal not in scope

begin

Inst_IBUFGDS_CLK: IBUFGDS PORT MAP(
	O => IN_CLK,
	I => IN_CLK_P,
	IB => IN_CLK_N
	);

Inst_IBUFDS_DATA0: IBUFDS PORT MAP(
	O => IN_DATA0,
	I => IN_DATA0_P,
	IB => IN_DATA0_N
	);
Inst_IBUFDS_DATA1: IBUFDS PORT MAP(
	O => IN_DATA1,
	I => IN_DATA1_P,
	IB => IN_DATA1_N
	);
Inst_IBUFDS_X: IBUFDS PORT MAP(
	O => IN_X,
	I => IN_X_P,
	IB => IN_X_N
	);

Inst_OBUFDS_CLK: OBUFDS PORT MAP(
	I => OUT_CLK,
	O => OUT_CLK_P,
	OB => OUT_CLK_N
	);

Inst_OBUFDS_DATA0: OBUFDS PORT MAP(
	I => OUT_DATA0,
	O => OUT_DATA0_P,
	OB => OUT_DATA0_N
	);

Inst_OBUFDS_DATA1: OBUFDS PORT MAP(
	I => OUT_DATA1,
	O => OUT_DATA1_P,
	OB => OUT_DATA1_N
	);

Inst_OBUFDS_X: OBUFDS PORT MAP(
	I => OUT_X,
	O => OUT_X_P,
	OB => OUT_X_N
	);

OUT_DATA0 <= '0' when IN_BTN_TEST = '1' else IN_DATA0;
OUT_DATA1 <= '0' when IN_BTN_TEST = '1' else IN_DATA1;
OUT_X <= IN_X;
OUT_CLK <= IN_CLK;

end Behavioral;