signal rst : STD_LOGIC; --------------------------------------------------------------------- -- DDR3-Controller --------------------------------------------------------------------- signal app_cmd : std_logic_vector(2 downto 0); signal app_en : std_logic; signal app_wdf_data : std_logic_vector(127 downto 0); signal app_wdf_end : std_logic; signal app_wdf_wren : std_logic; signal app_rd_data : std_logic_vector(127 downto 0); signal app_rd_data_end : std_logic; signal app_rd_data_valid : std_logic; signal app_rdy : std_logic; signal app_wdf_rdy : std_logic; signal app_sr_req : std_logic; signal app_ref_req : std_logic; signal app_zq_req : std_logic; signal app_sr_active : std_logic; signal app_ref_ack : std_logic; signal app_zq_ack : std_logic; signal ui_clk : std_logic; signal ui_clk_sync_rst : std_logic; signal app_wdf_mask : std_logic_vector(15 downto 0); signal app_addr : std_logic_vector(27 downto 0); -- System Clock Ports signal sys_clk_i : std_logic; -- Reference Clock Ports signal clk_ref_i : std_logic; signal device_temp : std_logic_vector(11 downto 0); signal init_calib_complete : std_logic; --------------------------------------------------------------------- -- PLL for DDR3-MIG --------------------------------------------------------------------- signal clk166 : std_logic; signal clk200 : std_logic; signal locked : std_logic; component mig_7series_0 port( ddr3_dq : inout std_logic_vector(15 downto 0); ddr3_dqs_p : inout std_logic_vector(1 downto 0); ddr3_dqs_n : inout std_logic_vector(1 downto 0); ddr3_addr : out std_logic_vector(13 downto 0); ddr3_ba : out std_logic_vector(2 downto 0); ddr3_ras_n : out std_logic; ddr3_cas_n : out std_logic; ddr3_we_n : out std_logic; ddr3_reset_n : out std_logic; ddr3_ck_p : out std_logic_vector(0 downto 0); ddr3_ck_n : out std_logic_vector(0 downto 0); ddr3_cke : out std_logic_vector(0 downto 0); ddr3_cs_n : out std_logic_vector(0 downto 0); ddr3_dm : out std_logic_vector(1 downto 0); ddr3_odt : out std_logic_vector(0 downto 0); app_addr : in std_logic_vector(27 downto 0); app_cmd : in std_logic_vector(2 downto 0); app_en : in std_logic; app_wdf_data : in std_logic_vector(127 downto 0); app_wdf_end : in std_logic; app_wdf_mask : in std_logic_vector(15 downto 0); app_wdf_wren : in std_logic; app_rd_data : out std_logic_vector(127 downto 0); app_rd_data_end : out std_logic; app_rd_data_valid : out std_logic; app_rdy : out std_logic; app_wdf_rdy : out std_logic; app_sr_req : in std_logic; app_ref_req : in std_logic; app_zq_req : in std_logic; app_sr_active : out std_logic; app_ref_ack : out std_logic; app_zq_ack : out std_logic; ui_clk : out std_logic; ui_clk_sync_rst : out std_logic; init_calib_complete : out std_logic; -- System Clock Ports sys_clk_i : in std_logic; -- Reference Clock Ports clk_ref_i : in std_logic; device_temp : out std_logic_vector(11 downto 0); sys_rst : in std_logic ); end component mig_7series_0; component clk_wiz_2 port (-- Clock in ports -- Clock out ports clk_out166 : out std_logic; clk_out200 : out STD_LOGIC; -- Status and control signals locked : out std_logic; clk_in1 : in std_logic ); end component; begin your_instance_name : clk_wiz_2 port map ( -- Clock out ports clk_out166 => clk166, clk_out200 => clk200, -- Status and control signals locked => locked, -- Clock in ports clk_in1 => clk100 ); u_mig_7series_0_mig : mig_7series_0 port map ( -- Memory interface ports ddr3_addr => ddr3_addr, ddr3_ba => ddr3_ba, ddr3_cas_n => ddr3_cas_n, ddr3_ck_n => ddr3_ck_n, ddr3_ck_p => ddr3_ck_p, ddr3_cke => ddr3_cke, ddr3_ras_n => ddr3_ras_n, ddr3_reset_n => ddr3_reset_n, ddr3_we_n => ddr3_we_n, ddr3_dq => ddr3_dq, ddr3_dqs_n => ddr3_dqs_n, ddr3_dqs_p => ddr3_dqs_p, ddr3_cs_n => ddr3_cs_n, ddr3_dm => ddr3_dm, ddr3_odt => ddr3_odt, -- Application interface ports init_calib_complete => init_calib_complete, app_addr => app_addr, app_cmd => app_cmd, app_en => app_en, app_wdf_data => app_wdf_data, app_wdf_end => app_wdf_end, app_wdf_wren => app_wdf_wren, app_rd_data => app_rd_data, app_rd_data_end => app_rd_data_end, app_rd_data_valid => app_rd_data_valid, app_rdy => app_rdy, app_wdf_rdy => app_wdf_rdy, app_sr_req => '0', app_ref_req => '0', --USER_REFRESH = OFF app_zq_req => '0', --tZQI = 128ms app_sr_active => open, app_ref_ack => open, app_zq_ack => open, ui_clk => ui_clk, ui_clk_sync_rst => ui_clk_sync_rst, app_wdf_mask => app_wdf_mask, -- System Clock Ports sys_clk_i => clk166, -- Reference Clock Ports clk_ref_i => clk200, device_temp => open, sys_rst => rst ); pb0 <= ui_clk; --> 0 pb1 <= ui_clk_sync_rst; --> 1 pb2 <= app_rdy; --> 0 pb3 <= app_wdf_rdy; --> 0 pb4 <= clk100; --> 100MHz pb5 <= clk166; --> 166MHz pb6 <= clk200; --> 200MHz pb7 <= rst; --> 0 pd(0) <= init_calib_complete; --> 0 pd(1) <= locked; --> 1 p2: process(ui_clk) is begin if rst = '1' then app_addr <= (OThers => '0'); --IN Current Address (27 downto 0) app_cmd <= "000"; --IN command for current request (001 = Read / 000 = Write) app_en <= '0'; --IN strobe for app_addr, app_cmd app_wdf_data <= (others => '0'); --IN Data for write-Commands (127 downto 0) app_wdf_end <= '0'; --IN current clock is last for app_wdf_data app_wdf_wren <= '0'; --IN Strobe for app_wdf_data app_wdf_mask <= x"ffff"; --IN MASK for app_wdf_data (15 downto 0) elsif rising_edge(ui_clk) THEN if ui_clk_sync_rst = '1' THEN else --processing if init_calib_complete = '1' THEN if app_rdy = '1' THEN app_en <= '1'; else app_en <= '0'; end if; if app_wdf_rdy = '1' THEN app_wdf_wren <= '1'; app_wdf_end <= '1'; else app_wdf_wren <= '0'; app_wdf_end <= '0'; end if; end if; end if; end if; end process; p1: process(clk100) is begin if rising_edge(clk100) then rst <= ((not rst_n) and locked); if rst /= '0' then else end if; end if; end process; end Behavioral;