library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

--use IEEE.std_logic_signed.all;
--use IEEE.std_logic_unsigned.all;
--use IEEE.STD_LOGIC_ARITH.ALL;

entity hvfg is
    --- Wo muss der hin constant IO_WIDTH : integer := 100;
    Port ( clk         : in   STD_LOGIC;
          reset        : in  std_logic;
          led0          : out  STD_LOGIC;
          led1          : out  STD_LOGIC;
          led2          : out  STD_LOGIC;
          spiclk        : in  std_logic;
          spimosi       : in  std_logic;
          switchleds   :  out std_logic_vector(19 downto 0);
          spimiso       : out  std_logic
          --switchleds   : out std_ulogic_vector(20 downto 0);
          -- sonicht switchleds   : out std_logic;
          --spiclk        : in  std_logic;
          --spimosi       : in  std_logic;
          --spimiso       : out  std_logic
         
          );
end hvfg;

-- 
architecture Behavioral of hvfg is
-- blinkdummy 
    signal zaehler    : integer range 0 to 10000000-1 := 0;
    signal logikpegel : std_logic := '0';
  
    --signal switchleds   :  std_ulogic_vector(20 downto 0);
          -- sonicht switchleds   : out std_logic;
    --signal spiclk        :  std_logic;
    --signal spimosi       :  std_logic;
    --signal spimiso       :   std_logic;
  
    type fsmstate is(idle,waitfor0,waitfor1);
    signal fsm         : fsmstate := idle;
    
    signal  indata_sulv : std_ulogic_vector(15 downto 0);  
    signal  indata_unsv : unsigned(20 downto 0);
    signal  indata_int  : integer range 0 to 20;  
    
    --signal outdata_sulv : std_ulogic_vector(15 downto 0);  
    signal outdata_temp : unsigned(15 downto 0) := "1000000000000001" ;
    signal outdata_sulv : std_logic_vector(15 downto 0) ;
    
    -- geht nich warumnurwarum signal outdata_sulv : std_ulogic_vector(15 downto 0) := "16#deadbeef#";  

    signal sig1        : integer;
    signal cnt         : integer range 0 to (2**32)-1;
    signal ind         : integer range 0 to (2**32)-1;
    signal i1          : natural range 0 to (2**32)-1;
    --variable ADDR_IN_INT : integer range 0 to 2**ADDR_WIDTH-1; 
    signal fsmcnt      : integer range 0 to (2**32)-1;
    
 
    ---output_1a <= std_logic_vector(to_unsigned(input_1, output_1a'length));
    --signal input_1   : integer;
    --signal output_1a : std_logic_vector(3 downto 0);
    --signal output_1b : std_logic_vector(3 downto 0);
    -- This line demonstrates how to convert positive integers
    --output_1a <= std_logic_vector(to_unsigned(input_1, output_1a'length));
    ---https://www.nandland.com/vhdl/tips/tip-convert-numeric-std-logic-vector-to-integer.html
    --signal input_4   : std_logic_vector(3 downto 0);
    --signal output_4a : integer;
    --signal output_4b : integer;
    --count <= (others => '0');
    -- if VECTOR = (15 downto 0=>'0') then..
    -- This line demonstrates the unsigned case
    --output_4a <= to_integer(unsigned(input_4));
    -- This line demonstrates the signed case
    --output_4b <= to_integer(signed(input_4));
    
begin

-- hier spielt die Musike
process (clk, reset)
  -- variable ??????????? 
  --variable cnt: integer range 0 to (2**32)-1;
  
begin
    if (reset = '1') then
	   cnt <= 0;
	   fsm <= idle;
	   outdata_sulv <= "1001010101010010";
    elsif (clk'event) and (clk='1') then
	    cnt <= cnt +1 ;
	   --switchleds(cnt mod 160) <= '0';
       ----------------------------
       case fsm is
         when idle =>
           if spiclk='1' then 
              fsm <= waitfor1; 
              ind <= 0;
              fsmcnt <= 0 ;
              i1 <= 0; 
           end if;  
       --------------------------------     
         when waitfor1 =>
           fsmcnt <= fsmcnt +1; 
           if fsmcnt > 10000 then --- timeout
               fsm <= idle;
           end if;       
           if spiclk='1' then
           spimiso <= '0'; 
              ind <= ind+1;              
              fsm <= waitfor0;
              i1 <= 1;
              spimiso <= outdata_sulv(i1);
              --i1 <=1;
              --spimiso <= spimosi;  
              --spimiso <= outdata_sulv(15-ind); 
              fsmcnt <= 0 ;
           end if;  
       --------------------------------     
         when waitfor0 =>
           fsmcnt <= fsmcnt +1; 
           if fsmcnt > 10000 then --- timeout
               fsm <= idle;
           end if;       
           if spiclk='0' then 
              indata_sulv(16-ind) <= spimosi;
              ---spimiso <= spimosi;
              --outdata_sulv <= std_logic_vector(outdata_temp);
              i1 <= 0;
              spimiso <= outdata_sulv(i1);
              fsm <= waitfor1; 
              fsmcnt <= 0 ; 
              -- das liegt am index
              -- outdata_sulv <= "1000000000000001";
              -- spimiso <= outdata_sulv(14);  
              if ind = 16 then -- fettich
               -- -- hier muss ne Redundanz rein
                fsm <= idle; 
                indata_unsv <= unsigned(indata_sulv);
                indata_int  <= to_integer(indata_unsv);
                --switchleds(indata_int) <= '1';
                --switchleds(indata_int) <= indata_sulv(9);
              end if;  
           end if;  
       end case;   
       -------------------------------------------          
	   if( cnt > 50000) then
		  cnt <= 0;
	   end if ; 
	   ---------------------------------------------
	 end if;
end process ;

-- blinkdummy    
process begin
  wait until rising_edge(clk);
    if (zaehler<10000000-1) then
        zaehler <= zaehler+1;
    else
        zaehler <= 0;
        logikpegel <= not logikpegel;
    end if;
    switchleds(19) <= logikpegel;
    switchleds(18) <= logikpegel;
    switchleds(17) <= logikpegel;
    switchleds(16) <= logikpegel;
    switchleds(15) <= logikpegel;
    switchleds(14) <= logikpegel;
    switchleds(13) <= logikpegel;
    switchleds(12) <= logikpegel;
    switchleds(11) <= logikpegel;
    switchleds(10) <= logikpegel;
    switchleds(9) <= logikpegel;
    switchleds(8) <= logikpegel;
    switchleds(7) <= logikpegel;
    switchleds(6) <= logikpegel;
    switchleds(5) <= logikpegel;
    switchleds(4) <= logikpegel;
    switchleds(3) <= logikpegel;
    switchleds(2) <= logikpegel;
    switchleds(1) <= logikpegel;
    switchleds(0) <= logikpegel;
    led0 <= logikpegel;
    led1 <= logikpegel;
    led2 <= logikpegel;
end process;
 
        
end Behavioral;