library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity PWM is
	port(
		clk                 : in  std_logic;
		input               : in  std_logic;
		output              : out std_logic
	);
end PWM;

architecture rtl of PWM is

component MMCM is
	port(
		clk_in              : in  std_logic;
		clk_out_x1          : out std_logic;
		clk_out_x10         : out std_logic
	);
end component;

signal clk_x1               : std_logic := '0';
signal clk_x10              : std_logic := '0';
signal clk_x1_sr            : std_logic_vector(4 downto 0) := (others => '0');
signal input_q              : std_logic := '0';
signal counter              : unsigned(3 downto 0) := (others => '0');

begin

inst_MMCM : MMCM
	port map(
		clk_in              => clk,
		clk_out_x1          => clk_x1,
		clk_out_x10         => clk_x10
	);

process begin
	wait until rising_edge(clk_x10);
	clk_x1_sr               <= clk_x1_sr(3 downto 0) & clk;
	if clk_x1_sr = "10000" then
		input_q             <= input;
	end if;
	
	if clk_x1_sr = "00000" then
		counter             <= (others => '0');
	else
		counter             <= counter +1;
	end if;
	
	output                  <= '0';
	if input_q = '1' and counter = 8 then
		output              <= '1';
	end if;

	if input_q = '0' and counter /= 9 then
		output              <= '1';
	end if;

end process;

end;