library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity tb_PWM is
end tb_PWM;

architecture tb of tb_PWM is

component PWM is
	port(
		clk    : in  std_logic;
		input  : in  std_logic;
		output : out std_logic
	);
end component;

signal clk    : std_logic := '1';
signal input  : std_logic := '0';
signal output : std_logic := '0';

begin

clk <= not clk after 5 ns;
input <= not input after 49 ns;

inst_PWM : PWM
	port map(
		clk    => clk,
		input  => input,
		output => output
	);

end;