library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity count is
    port
    (
        clk   : in std_logic;
        reset : in std_logic;
        S_1   : in std_logic; --sensor signal
        q     : out integer range 0 to 2147483647; --32bit    -- 16 bit 65535
        y     : out std_logic
    );
end entity;

architecture rtl of count is

begin

process (clk)
    variable cnt : integer range 0 to 2147483647;  
begin
    if (rising_edge(clk)) then
        if (reset = '1') then
            cnt := 0;
        elsif (S_1 = '1') then
            cnt := cnt + 1;
            y <= '0';
        end if;
    end if;
    q <= cnt;
end process;

end;