library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity INT_TO_BCD is
    port
    (
        q       : in  integer range 0 to 2147483647;
        BCD_OUT : out STD_LOGIC_VECTOR (3 downto 0)
    );
end INT_TO_BCD;

architecture arch of INT_TO_BCD is

begin

process (q) begin
    case q is
        when 0 => BCD_OUT <= "0000";
        when 1 => BCD_OUT <= "0001";
        when 2 => BCD_OUT <= "0010";
        when 3 => BCD_OUT <= "0011";
        when 4 => BCD_OUT <= "0100";
        when 5 => BCD_OUT <= "0101";
        when 6 => BCD_OUT <= "0110";
        when 7 => BCD_OUT <= "0111";
        when 8 => BCD_OUT <= "1000";
        when 9 => BCD_OUT <= "1001";
        when others => BCD_OUT <= "1110";
    end case;
end process;

end;