library ieee;
use ieee.std_logic_1164.all;
use IEEE.NUMERIC_STD.all;

entity Seg7_Comp is
    port
    (
        S_1    : in  std_logic;
        led_o  : out std_logic_vector(6 downto 0);
        reset  : in  std_logic;
        areset : in  std_logic;
        inclk0 : in  std_logic;
        y      : out std_logic;
        locked : out std_logic
    );
end Seg7_Comp;

architecture arch of Seg7_Comp is

component count is
    port
    (
        clk   : in std_logic;
        reset : in std_logic;
        S_1   : in std_logic; --sensor signal
        q     : out integer range 0 to 2147483647; --32bit    -- 16 bit 65535
        y     : out std_logic
    );
end component;

component INT_TO_BCD is
    port
    (
        q       : in  integer range 0 to 2147483647;
        BCD_OUT : out STD_LOGIC_VECTOR (3 downto 0)
    );
end component;

component BCD_TO_7SEG is
    port
    (
        BCD_IN : in  std_logic_vector(3 downto 0); -- nur fuer simmulation stdlogic  ueberall
        a      : out std_logic;
        b      : out std_logic;
        c      : out std_logic;
        d      : out std_logic;
        e      : out std_logic;
        f      : out std_logic;
        g      : out std_logic
    );
end component;

signal c0      : std_logic := '0';
signal q       : integer range 0 to 2147483647 := 0;
signal BCD     : std_logic_vector(3 downto 0) := (others => '0');

begin

-- DUMMY clock component
c0     <= inclk0;
locked <= '1';

inst_count : count
    port map
    (
        clk   => c0,
        reset => reset,
        S_1   => S_1,
        q     => q,
        y     => y
    );

inst_INT_TO_BCD : INT_TO_BCD
    port map
    (
        q       => q,
        BCD_OUT => BCD
    );

inst_BCD_TO_7SEG : BCD_TO_7SEG
    port map
    (
        BCD_IN => BCD,
        a      => led_o(6),
        b      => led_o(5),
        c      => led_o(4),
        d      => led_o(3),
        e      => led_o(2),
        f      => led_o(1),
        g      => led_o(0)
    );

end;