library ieee;
use ieee.std_logic_1164.all;

entity tb_Seg7_Comp is
end tb_Seg7_Comp;

architecture tb of tb_Seg7_Comp is

component Seg7_Comp
    port
    (
        S_1    : in  std_logic;
        led_o  : out std_logic_vector (6 downto 0);
        reset  : in  std_logic;
        areset : in  std_logic;
        inclk0 : in  std_logic;
        y      : out std_logic;
        locked : out std_logic
    );
end component;

constant ClockPeriod : time := 10 ns; -- 100 MHz

signal S_1    : std_logic := '0';
signal led_o  : std_logic_vector (6 downto 0) := (others => '0');
signal reset  : std_logic := '0';
signal areset : std_logic := '0';
signal inclk0 : std_logic := '0';
signal y      : std_logic := '0';
signal locked : std_logic := '0';

begin

inclk0 <= not inclk0 after ClockPeriod/2;

process begin
	wait for 1 us;
	for i in 0 to 15 loop
		S_1 <= '1';
		wait for 100 ns;
		S_1 <= '0';
		wait for 400 ns;
	end loop;
	wait;
end process;

UUT : Seg7_Comp
    port map
    (
        S_1    => S_1,
        led_o  => led_o,
        reset  => reset,
        areset => areset,
        inclk0 => inclk0,
        y      => y,
        locked => locked
    );

end;