Design Name | minilog |
Fitting Status | Successful |
Software Version | J.33 |
Device Used | XC9572-7-TQ100 |
Date | 7- 8-2009, 10:39AM |
Macrocells Used | Pterms Used | Registers Used | Pins Used | Function Block Inputs Used |
---|---|---|---|---|
39/72 (55%) | 102/360 (29%) | 29/72 (41%) | 53/72 (74%) | 79/144 (55%) |
|
|
Signal mapped onto global clock net (GCK1) | clk_80 |
Macrocells in high performance mode (MCHP) | 39 |
Macrocells in low power mode (MCLP) | 0 |
Total macrocells used (MC) | 39 |