#include #include #include #include #include #include "rfm69registers.h" #include "spi.h" #define _XTAL_FREQ 1000000 volatile char bufferflag = 0; void init_spi() { //RB4 is clock , RB6 is SDI miso , RC2 enable, RB7 is SDO mosi , rc7 chip select, rc6 reset SSP1CON1bits.SSPEN = 0; //disable serial port SSP1CON1bits.CKP = 0; //clock idle is low SSP1CON1bits.SSPM = 0b0000; //clock = fosc/4 SSP1STATbits.CKE = 1; // TRISBbits.TRISB6 = 1; TRISBbits.TRISB7 = 0; TRISBbits.TRISB4 = 0; TRISCbits.TRISC7 = 0; TRISCbits.TRISC2 = 0; LATCbits.LATC7 = 1; // pull up chip select LATCbits.LATC2 = 0; RB4PPS = 0x07; RB7PPS = 0x08; SSP1DATPPS = 1; //pps on rb6 miso //?? SSP1CON1bits.SSPEN = 1; //enable serial port } void rfm_standby() { LATCbits.LATC7 = 0; // pull down chip select SSP1BUF = 0b10000001; while (!SSP1STATbits.BF); SSP1BUF = 0x84; //old 0x04 while (!SSP1STATbits.BF); LATCbits.LATC7 = 1; // pull up chip select } void rfm_sendframe (char data ) { LATCbits.LATC7 = 0; // pull down chip select SSP1BUF = 0x80; while (!SSP1STATbits.BF); SSP1BUF = 1; while (!SSP1STATbits.BF); SSP1BUF = (uint8_t)1; //receiver id while (!SSP1STATbits.BF); SSP1BUF = (uint8_t)2; //sender id while (!SSP1STATbits.BF); SSP1BUF = 0; while (!SSP1STATbits.BF); SSP1BUF = (uint8_t)data; while (!SSP1STATbits.BF); LATCbits.LATC7 = 1; // pull up chip select rfm_txmode(); __delay_ms(100); rfm_standby(); } void rfm_txmode() { LATCbits.LATC7 = 0; // pull down chip select SSP1BUF = 0b10000001; while (!SSP1STATbits.BF); SSP1BUF = 0x8C; while (!SSP1STATbits.BF); LATCbits.LATC7 = 1; // pull up chip select } void rfm_txpwr_high() { LATCbits.LATC7 = 0; // pull down chip select SSP1BUF = 0x11|0x80; while (!SSP1STATbits.BF); SSP1BUF = 0xFF; //old 7F while (!SSP1STATbits.BF); SSP1BUF = 0x13|0x80; while (!SSP1STATbits.BF); SSP1BUF = 0x1F; //old 0F while (!SSP1STATbits.BF); SSP1BUF = 0x5A|0x80; while (!SSP1STATbits.BF); SSP1BUF = 0x55; //old 0x5D while (!SSP1STATbits.BF); SSP1BUF = 0x5C|0x80; while (!SSP1STATbits.BF); SSP1BUF = 0x7C; while (!SSP1STATbits.BF); LATCbits.LATC7 = 1; // pull up chip select } void rfm_test () { //should return 0x24 on miso LATCbits.LATC7 = 0; // pull down chip select SSP1BUF = 0x10; while (!SSP1STATbits.BF); SSP1BUF = 0x00; while (!SSP1STATbits.BF); LATCbits.LATC7 = 1; // pull up chip select } void rfm_init () { //rfm_standby(); __delay_ms(10); rfm_configs(); //rfm_txpwr_high(); __delay_ms(10); //rfm_txmode(); } void rfm_reg_write(uint8_t address , uint8_t data) { LATCbits.LATC7 = 0; // pull down chip select SSP1BUF = address|0x80; while (!SSP1STATbits.BF); SSP1BUF = data; while (!SSP1STATbits.BF); LATCbits.LATC7 = 1; // pull up chip select } /*void rfm_encrypt(void) { LATCbits.LATC7 = 0; // pull down chip select SSP1BUF = 0x3E|0x80; while (!SSP1STATbits.BF); for (int j = 0; j<16;j++) { SSP1BUF = 1; while (!SSP1STATbits.BF); } LATCbits.LATC7 = 1; // pull up chip select } */ void rfm_configs(void) { const uint8_t CONFIG[][2] = { /* 0x01 */ {REG_OPMODE, RF_OPMODE_SEQUENCER_ON | RF_OPMODE_LISTEN_OFF | RF_OPMODE_STANDBY}, /* 0x02 */ {REG_DATAMODUL, RF_DATAMODUL_DATAMODE_PACKET | RF_DATAMODUL_MODULATIONTYPE_FSK | RF_DATAMODUL_MODULATIONSHAPING_00}, // no shaping /* 0x03 */ {REG_BITRATEMSB, RF_BITRATEMSB_55555}, // default: 4.8 KBPS /* 0x04 */ {REG_BITRATELSB, RF_BITRATELSB_55555}, /* 0x05 */ {REG_FDEVMSB, RF_FDEVMSB_50000}, // default: 5KHz, (FDEV + BitRate / 2 <= 500KHz) /* 0x06 */ {REG_FDEVLSB, RF_FDEVLSB_50000}, /* 0x07 */ {REG_FRFMSB, RF_FRFMSB_433}, /* 0x08 */ {REG_FRFMID,RF_FRFMID_433}, /* 0x09 */ {REG_FRFLSB, RF_FRFLSB_433}, // looks like PA1 and PA2 are not implemented on RFM69W/CW, hence the max output power is 13dBm // +17dBm and +20dBm are possible on RFM69HW // +13dBm formula: Pout = -18 + OutputPower (with PA0 or PA1**) // +17dBm formula: Pout = -14 + OutputPower (with PA1 and PA2)** // +20dBm formula: Pout = -11 + OutputPower (with PA1 and PA2)** and high power PA settings (section 3.3.7 in datasheet) ///* 0x11 */ { REG_PALEVEL, RF_PALEVEL_PA0_ON | RF_PALEVEL_PA1_OFF | RF_PALEVEL_PA2_OFF | RF_PALEVEL_OUTPUTPOWER_11111}, ///* 0x13 */ { REG_OCP, RF_OCP_ON | RF_OCP_TRIM_95 }, // over current protection (default is 95mA) // RXBW defaults are { REG_RXBW, RF_RXBW_DCCFREQ_010 | RF_RXBW_MANT_24 | RF_RXBW_EXP_5} (RxBw: 10.4KHz) /* 0x19 */ {REG_RXBW, RF_RXBW_DCCFREQ_010 | RF_RXBW_MANT_16 | RF_RXBW_EXP_2}, // (BitRate < 2 * RxBw) // for BR-19200: /* 0x19 */ { REG_RXBW, RF_RXBW_DCCFREQ_010 | RF_RXBW_MANT_24 | RF_RXBW_EXP_3 }, /* 0x25 */ {REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_01}, // DIO0 is the only IRQ we're using /* 0x26 */ {REG_DIOMAPPING2, RF_DIOMAPPING2_CLKOUT_OFF}, // DIO5 ClkOut disable for power saving /* 0x28 */ {REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN}, // writing to this bit ensures that the FIFO & status flags are reset /* 0x29 */ {REG_RSSITHRESH, 220}, // must be set to dBm = (-Sensitivity / 2), default is 0xE4 = 228 so -114dBm ///* 0x2D */ { REG_PREAMBLELSB, RF_PREAMBLESIZE_LSB_VALUE } // default 3 preamble bytes 0xAAAAAA /* 0x2E */ {REG_SYNCCONFIG, RF_SYNC_ON | RF_SYNC_FIFOFILL_AUTO | RF_SYNC_SIZE_2 | RF_SYNC_TOL_0}, /* 0x2F */ {REG_SYNCVALUE1, 0x2D}, // attempt to make this compatible with sync1 byte of RFM12B lib /* 0x30 */ {REG_SYNCVALUE2, 100}, // NETWORK ID //* 0x31 */ { REG_SYNCVALUE3, 0xAA }, //* 0x31 */ { REG_SYNCVALUE4, 0xBB }, /* 0x37 */ {REG_PACKETCONFIG1, RF_PACKET1_FORMAT_VARIABLE | RF_PACKET1_DCFREE_OFF | RF_PACKET1_CRC_ON | RF_PACKET1_CRCAUTOCLEAR_ON | RF_PACKET1_ADRSFILTERING_OFF}, /* 0x38 */ {REG_PAYLOADLENGTH, 66}, // in variable length mode: the max frame size, not used in TX ///* 0x39 */ { REG_NODEADRS, nodeID }, // turned off because we're not using address filtering /* 0x3C */ {REG_FIFOTHRESH, RF_FIFOTHRESH_TXSTART_FIFONOTEMPTY | RF_FIFOTHRESH_VALUE}, // TX on FIFO not empty /* 0x3D */ {REG_PACKETCONFIG2, RF_PACKET2_RXRESTARTDELAY_2BITS | RF_PACKET2_AUTORXRESTART_OFF | RF_PACKET2_AES_OFF}, // RXRESTARTDELAY must match transmitter PA ramp-down time (bitrate dependent) // for BR-19200: /* 0x3D */ { REG_PACKETCONFIG2, RF_PACKET2_RXRESTARTDELAY_NONE | RF_PACKET2_AUTORXRESTART_ON | RF_PACKET2_AES_OFF }, // RXRESTARTDELAY must match transmitter PA ramp-down time (bitrate dependent) /* 0x6F */ {REG_TESTDAGC, RF_DAGC_IMPROVED_LOWBETA0}, // run DAGC continuously in RX mode for Fading Margin Improvement, recommended default for AfcLowBetaOn=0 {255, 0}}; //rfm_reg_write(0x2f,0xAA); //__delay_ms(10); // rfm_reg_write(0x30,0x55); //__delay_ms(100); for (uint8_t i = 0; CONFIG[i][0] != 255; i++) { rfm_reg_write(CONFIG[i][0], CONFIG[i][1]); } // rfm_reg_write(0x13,0x0F); // rfm_txpwr_high(); __delay_ms(100); //rfm_standby(); //LATCbits.LATC2 = 1; }