library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity split_digits is
	port
	(
		i_clk                : in    std_logic;
		i_start              : in    std_logic;
		i_number             : in    std_logic_vector(9 downto 0);
		o_digits             : out   std_logic_vector(11 downto 0);
		o_busy               : out   std_logic
	);
end split_digits;

architecture rtl of split_digits is

signal s_counter             : unsigned(9 downto 0) := (others => '0');
signal s_digits              : std_logic_vector(11 downto 0) := (others => '0');

begin

o_busy                       <= '1' when i_start = '1' or s_counter > 0 else '0';
o_digits                     <= s_digits;

process begin
	wait until rising_edge(i_clk);
	if s_counter > 0 then
		s_counter <= s_counter - 1;
	else
		if i_start = '1' then
			s_counter <= unsigned(i_number);
		end if;
	end if;
	
	if s_counter > 0 then
		if unsigned(s_digits(3 downto 0)) < 9 then
			s_digits(3 downto 0) <= std_logic_vector(unsigned(s_digits(3 downto 0)) + 1);
		else
			s_digits(3 downto 0) <= (others => '0');
			
			if unsigned(s_digits(7 downto 4)) < 9 then
				s_digits(7 downto 4) <= std_logic_vector(unsigned(s_digits(7 downto 4)) + 1);
			else
				s_digits(7 downto 4) <= (others => '0');
			
				if unsigned(s_digits(11 downto 8)) < 9 then
					s_digits(11 downto 8) <= std_logic_vector(unsigned(s_digits(11 downto 8)) + 1);
				else
					s_digits(11 downto 8) <= (others => '0');
				end if;
			end if;
		end if;
	end if;

end process;

end;