library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.NUMERIC_STD.all;

entity tb_split_digits is
end tb_split_digits;

architecture tb of tb_split_digits is

signal s_clk                 : std_logic := '0';
signal s_start               : std_logic := '0';
signal s_number              : std_logic_vector(9 downto 0) := std_logic_vector(to_unsigned(532,10));
signal s_digits              : std_logic_vector(11 downto 0) := (others => '0');
signal s_busy                : std_logic := '0';

begin

s_clk                        <= not s_clk after 5 ns;

process begin
	wait for 100 ns;
	s_start <= '1';
	wait for 10 ns;
	s_start <= '0';
	wait;
end process;

inst_split_digits : entity work.split_digits
	port map
	(
		i_clk                => s_clk,
		i_start              => s_start,
		i_number             => s_number,
		o_digits             => s_digits,
		o_busy               => s_busy
	);

end;