library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity tb_aufgabe3 is
end tb_aufgabe3;

architecture tb of tb_aufgabe3 is

component aufgabe3 is
	Port
	(	CLK, S0, S1, S2, S4, S3 : in std_logic;
		D : in unsigned(4 downto 0);
		Q : out unsigned(4 downto 0)
	);
end component;

signal CLK : std_logic := '0';
signal S0  : std_logic := '0';
signal S1  : std_logic := '0';
signal S2  : std_logic := '0';
signal S3  : std_logic := '0';
signal S4  : std_logic := '0';
signal D   : unsigned(4 downto 0) := (others => '0');
signal Q   : unsigned(4 downto 0) := (others => '0');


signal counter_reset     : std_logic := '0';
signal counter_clear     : std_logic := '0';
signal counter_not_load  : std_logic := '1';
signal counter_enable    : std_logic := '0';
signal counter_direction : std_logic := '0';

begin

CLK <= not CLK after 5 ns;
S0  <= counter_reset;
S1  <= counter_clear;
S2  <= counter_not_load;
S3  <= counter_enable;
S4  <= counter_direction;

process begin
	wait for 100 ns;
	counter_reset <= '1';
	wait for 10 ns;
	counter_reset <= '0';
	wait for 10 ns;
	D <= to_unsigned(26,5);
	wait for 10 ns;
	counter_not_load <= '0';
	wait for 10 ns;
	counter_not_load <= '1';
	wait for 10 ns;
	counter_direction <= '1';
	wait for 10 ns;
	counter_enable <= '1';
	wait for 130 ns;
	counter_direction <= '0';
	wait for 50 ns;
	counter_enable <= '0';
	wait for 10 ns;
	counter_clear <= '1';
	wait for 10 ns;
	counter_clear <= '0';
	wait for 10 ns;
	counter_direction <= '1';
	wait for 10 ns;
	counter_enable <= '1';
	wait for 400 ns;
	wait;
end process;

inst_aufgabe3 : aufgabe3
	Port map
	(
		CLK => CLK,
		S0  => S0, 
		S1  => S1, 
		S2  => S2, 
		S3  => S3, 
		S4  => S4, 
		D   => D,  
		Q   => Q  
	);

end;