library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity karnaughtafel is
  port (a, b, c, d : in  std_logic;
        y          : out std_logic);
end karnaughtafel;

architecture verhalten of karnaughtafel is

  signal all_inputs : std_logic_vector(3 downto 0);
begin

  all_inputs <= a & b & c & d;

  with all_inputs select
    y <=
    '1'      when "0000",
    '1'      when "0001",
    '1'      when "0011",
    '1'      when "0010",
    --
    '1'      when "0100",
    '1'      when "0101",
    '1'      when "0111",
    '1'      when "0110",
    --
    '1'      when "1100",
    '1'      when "1101",
    '1'      when "1111",
    '1'      when "1110",
    --
    '1'      when "1000",
    '1'      when "1001",
    '1'      when "1011",
    '1'      when "1010",
    'X'      when others;
end verhalten;