library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity seven_segment is -- nur eine einzige Anzeige. Kann man die verschachteln nachher und als dez Anzeige verwalten? Port ( clk : in std_logic; data : in std_logic_vector(3 downto 0); segments : out std_logic_vector(6 downto 0); enable : out std_logic; oe : in std_logic); end seven_segment; architecture Behavioral of seven_segment is signal data_int : std_logic_vector(3 downto 0); begin process begin wait until rising_edge(clk); case data_int is -- da ich ohnehin noch keine hardware habe, scheint mir das ausreichend when "0000" => segments <= "0000000"; when "0001" => segments <= "0000001"; when "0010" => segments <= "0000011"; when "0011" => segments <= "0000111"; when "0100" => segments <= "0001111"; when "0101" => segments <= "0011111"; when "0110" => segments <= "0111111"; when "0111" => segments <= "1111111"; when others => segments <= "0000000"; end case; if (oe = '1') then enable <= '1'; else enable <= '0'; end if; end process; data_int <= data; end Behavioral; library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity counter is generic(width : natural := 4);-- vielleicht klappts ja später, längere Anzeigen zu kaskadieren port( clk : in std_logic; count : out std_logic_vector(width-1 downto 0)); end counter; architecture Behavioral of counter is component seven_segment Port ( clk : in std_logic; data : in std_logic_vector(3 downto 0); segments : out std_logic_vector(6 downto 0); enable : out std_logic; oe : in std_logic); end component; signal count_int : std_logic_vector(width-1 downto 0); begin process begin wait until rising_edge(clk); count_int <= count_int + 1; end process; anz : seven_segment port map( clk => clk, data => count, oe => '1'); count <= count_int; end Behavioral;