TestOszi Project Status (07/24/2009 - 10:59:53)
Project File: TestOszi.ise Implementation State: Programming File Generated
Module Name: spartan3AN_test
  • Errors:
No Errors
Target Device: xc3s700an-4fgg484
  • Warnings:
16 Warnings
Product Version:ISE 11.1
  • Routing Results:
All Signals Completely Routed
Design Goal: Balanced
  • Timing Constraints:
All Constraints Met
Design Strategy: Xilinx Default (unlocked)
  • Final Timing Score:
0 (Setup: 0, Hold: 0) (Timing Report)
 
Device Utilization Summary [-]
Logic UtilizationUsedAvailableUtilizationNote(s)
Number of Slice Flip Flops 47 11,776 1%  
Number of 4 input LUTs 91 11,776 1%  
Number of occupied Slices 49 5,888 1%  
    Number of Slices containing only related logic 49 49 100%  
    Number of Slices containing unrelated logic 0 49 0%  
Total Number of 4 input LUTs 91 11,776 1%  
Number of bonded IOBs 6 372 1%  
Number of BUFGMUXs 1 24 4%  
Average Fanout of Non-Clock Nets 3.85      
 
Performance Summary [-]
Final Timing Score: 0 (Setup: 0, Hold: 0) Pinout Data: Pinout Report
Routing Results: All Signals Completely Routed Clock Data: Clock Report
Timing Constraints: All Constraints Met    
 
Detailed Reports [-]
Report NameStatusGenerated ErrorsWarningsInfos
Synthesis ReportCurrentFr 24. Jul 10:59:11 2009016 Warnings0
Translation ReportCurrentFr 24. Jul 10:59:17 2009000
Map ReportCurrentFr 24. Jul 10:59:22 2009002 Infos
Place and Route ReportCurrentFr 24. Jul 10:59:38 2009003 Infos
Power Report     
Post-PAR Static Timing ReportCurrentFr 24. Jul 10:59:42 2009003 Infos
Bitgen ReportCurrentFr 24. Jul 10:59:51 2009000
 
Secondary Reports [-]
Report NameStatusGenerated
ISIM Simulator LogOut of DateFr 24. Jul 10:45:24 2009

Date Generated: 07/24/2009 - 10:59:53