TestOszi Project Status (07/24/2009 - 10:59:53) | |||
Project File: | TestOszi.ise | Implementation State: | Programming File Generated |
Module Name: | spartan3AN_test |
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No Errors |
Target Device: | xc3s700an-4fgg484 |
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16 Warnings |
Product Version: | ISE 11.1 |
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All Signals Completely Routed |
Design Goal: | Balanced |
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All Constraints Met |
Design Strategy: | Xilinx Default (unlocked) |
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0 (Setup: 0, Hold: 0) (Timing Report) |
Device Utilization Summary | [-] | ||||
Logic Utilization | Used | Available | Utilization | Note(s) | |
Number of Slice Flip Flops | 47 | 11,776 | 1% | ||
Number of 4 input LUTs | 91 | 11,776 | 1% | ||
Number of occupied Slices | 49 | 5,888 | 1% | ||
Number of Slices containing only related logic | 49 | 49 | 100% | ||
Number of Slices containing unrelated logic | 0 | 49 | 0% | ||
Total Number of 4 input LUTs | 91 | 11,776 | 1% | ||
Number of bonded IOBs | 6 | 372 | 1% | ||
Number of BUFGMUXs | 1 | 24 | 4% | ||
Average Fanout of Non-Clock Nets | 3.85 |
Performance Summary | [-] | |||
Final Timing Score: | 0 (Setup: 0, Hold: 0) | Pinout Data: | Pinout Report | |
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report | |
Timing Constraints: | All Constraints Met |
Detailed Reports | [-] | |||||
Report Name | Status | Generated | Errors | Warnings | Infos | |
Synthesis Report | Current | Fr 24. Jul 10:59:11 2009 | 0 | 16 Warnings | 0 | |
Translation Report | Current | Fr 24. Jul 10:59:17 2009 | 0 | 0 | 0 | |
Map Report | Current | Fr 24. Jul 10:59:22 2009 | 0 | 0 | 2 Infos | |
Place and Route Report | Current | Fr 24. Jul 10:59:38 2009 | 0 | 0 | 3 Infos | |
Power Report | ||||||
Post-PAR Static Timing Report | Current | Fr 24. Jul 10:59:42 2009 | 0 | 0 | 3 Infos | |
Bitgen Report | Current | Fr 24. Jul 10:59:51 2009 | 0 | 0 | 0 |
Secondary Reports | [-] | ||
Report Name | Status | Generated | |
ISIM Simulator Log | Out of Date | Fr 24. Jul 10:45:24 2009 |